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Michael Brown 592755eccf [realtek] Allow reaction time between writing RTL_CAPR and reading RTL_CR

Some older RTL8139 chips seem to not immediately update the
RTL_CR.BUFE bit in response to a write to RTL_CAPR.  This results in
iPXE seeing a spurious zero-length received packet, and thereafter
being out of sync with the hardware's RX ring offset.

Fix by inserting an extra PCI read cycle after writing to RTL_CAPR, to
give the chip time to react before we next read RTL_CR.

Reported-by: Gelip <mrgelip@gmail.com>
Tested-by: Gelip <mrgelip@gmail.com>
Signed-off-by: Michael Brown <mcb30@ipxe.org>

2013-04-30 13:42:12 +01:00

contrib

[errdb] Strip platform error code for non-platform-generated errors

2013-04-29 15:36:32 +01:00

src

[realtek] Allow reaction time between writing RTL_CAPR and reading RTL_CR

2013-04-30 13:42:12 +01:00

COPYING

Initial revision

2005-05-17 16:44:57 +00:00

COPYRIGHTS

[build] Rename gPXE to iPXE

2010-04-19 23:43:39 +01:00

README

[doc] Re-add README file

2010-05-28 00:03:47 +01:00

README

iPXE README File

Quick start guide:

   cd src
   make

For any more detailed instructions, see http://ipxe.org

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