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[realtek] Allow reaction time between writing RTL_CAPR and reading RTL_CR

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Some older RTL8139 chips seem to not immediately update the
RTL_CR.BUFE bit in response to a write to RTL_CAPR.  This results in
iPXE seeing a spurious zero-length received packet, and thereafter
being out of sync with the hardware's RX ring offset.

Fix by inserting an extra PCI read cycle after writing to RTL_CAPR, to
give the chip time to react before we next read RTL_CR.

Reported-by: Gelip <mrgelip@gmail.com>
Tested-by: Gelip <mrgelip@gmail.com>
Signed-off-by: Michael Brown <mcb30@ipxe.org>
This commit is contained in:
Michael Brown 2013-04-30 13:36:04 +01:00
parent e411b37eb1
commit 592755eccf
1 changed files with 3 additions and 0 deletions
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3
src/drivers/net/realtek.c
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@ -861,6 +861,9 @@ static void realtek_legacy_poll_rx ( struct net_device *netdev ) {
rtl->rx_offset = ( ( rtl->rx_offset + 3 ) & ~3 );
rtl->rx_offset = ( rtl->rx_offset % RTL_RXBUF_LEN );
writew ( ( rtl->rx_offset - 16 ), rtl->regs + RTL_CAPR );
/* Give chip time to react before rechecking RTL_CR */
readw ( rtl->regs + RTL_CAPR );
}
}