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[realtek] Clear bit 24 of RCR

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On an Asus Z87-K motherboard with an onboard 8168 NIC, booting into
Windows 7 and then warm rebooting into iPXE results in a broken RX
datapath: packets can be transmitted successfully but garbage is
received.  A cold reboot clears the problem.

A dump of the PHY registers reveals only one difference: in the
failure case the bits ADVERTISE_PAUSE_CAP and ADVERTISE_PAUSE_ASYM are
cleared.  Explicitly setting these bits does not fix the problem.

A dump of the MAC registers reveals a few differences, of which the
most obvious culprit is the undocumented bit 24 of the Receive
Configuration Register (RCR), which is set in the failure case.
Explicitly clearing this bit does fix the problem.

Reported-by: Sebastian Nielsen <ipxe@sebbe.eu>
Reported-by: Oliver Rath <rath@mglug.de>
Debugged-by: Sebastian Nielsen <ipxe@sebbe.eu>
Tested-by: Sebastian Nielsen <ipxe@sebbe.eu>
Signed-off-by: Michael Brown <mcb30@ipxe.org>
This commit is contained in:
Michael Brown 2014-03-17 17:15:18 +00:00
parent 87b59677ba
commit ccb6e5c627
2 changed files with 3 additions and 2 deletions
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4
src/drivers/net/realtek.c
View File

@ -708,8 +708,8 @@ static int realtek_open ( struct net_device *netdev ) {
/* Configure receiver */
rcr = readl ( rtl->regs + RTL_RCR );
rcr &= ~( RTL_RCR_RXFTH_MASK | RTL_RCR_RBLEN_MASK |
RTL_RCR_MXDMA_MASK );
rcr &= ~( RTL_RCR_STOP_WORKING | RTL_RCR_RXFTH_MASK |
RTL_RCR_RBLEN_MASK | RTL_RCR_MXDMA_MASK );
rcr |= ( RTL_RCR_RXFTH_DEFAULT | RTL_RCR_RBLEN_DEFAULT |
RTL_RCR_MXDMA_DEFAULT | RTL_RCR_WRAP | RTL_RCR_AB |
RTL_RCR_AM | RTL_RCR_APM | RTL_RCR_AAP );

1
src/drivers/net/realtek.h
View File

@ -140,6 +140,7 @@ enum realtek_legacy_status {
/** Receive (Rx) Configuration Register (dword) */
#define RTL_RCR 0x44
#define RTL_RCR_STOP_WORKING 0x01000000UL /**< Here be dragons */
#define RTL_RCR_RXFTH(x) ( (x) << 13 ) /**< Receive FIFO threshold */
#define RTL_RCR_RXFTH_MASK RTL_RCR_RXFTH ( 0x7 )
#define RTL_RCR_RXFTH_DEFAULT RTL_RCR_RXFTH ( 0x7 /* Whole packet */ )