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msm: timer: fix initialization of timers

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Timers were previously initialised with writing 0 to the CLEAR reg. However
to succesfully clear the timer, one should write 1 to this reg.
This commit is contained in:
Martijn Stolk 2010-07-07 17:32:22 +02:00 committed by Markinus
parent 03c33afdb2
commit b8b23555a2
1 changed files with 3 additions and 1 deletions
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4
arch/arm/mach-msm/timer.c
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@ -688,7 +688,9 @@ static void __init msm_timer_init(void)
struct clock_event_device *ce = &clock->clockevent;
struct clocksource *cs = &clock->clocksource;
writel(0, clock->regbase + TIMER_ENABLE);
writel(0, clock->regbase + TIMER_CLEAR);
// The timer should be cleared by setting the first bit.
writel(1, clock->regbase + TIMER_CLEAR);
writel(0, clock->regbase + TIMER_COUNT_VAL);
writel(~0, clock->regbase + TIMER_MATCH_VAL);
while (msm_read_timer_count(clock)) ; /* wait for clock to clear */