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[3c90x] 3c90x driver rewrite using gPXE API
This is a major rewrite of the legacy etherboot 3c90x driver using the gPXE API for much improved performance over the legacy driver it replaces. This driver has been tested on 3c905, 3c905B, and 3c905C cards. Reviewed-by: Stefan Hajnoczi <stefanha@gmail.com> Reviewed-by: Marty Connor <mdc@etherboot.org> Tested-by: Marty Connor <mdc@etherboot.org> Tested-by: Daniel Verkamp <daniel@drv.nu> Signed-off-by: Marty Connor <mdc@etherboot.org>
This commit is contained in:
Thomas Miletich
Marty Connor
parent
3c68ff99ea
commit
90c01ef1e4
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Load Diff
300
src/drivers/net/3c90x.h
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300
src/drivers/net/3c90x.h
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/*
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* 3c90x.c -- This file implements the 3c90x driver for etherboot. Written
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* by Greg Beeley, Greg.Beeley@LightSys.org. Modified by Steve Smith,
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* Steve.Smith@Juno.Com. Alignment bug fix Neil Newell (nn@icenoir.net).
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*
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* Port from etherboot to gPXE API, implementation of tx/rx ring support
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* by Thomas Miletich, thomas.miletich@gmail.com
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* Thanks to Marty Connor and Stefan Hajnoczi for their help and feedback.
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*
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* This program Copyright (C) 1999 LightSys Technology Services, Inc.
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* Portions Copyright (C) 1999 Steve Smith
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*
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* This program may be re-distributed in source or binary form, modified,
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* sold, or copied for any purpose, provided that the above copyright message
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* and this text are included with all source copies or derivative works, and
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* provided that the above copyright message and this text are included in the
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* documentation of any binary-only distributions. This program is distributed
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* WITHOUT ANY WARRANTY, without even the warranty of FITNESS FOR A PARTICULAR
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* PURPOSE or MERCHANTABILITY. Please read the associated documentation
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* "3c90x.txt" before compiling and using this driver.
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*
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* --------
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*
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* Program written with the assistance of the 3com documentation for
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* the 3c905B-TX card, as well as with some assistance from the 3c59x
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* driver Donald Becker wrote for the Linux kernel, and with some assistance
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* from the remainder of the Etherboot distribution.
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*
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* REVISION HISTORY:
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*
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* v0.10 1-26-1998 GRB Initial implementation.
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* v0.90 1-27-1998 GRB System works.
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* v1.00pre1 2-11-1998 GRB Got prom boot issue fixed.
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* v2.0 9-24-1999 SCS Modified for 3c905 (from 3c905b code)
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* Re-wrote poll and transmit for
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* better error recovery and heavy
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* network traffic operation
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* v2.01 5-26-2003 NN Fixed driver alignment issue which
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* caused system lockups if driver structures
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* not 8-byte aligned.
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* v2.02 11-28-2007 GSt Got polling working again by replacing
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* "for(i=0;i<40000;i++);" with "mdelay(1);"
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*
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*
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* indent options: indent -kr -i8 3c90x.c
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*/
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#ifndef __3C90X_H_
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#define __3C90X_H_
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static struct net_device_operations a3c90x_operations;
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#define XCVR_MAGIC (0x5A00)
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/* Register definitions for the 3c905 */
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enum Registers {
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regPowerMgmtCtrl_w = 0x7c, /* 905B Revision Only */
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regUpMaxBurst_w = 0x7a, /* 905B Revision Only */
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regDnMaxBurst_w = 0x78, /* 905B Revision Only */
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regDebugControl_w = 0x74, /* 905B Revision Only */
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regDebugData_l = 0x70, /* 905B Revision Only */
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regRealTimeCnt_l = 0x40, /* Universal */
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regUpBurstThresh_b = 0x3e, /* 905B Revision Only */
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regUpPoll_b = 0x3d, /* 905B Revision Only */
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regUpPriorityThresh_b = 0x3c, /* 905B Revision Only */
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regUpListPtr_l = 0x38, /* Universal */
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regCountdown_w = 0x36, /* Universal */
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regFreeTimer_w = 0x34, /* Universal */
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regUpPktStatus_l = 0x30, /* Universal with Exception, pg 130 */
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regTxFreeThresh_b = 0x2f, /* 90X Revision Only */
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regDnPoll_b = 0x2d, /* 905B Revision Only */
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regDnPriorityThresh_b = 0x2c, /* 905B Revision Only */
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regDnBurstThresh_b = 0x2a, /* 905B Revision Only */
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regDnListPtr_l = 0x24, /* Universal with Exception, pg 107 */
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regDmaCtrl_l = 0x20, /* Universal with Exception, pg 106 */
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/* */
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regIntStatusAuto_w = 0x1e, /* 905B Revision Only */
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regTxStatus_b = 0x1b, /* Universal with Exception, pg 113 */
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regTimer_b = 0x1a, /* Universal */
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regTxPktId_b = 0x18, /* 905B Revision Only */
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regCommandIntStatus_w = 0x0e, /* Universal (Command Variations) */
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};
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/* following are windowed registers */
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enum Registers7 {
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regPowerMgmtEvent_7_w = 0x0c, /* 905B Revision Only */
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regVlanEtherType_7_w = 0x04, /* 905B Revision Only */
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regVlanMask_7_w = 0x00, /* 905B Revision Only */
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};
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enum Registers6 {
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regBytesXmittedOk_6_w = 0x0c, /* Universal */
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regBytesRcvdOk_6_w = 0x0a, /* Universal */
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regUpperFramesOk_6_b = 0x09, /* Universal */
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regFramesDeferred_6_b = 0x08, /* Universal */
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regFramesRecdOk_6_b = 0x07, /* Universal with Exceptions, pg 142 */
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regFramesXmittedOk_6_b = 0x06, /* Universal */
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regRxOverruns_6_b = 0x05, /* Universal */
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regLateCollisions_6_b = 0x04, /* Universal */
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regSingleCollisions_6_b = 0x03, /* Universal */
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regMultipleCollisions_6_b = 0x02, /* Universal */
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regSqeErrors_6_b = 0x01, /* Universal */
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regCarrierLost_6_b = 0x00, /* Universal */
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};
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enum Registers5 {
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regIndicationEnable_5_w = 0x0c, /* Universal */
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regInterruptEnable_5_w = 0x0a, /* Universal */
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regTxReclaimThresh_5_b = 0x09, /* 905B Revision Only */
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regRxFilter_5_b = 0x08, /* Universal */
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regRxEarlyThresh_5_w = 0x06, /* Universal */
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regTxStartThresh_5_w = 0x00, /* Universal */
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};
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enum Registers4 {
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regUpperBytesOk_4_b = 0x0d, /* Universal */
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regBadSSD_4_b = 0x0c, /* Universal */
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regMediaStatus_4_w = 0x0a, /* Universal with Exceptions, pg 201 */
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regPhysicalMgmt_4_w = 0x08, /* Universal */
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regNetworkDiagnostic_4_w = 0x06, /* Universal with Exceptions, pg 203 */
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regFifoDiagnostic_4_w = 0x04, /* Universal with Exceptions, pg 196 */
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regVcoDiagnostic_4_w = 0x02, /* Undocumented? */
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};
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enum Registers3 {
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regTxFree_3_w = 0x0c, /* Universal */
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regRxFree_3_w = 0x0a, /* Universal with Exceptions, pg 125 */
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regResetMediaOptions_3_w = 0x08, /* Media Options on B Revision, */
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/* Reset Options on Non-B Revision */
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regMacControl_3_w = 0x06, /* Universal with Exceptions, pg 199 */
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regMaxPktSize_3_w = 0x04, /* 905B Revision Only */
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regInternalConfig_3_l = 0x00, /* Universal, different bit */
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/* definitions, pg 59 */
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};
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enum Registers2 {
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regResetOptions_2_w = 0x0c, /* 905B Revision Only */
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regStationMask_2_3w = 0x06, /* Universal with Exceptions, pg 127 */
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regStationAddress_2_3w = 0x00, /* Universal with Exceptions, pg 127 */
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};
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enum Registers1 {
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regRxStatus_1_w = 0x0a, /* 90X Revision Only, Pg 126 */
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};
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enum Registers0 {
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regEepromData_0_w = 0x0c, /* Universal */
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regEepromCommand_0_w = 0x0a, /* Universal */
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regBiosRomData_0_b = 0x08, /* 905B Revision Only */
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regBiosRomAddr_0_l = 0x04, /* 905B Revision Only */
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};
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/* The names for the eight register windows */
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enum Windows {
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winNone = 0xff,
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winPowerVlan7 = 0x07,
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winStatistics6 = 0x06,
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winTxRxControl5 = 0x05,
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winDiagnostics4 = 0x04,
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winTxRxOptions3 = 0x03,
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winAddressing2 = 0x02,
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winUnused1 = 0x01,
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winEepromBios0 = 0x00,
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};
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/* Command definitions for the 3c90X */
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enum Commands {
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cmdGlobalReset = 0x00, /* Universal with Exceptions, pg 151 */
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cmdSelectRegisterWindow = 0x01, /* Universal */
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cmdEnableDcConverter = 0x02, /* */
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cmdRxDisable = 0x03, /* */
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cmdRxEnable = 0x04, /* Universal */
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cmdRxReset = 0x05, /* Universal */
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cmdStallCtl = 0x06, /* Universal */
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cmdTxEnable = 0x09, /* Universal */
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cmdTxDisable = 0x0A, /* */
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cmdTxReset = 0x0B, /* Universal */
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cmdRequestInterrupt = 0x0C, /* */
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cmdAcknowledgeInterrupt = 0x0D, /* Universal */
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cmdSetInterruptEnable = 0x0E, /* Universal */
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cmdSetIndicationEnable = 0x0F, /* Universal */
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cmdSetRxFilter = 0x10, /* Universal */
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cmdSetRxEarlyThresh = 0x11, /* */
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cmdSetTxStartThresh = 0x13, /* */
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cmdStatisticsEnable = 0x15, /* */
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cmdStatisticsDisable = 0x16, /* */
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cmdDisableDcConverter = 0x17, /* */
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cmdSetTxReclaimThresh = 0x18, /* */
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cmdSetHashFilterBit = 0x19, /* */
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};
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enum FrameStartHeader {
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fshTxIndicate = 0x8000,
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fshDnComplete = 0x10000,
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};
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enum UpDownDesc {
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upLastFrag = (1 << 31),
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downLastFrag = (1 << 31),
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};
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enum UpPktStatus {
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upComplete = (1 << 15),
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upError = (1 << 14),
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};
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enum Stalls {
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upStall = 0x00,
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upUnStall = 0x01,
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dnStall = 0x02,
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dnUnStall = 0x03,
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};
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enum Resources {
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resRxRing = 0x00,
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resTxRing = 0x02,
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resRxIOBuf = 0x04
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};
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enum eeprom {
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eepromBusy = (1 << 15),
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eepromRead = ((0x02) << 6),
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eepromRead_556 = 0x230,
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eepromHwAddrOffset = 0x0a,
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};
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/* Bit 4 is only used in revison B and upwards */
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enum linktype {
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link10BaseT = 0x00,
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linkAUI = 0x01,
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link10Base2 = 0x03,
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link100BaseFX = 0x05,
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linkMII = 0x06,
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linkAutoneg = 0x08,
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linkExternalMII = 0x09,
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};
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/* Values for int status register bitmask */
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#define INT_INTERRUPTLATCH (1<<0)
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#define INT_HOSTERROR (1<<1)
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#define INT_TXCOMPLETE (1<<2)
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#define INT_RXCOMPLETE (1<<4)
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#define INT_RXEARLY (1<<5)
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#define INT_INTREQUESTED (1<<6)
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#define INT_UPDATESTATS (1<<7)
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#define INT_LINKEVENT (1<<8)
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#define INT_DNCOMPLETE (1<<9)
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#define INT_UPCOMPLETE (1<<10)
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#define INT_CMDINPROGRESS (1<<12)
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#define INT_WINDOWNUMBER (7<<13)
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/* Buffer sizes */
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#define TX_RING_SIZE 8
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#define RX_RING_SIZE 8
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#define TX_RING_ALIGN 16
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#define RX_RING_ALIGN 16
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#define RX_BUF_SIZE 1536
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/* Timeouts for eeprom and command completion */
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/* Timeout 1 second, to be save */
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#define EEPROM_TIMEOUT 1 * 1000 * 1000
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/* TX descriptor */
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struct TXD {
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volatile unsigned int DnNextPtr;
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volatile unsigned int FrameStartHeader;
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volatile unsigned int DataAddr;
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volatile unsigned int DataLength;
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} __attribute__ ((aligned(8))); /* 64-bit aligned for bus mastering */
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/* RX descriptor */
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struct RXD {
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volatile unsigned int UpNextPtr;
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volatile unsigned int UpPktStatus;
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volatile unsigned int DataAddr;
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volatile unsigned int DataLength;
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} __attribute__ ((aligned(8))); /* 64-bit aligned for bus mastering */
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/* Private NIC dats */
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struct INF_3C90X {
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unsigned int is3c556;
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unsigned char isBrev;
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unsigned char CurrentWindow;
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unsigned int IOAddr;
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unsigned short eeprom[0x21];
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unsigned int tx_cur; /* current entry in tx_ring */
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unsigned int tx_cnt; /* current number of used tx descriptors */
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unsigned int tx_tail; /* entry of last finished packet */
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unsigned int rx_cur;
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struct TXD *tx_ring;
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struct RXD *rx_ring;
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struct io_buffer *tx_iobuf[TX_RING_SIZE];
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struct io_buffer *rx_iobuf[RX_RING_SIZE];
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struct nvs_device nvs;
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};
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#endif
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