349 lines
8.4 KiB
C
349 lines
8.4 KiB
C
/*
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* Blackfin CPLB exception handling for when MPU in on
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*
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* Copyright 2008-2009 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later.
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*/
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#include <linux/module.h>
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#include <linux/mm.h>
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#include <asm/blackfin.h>
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#include <asm/cacheflush.h>
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#include <asm/cplb.h>
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#include <asm/cplbinit.h>
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#include <asm/mmu_context.h>
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/*
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* WARNING
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*
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* This file is compiled with certain -ffixed-reg options. We have to
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* make sure not to call any functions here that could clobber these
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* registers.
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*/
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int page_mask_nelts;
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int page_mask_order;
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unsigned long *current_rwx_mask[NR_CPUS];
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int nr_dcplb_miss[NR_CPUS], nr_icplb_miss[NR_CPUS];
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int nr_icplb_supv_miss[NR_CPUS], nr_dcplb_prot[NR_CPUS];
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int nr_cplb_flush[NR_CPUS];
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/*
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* Given the contents of the status register, return the index of the
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* CPLB that caused the fault.
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*/
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static inline int faulting_cplb_index(int status)
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{
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int signbits = __builtin_bfin_norm_fr1x32(status & 0xFFFF);
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return 30 - signbits;
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}
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/*
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* Given the contents of the status register and the DCPLB_DATA contents,
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* return true if a write access should be permitted.
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*/
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static inline int write_permitted(int status, unsigned long data)
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{
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if (status & FAULT_USERSUPV)
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return !!(data & CPLB_SUPV_WR);
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else
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return !!(data & CPLB_USER_WR);
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}
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/* Counters to implement round-robin replacement. */
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static int icplb_rr_index[NR_CPUS], dcplb_rr_index[NR_CPUS];
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/*
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* Find an ICPLB entry to be evicted and return its index.
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*/
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static int evict_one_icplb(unsigned int cpu)
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{
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int i;
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for (i = first_switched_icplb; i < MAX_CPLBS; i++)
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if ((icplb_tbl[cpu][i].data & CPLB_VALID) == 0)
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return i;
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i = first_switched_icplb + icplb_rr_index[cpu];
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if (i >= MAX_CPLBS) {
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i -= MAX_CPLBS - first_switched_icplb;
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icplb_rr_index[cpu] -= MAX_CPLBS - first_switched_icplb;
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}
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icplb_rr_index[cpu]++;
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return i;
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}
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static int evict_one_dcplb(unsigned int cpu)
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{
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int i;
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for (i = first_switched_dcplb; i < MAX_CPLBS; i++)
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if ((dcplb_tbl[cpu][i].data & CPLB_VALID) == 0)
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return i;
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i = first_switched_dcplb + dcplb_rr_index[cpu];
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if (i >= MAX_CPLBS) {
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i -= MAX_CPLBS - first_switched_dcplb;
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dcplb_rr_index[cpu] -= MAX_CPLBS - first_switched_dcplb;
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}
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dcplb_rr_index[cpu]++;
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return i;
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}
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static noinline int dcplb_miss(unsigned int cpu)
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{
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unsigned long addr = bfin_read_DCPLB_FAULT_ADDR();
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int status = bfin_read_DCPLB_STATUS();
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unsigned long *mask;
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int idx;
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unsigned long d_data;
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nr_dcplb_miss[cpu]++;
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d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB;
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#ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE
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if (bfin_addr_dcacheable(addr)) {
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d_data |= CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND;
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# ifdef CONFIG_BFIN_EXTMEM_WRITETHROUGH
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d_data |= CPLB_L1_AOW | CPLB_WT;
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# endif
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}
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#endif
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if (L2_LENGTH && addr >= L2_START && addr < L2_START + L2_LENGTH) {
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addr = L2_START;
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d_data = L2_DMEMORY;
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} else if (addr >= physical_mem_end) {
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if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE
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&& (status & FAULT_USERSUPV)) {
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addr &= ~0x3fffff;
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d_data &= ~PAGE_SIZE_4KB;
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d_data |= PAGE_SIZE_4MB;
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} else if (addr >= BOOT_ROM_START && addr < BOOT_ROM_START + BOOT_ROM_LENGTH
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&& (status & (FAULT_RW | FAULT_USERSUPV)) == FAULT_USERSUPV) {
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addr &= ~(1 * 1024 * 1024 - 1);
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d_data &= ~PAGE_SIZE_4KB;
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d_data |= PAGE_SIZE_1MB;
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} else
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return CPLB_PROT_VIOL;
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} else if (addr >= _ramend) {
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d_data |= CPLB_USER_RD | CPLB_USER_WR;
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} else {
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mask = current_rwx_mask[cpu];
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if (mask) {
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int page = addr >> PAGE_SHIFT;
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int idx = page >> 5;
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int bit = 1 << (page & 31);
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if (mask[idx] & bit)
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d_data |= CPLB_USER_RD;
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mask += page_mask_nelts;
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if (mask[idx] & bit)
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d_data |= CPLB_USER_WR;
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}
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}
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idx = evict_one_dcplb(cpu);
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addr &= PAGE_MASK;
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dcplb_tbl[cpu][idx].addr = addr;
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dcplb_tbl[cpu][idx].data = d_data;
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_disable_dcplb();
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bfin_write32(DCPLB_DATA0 + idx * 4, d_data);
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bfin_write32(DCPLB_ADDR0 + idx * 4, addr);
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_enable_dcplb();
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return 0;
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}
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static noinline int icplb_miss(unsigned int cpu)
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{
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unsigned long addr = bfin_read_ICPLB_FAULT_ADDR();
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int status = bfin_read_ICPLB_STATUS();
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int idx;
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unsigned long i_data;
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nr_icplb_miss[cpu]++;
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/* If inside the uncached DMA region, fault. */
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if (addr >= _ramend - DMA_UNCACHED_REGION && addr < _ramend)
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return CPLB_PROT_VIOL;
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if (status & FAULT_USERSUPV)
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nr_icplb_supv_miss[cpu]++;
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/*
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* First, try to find a CPLB that matches this address. If we
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* find one, then the fact that we're in the miss handler means
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* that the instruction crosses a page boundary.
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*/
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for (idx = first_switched_icplb; idx < MAX_CPLBS; idx++) {
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if (icplb_tbl[cpu][idx].data & CPLB_VALID) {
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unsigned long this_addr = icplb_tbl[cpu][idx].addr;
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if (this_addr <= addr && this_addr + PAGE_SIZE > addr) {
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addr += PAGE_SIZE;
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break;
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}
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}
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}
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i_data = CPLB_VALID | CPLB_PORTPRIO | PAGE_SIZE_4KB;
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#ifdef CONFIG_BFIN_EXTMEM_ICACHEABLE
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/*
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* Normal RAM, and possibly the reserved memory area, are
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* cacheable.
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*/
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if (addr < _ramend ||
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(addr < physical_mem_end && reserved_mem_icache_on))
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i_data |= CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND;
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#endif
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if (L2_LENGTH && addr >= L2_START && addr < L2_START + L2_LENGTH) {
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addr = L2_START;
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i_data = L2_IMEMORY;
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} else if (addr >= physical_mem_end) {
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if (addr >= BOOT_ROM_START && addr < BOOT_ROM_START + BOOT_ROM_LENGTH
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&& (status & FAULT_USERSUPV)) {
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addr &= ~(1 * 1024 * 1024 - 1);
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i_data &= ~PAGE_SIZE_4KB;
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i_data |= PAGE_SIZE_1MB;
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} else
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return CPLB_PROT_VIOL;
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} else if (addr >= _ramend) {
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i_data |= CPLB_USER_RD;
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} else {
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/*
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* Two cases to distinguish - a supervisor access must
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* necessarily be for a module page; we grant it
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* unconditionally (could do better here in the future).
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* Otherwise, check the x bitmap of the current process.
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*/
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if (!(status & FAULT_USERSUPV)) {
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unsigned long *mask = current_rwx_mask[cpu];
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if (mask) {
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int page = addr >> PAGE_SHIFT;
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int idx = page >> 5;
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int bit = 1 << (page & 31);
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mask += 2 * page_mask_nelts;
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if (mask[idx] & bit)
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i_data |= CPLB_USER_RD;
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}
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}
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}
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idx = evict_one_icplb(cpu);
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addr &= PAGE_MASK;
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icplb_tbl[cpu][idx].addr = addr;
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icplb_tbl[cpu][idx].data = i_data;
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_disable_icplb();
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bfin_write32(ICPLB_DATA0 + idx * 4, i_data);
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bfin_write32(ICPLB_ADDR0 + idx * 4, addr);
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_enable_icplb();
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return 0;
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}
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static noinline int dcplb_protection_fault(unsigned int cpu)
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{
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int status = bfin_read_DCPLB_STATUS();
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nr_dcplb_prot[cpu]++;
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if (status & FAULT_RW) {
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int idx = faulting_cplb_index(status);
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unsigned long data = dcplb_tbl[cpu][idx].data;
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if (!(data & CPLB_WT) && !(data & CPLB_DIRTY) &&
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write_permitted(status, data)) {
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data |= CPLB_DIRTY;
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dcplb_tbl[cpu][idx].data = data;
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bfin_write32(DCPLB_DATA0 + idx * 4, data);
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return 0;
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}
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}
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return CPLB_PROT_VIOL;
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}
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int cplb_hdr(int seqstat, struct pt_regs *regs)
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{
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int cause = seqstat & 0x3f;
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unsigned int cpu = raw_smp_processor_id();
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switch (cause) {
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case 0x23:
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return dcplb_protection_fault(cpu);
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case 0x2C:
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return icplb_miss(cpu);
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case 0x26:
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return dcplb_miss(cpu);
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default:
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return 1;
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}
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}
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void flush_switched_cplbs(unsigned int cpu)
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{
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int i;
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unsigned long flags;
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nr_cplb_flush[cpu]++;
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local_irq_save_hw(flags);
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_disable_icplb();
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for (i = first_switched_icplb; i < MAX_CPLBS; i++) {
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icplb_tbl[cpu][i].data = 0;
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bfin_write32(ICPLB_DATA0 + i * 4, 0);
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}
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_enable_icplb();
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_disable_dcplb();
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for (i = first_switched_dcplb; i < MAX_CPLBS; i++) {
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dcplb_tbl[cpu][i].data = 0;
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bfin_write32(DCPLB_DATA0 + i * 4, 0);
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}
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_enable_dcplb();
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local_irq_restore_hw(flags);
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}
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void set_mask_dcplbs(unsigned long *masks, unsigned int cpu)
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{
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int i;
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unsigned long addr = (unsigned long)masks;
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unsigned long d_data;
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unsigned long flags;
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if (!masks) {
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current_rwx_mask[cpu] = masks;
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return;
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}
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local_irq_save_hw(flags);
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current_rwx_mask[cpu] = masks;
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if (L2_LENGTH && addr >= L2_START && addr < L2_START + L2_LENGTH) {
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addr = L2_START;
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d_data = L2_DMEMORY;
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} else {
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d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB;
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#ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE
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d_data |= CPLB_L1_CHBL;
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# ifdef CONFIG_BFIN_EXTMEM_WRITETHROUGH
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d_data |= CPLB_L1_AOW | CPLB_WT;
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# endif
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#endif
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}
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_disable_dcplb();
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for (i = first_mask_dcplb; i < first_switched_dcplb; i++) {
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dcplb_tbl[cpu][i].addr = addr;
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dcplb_tbl[cpu][i].data = d_data;
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bfin_write32(DCPLB_DATA0 + i * 4, d_data);
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bfin_write32(DCPLB_ADDR0 + i * 4, addr);
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addr += PAGE_SIZE;
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}
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_enable_dcplb();
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local_irq_restore_hw(flags);
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}
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