211 lines
6.1 KiB
C
211 lines
6.1 KiB
C
/* arch/arm/mach-msm/clock.h
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*
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* Copyright (C) 2007 Google, Inc.
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* Copyright (c) 2007 QUALCOMM Incorporated
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef __ARCH_ARM_MACH_MSM_CLOCK_H
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#define __ARCH_ARM_MACH_MSM_CLOCK_H
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#include <linux/list.h>
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#include <mach/clk.h>
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#if defined (CONFIG_ARCH_MSM7X30)
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#include "clock-pcom.h"
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#include "clock-7x30.h"
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#endif
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#define CLKFLAG_USE_MAX_TO_SET (0x00000001)
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#define CLKFLAG_AUTO_OFF (0x00000002)
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#define CLKFLAG_USE_MIN_TO_SET (0x00000004)
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#define CLKFLAG_SHARED (0x00000008)
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#define CLKFLAG_HANDLE (0x00000010)
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#define CLKFLAG_ARCH_MSM7X00A (0x00010000)
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#define CLKFLAG_ARCH_QSD8X50 (0x00020000)
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#define CLKFLAG_ARCH_ALL (0xffff0000)
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struct clk_ops {
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int (*enable)(unsigned id);
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void (*disable)(unsigned id);
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void (*auto_off)(unsigned id);
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int (*reset)(unsigned id, enum clk_reset_action action);
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int (*set_rate)(unsigned id, unsigned rate);
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int (*set_min_rate)(unsigned id, unsigned rate);
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int (*set_max_rate)(unsigned id, unsigned rate);
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int (*set_flags)(unsigned id, unsigned flags);
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unsigned (*get_rate)(unsigned id);
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unsigned (*is_enabled)(unsigned id);
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long (*round_rate)(unsigned id, unsigned rate);
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};
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struct clk {
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uint32_t id;
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uint32_t remote_id;
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uint32_t count;
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uint32_t flags;
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const char *name;
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struct clk_ops *ops;
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struct hlist_node list;
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struct device *dev;
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struct hlist_head handles;
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};
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struct clk_handle {
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struct clk clk;
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struct clk *source;
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unsigned long rate;
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};
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#define A11S_CLK_CNTL_ADDR (MSM_CSR_BASE + 0x100)
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#define A11S_CLK_SEL_ADDR (MSM_CSR_BASE + 0x104)
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#define A11S_VDD_SVS_PLEVEL_ADDR (MSM_CSR_BASE + 0x124)
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/* clock IDs used by the modem processor */
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#define ACPU_CLK 0 /* Applications processor clock */
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#define ADM_CLK 1 /* Applications data mover clock */
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#define ADSP_CLK 2 /* ADSP clock */
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#define EBI1_CLK 3 /* External bus interface 1 clock */
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#define EBI2_CLK 4 /* External bus interface 2 clock */
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#define ECODEC_CLK 5 /* External CODEC clock */
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#define EMDH_CLK 6 /* External MDDI host clock */
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#define GP_CLK 7 /* General purpose clock */
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#define GRP_CLK 8 /* Graphics clock */
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#define I2C_CLK 9 /* I2C clock */
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#define ICODEC_RX_CLK 10 /* Internal CODEX RX clock */
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#define ICODEC_TX_CLK 11 /* Internal CODEX TX clock */
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#define IMEM_CLK 12 /* Internal graphics memory clock */
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#define MDC_CLK 13 /* MDDI client clock */
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#define MDP_CLK 14 /* Mobile display processor clock */
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#define PBUS_CLK 15 /* Peripheral bus clock */
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#define PCM_CLK 16 /* PCM clock */
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#define PMDH_CLK 17 /* Primary MDDI host clock */
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#define SDAC_CLK 18 /* Stereo DAC clock */
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#define SDC1_CLK 19 /* Secure Digital Card clocks */
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#define SDC1_PCLK 20
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#define SDC2_CLK 21
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#define SDC2_PCLK 22
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#define SDC3_CLK 23
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#define SDC3_PCLK 24
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#define SDC4_CLK 25
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#define SDC4_PCLK 26
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#define TSIF_CLK 27 /* Transport Stream Interface clocks */
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#define TSIF_REF_CLK 28
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#define TV_DAC_CLK 29 /* TV clocks */
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#define TV_ENC_CLK 30
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#define UART1_CLK 31 /* UART clocks */
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#define UART2_CLK 32
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#define UART3_CLK 33
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#define UART1DM_CLK 34
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#define UART2DM_CLK 35
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#define USB_HS_CLK 36 /* High speed USB core clock */
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#define USB_HS_PCLK 37 /* High speed USB pbus clock */
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#define USB_OTG_CLK 38 /* Full speed USB clock */
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#define VDC_CLK 39 /* Video controller clock */
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#if defined(CONFIG_ARCH_QSD8X50) || defined(CONFIG_ARCH_MSM7227) || defined(CONFIG_ARCH_MSM7X00A) || defined(CONFIG_ARCH_MSM7X30)
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#define VFE_MDC_CLK 40 /* VFE MDDI client clock */
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#define VFE_CLK 41 /* Camera / Video Front End clock */
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#else
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/* older AMSS versions had these flipped */
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#define VFE_MDC_CLK 41 /* VFE MDDI client clock */
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#define VFE_CLK 40 /* Camera / Video Front End clock */
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#endif
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#define LCDC_PCLK 42
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#define LCDC_PAD_PCLK 43
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#define MDP_VSYNC_CLK 44
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#define SPI_CLK 45
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#define VFE_AXI_CLK 46
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#define USB_HS2_CLK 47 /* High speed USB 2 core clock */
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#define USB_HS2_PCLK 48 /* High speed USB 2 pbus clock */
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#define USB_HS3_CLK 49 /* High speed USB 3 core clock */
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#define USB_HS3_PCLK 50 /* High speed USB 3 pbus clock */
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#define GRP_PCLK 51 /* Graphics pbus clock */
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#define USB_PHY_CLK 52 /* USB PHY clock */
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#define USB_HS_CORE_CLK 53 /* High speed USB 1 core clock */
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#define USB_HS2_CORE_CLK 54 /* High speed USB 2 core clock */
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#define USB_HS3_CORE_CLK 55 /* High speed USB 3 core clock */
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#define CAM_MCLK_CLK 56
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#define CAMIF_PAD_PCLK 57
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#define GRP_2D_CLK 58
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#define GRP_2D_PCLK 59
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#define I2S_CLK 60
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#define JPEG_CLK 61
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#define JPEG_PCLK 62
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#define LPA_CODEC_CLK 63
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#define LPA_CORE_CLK 64
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#define LPA_PCLK 65
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#define MDC_IO_CLK 66
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#define MDC_PCLK 67
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#define MFC_CLK 68
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#define MFC_DIV2_CLK 69
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#define MFC_PCLK 70
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#define QUP_I2C_CLK 71
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#define ROTATOR_IMEM_CLK 72
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#define ROTATOR_PCLK 73
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#define VFE_CAMIF_CLK 74
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#define VFE_PCLK 75
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#define VPE_CLK 76
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#define I2C_2_CLK 77
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#define MI2S_CODEC_RX_SCLK 78
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#define MI2S_CODEC_RX_MCLK 79
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#define MI2S_CODEC_TX_SCLK 80
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#define MI2S_CODEC_TX_MCLK 81
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#define PMDH_PCLK 82
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#define EMDH_PCLK 83
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#define SPI_PCLK 84
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#define TSIF_PCLK 85
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#define MDP_PCLK 86
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#define SDAC_MCLK 87
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#define MI2S_HDMI_CLK 88
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#define MI2S_HDMI_MCLK 89
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#define AXI_ROTATOR_CLK 90
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#define HDMI_CLK 91
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#define CSI0_CLK 92
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#define CSI0_VFE_CLK 93
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#define CSI0_PCLK 94
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#define CSI1_CLK 95
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#define CSI1_VFE_CLK 96
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#define CSI1_PCLK 97
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#define GSBI_CLK 98
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#define GSBI_PCLK 99
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#define NR_CLKS 100
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extern struct clk msm_clocks[];
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void clk_enter_sleep(int from_idle);
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void clk_exit_sleep(void);
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#if defined (CONFIG_ARCH_MSM7X30)
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enum {
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PLL_0 = 0,
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PLL_1,
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PLL_2,
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PLL_3,
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PLL_4,
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PLL_5,
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PLL_6,
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NUM_PLL
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};
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enum clkvote_client {
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CLKVOTE_ACPUCLK = 0,
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CLKVOTE_PMQOS,
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CLKVOTE_MAX,
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};
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unsigned long clk_get_max_axi_khz(void);
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#endif
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#endif
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