420 lines
14 KiB
C
420 lines
14 KiB
C
/*
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* include/asm-xtensa/pgtable.h
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Copyright (C) 2001 - 2007 Tensilica Inc.
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*/
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#ifndef _XTENSA_PGTABLE_H
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#define _XTENSA_PGTABLE_H
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#include <asm-generic/pgtable-nopmd.h>
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#include <asm/page.h>
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/*
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* We only use two ring levels, user and kernel space.
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*/
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#define USER_RING 1 /* user ring level */
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#define KERNEL_RING 0 /* kernel ring level */
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/*
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* The Xtensa architecture port of Linux has a two-level page table system,
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* i.e. the logical three-level Linux page table layout is folded.
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* Each task has the following memory page tables:
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*
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* PGD table (page directory), ie. 3rd-level page table:
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* One page (4 kB) of 1024 (PTRS_PER_PGD) pointers to PTE tables
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* (Architectures that don't have the PMD folded point to the PMD tables)
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*
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* The pointer to the PGD table for a given task can be retrieved from
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* the task structure (struct task_struct*) t, e.g. current():
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* (t->mm ? t->mm : t->active_mm)->pgd
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*
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* PMD tables (page middle-directory), ie. 2nd-level page tables:
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* Absent for the Xtensa architecture (folded, PTRS_PER_PMD == 1).
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*
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* PTE tables (page table entry), ie. 1st-level page tables:
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* One page (4 kB) of 1024 (PTRS_PER_PTE) PTEs with a special PTE
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* invalid_pte_table for absent mappings.
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*
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* The individual pages are 4 kB big with special pages for the empty_zero_page.
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*/
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#define PGDIR_SHIFT 22
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#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
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#define PGDIR_MASK (~(PGDIR_SIZE-1))
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/*
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* Entries per page directory level: we use two-level, so
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* we don't really have any PMD directory physically.
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*/
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#define PTRS_PER_PTE 1024
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#define PTRS_PER_PTE_SHIFT 10
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#define PTRS_PER_PGD 1024
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#define PGD_ORDER 0
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#define USER_PTRS_PER_PGD (TASK_SIZE/PGDIR_SIZE)
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#define FIRST_USER_ADDRESS 0
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#define FIRST_USER_PGD_NR (FIRST_USER_ADDRESS >> PGDIR_SHIFT)
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/*
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* Virtual memory area. We keep a distance to other memory regions to be
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* on the safe side. We also use this area for cache aliasing.
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*/
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#define VMALLOC_START 0xC0000000
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#define VMALLOC_END 0xC7FEFFFF
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#define TLBTEMP_BASE_1 0xC7FF0000
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#define TLBTEMP_BASE_2 0xC7FF8000
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/*
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* Xtensa Linux config PTE layout (when present):
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* 31-12: PPN
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* 11-6: Software
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* 5-4: RING
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* 3-0: CA
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*
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* Similar to the Alpha and MIPS ports, we need to keep track of the ref
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* and mod bits in software. We have a software "you can read
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* from this page" bit, and a hardware one which actually lets the
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* process read from the page. On the same token we have a software
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* writable bit and the real hardware one which actually lets the
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* process write to the page.
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*
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* See further below for PTE layout for swapped-out pages.
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*/
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#define _PAGE_HW_EXEC (1<<0) /* hardware: page is executable */
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#define _PAGE_HW_WRITE (1<<1) /* hardware: page is writable */
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#define _PAGE_FILE (1<<1) /* non-linear mapping, if !present */
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#define _PAGE_PROTNONE (3<<0) /* special case for VM_PROT_NONE */
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/* None of these cache modes include MP coherency: */
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#define _PAGE_CA_BYPASS (0<<2) /* bypass, non-speculative */
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#define _PAGE_CA_WB (1<<2) /* write-back */
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#define _PAGE_CA_WT (2<<2) /* write-through */
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#define _PAGE_CA_MASK (3<<2)
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#define _PAGE_INVALID (3<<2)
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#define _PAGE_USER (1<<4) /* user access (ring=1) */
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/* Software */
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#define _PAGE_WRITABLE_BIT 6
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#define _PAGE_WRITABLE (1<<6) /* software: page writable */
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#define _PAGE_DIRTY (1<<7) /* software: page dirty */
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#define _PAGE_ACCESSED (1<<8) /* software: page accessed (read) */
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/* On older HW revisions, we always have to set bit 0 */
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#if XCHAL_HW_VERSION_MAJOR < 2000
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# define _PAGE_VALID (1<<0)
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#else
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# define _PAGE_VALID 0
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#endif
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#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
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#define _PAGE_PRESENT (_PAGE_VALID | _PAGE_CA_WB | _PAGE_ACCESSED)
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#ifdef CONFIG_MMU
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#define PAGE_NONE __pgprot(_PAGE_INVALID | _PAGE_USER | _PAGE_PROTNONE)
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#define PAGE_COPY __pgprot(_PAGE_PRESENT | _PAGE_USER)
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#define PAGE_COPY_EXEC __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_HW_EXEC)
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#define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_USER)
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#define PAGE_READONLY_EXEC __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_HW_EXEC)
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#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_WRITABLE)
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#define PAGE_SHARED_EXEC \
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__pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_WRITABLE | _PAGE_HW_EXEC)
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#define PAGE_KERNEL __pgprot(_PAGE_PRESENT | _PAGE_HW_WRITE)
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#define PAGE_KERNEL_EXEC __pgprot(_PAGE_PRESENT|_PAGE_HW_WRITE|_PAGE_HW_EXEC)
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#if (DCACHE_WAY_SIZE > PAGE_SIZE)
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# define _PAGE_DIRECTORY (_PAGE_VALID | _PAGE_ACCESSED)
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#else
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# define _PAGE_DIRECTORY (_PAGE_VALID | _PAGE_ACCESSED | _PAGE_CA_WB)
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#endif
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#else /* no mmu */
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# define PAGE_NONE __pgprot(0)
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# define PAGE_SHARED __pgprot(0)
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# define PAGE_COPY __pgprot(0)
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# define PAGE_READONLY __pgprot(0)
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# define PAGE_KERNEL __pgprot(0)
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#endif
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/*
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* On certain configurations of Xtensa MMUs (eg. the initial Linux config),
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* the MMU can't do page protection for execute, and considers that the same as
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* read. Also, write permissions may imply read permissions.
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* What follows is the closest we can get by reasonable means..
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* See linux/mm/mmap.c for protection_map[] array that uses these definitions.
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*/
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#define __P000 PAGE_NONE /* private --- */
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#define __P001 PAGE_READONLY /* private --r */
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#define __P010 PAGE_COPY /* private -w- */
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#define __P011 PAGE_COPY /* private -wr */
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#define __P100 PAGE_READONLY_EXEC /* private x-- */
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#define __P101 PAGE_READONLY_EXEC /* private x-r */
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#define __P110 PAGE_COPY_EXEC /* private xw- */
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#define __P111 PAGE_COPY_EXEC /* private xwr */
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#define __S000 PAGE_NONE /* shared --- */
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#define __S001 PAGE_READONLY /* shared --r */
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#define __S010 PAGE_SHARED /* shared -w- */
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#define __S011 PAGE_SHARED /* shared -wr */
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#define __S100 PAGE_READONLY_EXEC /* shared x-- */
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#define __S101 PAGE_READONLY_EXEC /* shared x-r */
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#define __S110 PAGE_SHARED_EXEC /* shared xw- */
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#define __S111 PAGE_SHARED_EXEC /* shared xwr */
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#ifndef __ASSEMBLY__
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#define pte_ERROR(e) \
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printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
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#define pgd_ERROR(e) \
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printk("%s:%d: bad pgd entry %08lx.\n", __FILE__, __LINE__, pgd_val(e))
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extern unsigned long empty_zero_page[1024];
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#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
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#ifdef CONFIG_MMU
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extern pgd_t swapper_pg_dir[PAGE_SIZE/sizeof(pgd_t)];
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extern void paging_init(void);
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extern void pgtable_cache_init(void);
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#else
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# define swapper_pg_dir NULL
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static inline void paging_init(void) { }
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static inline void pgtable_cache_init(void) { }
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#endif
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/*
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* The pmd contains the kernel virtual address of the pte page.
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*/
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#define pmd_page_vaddr(pmd) ((unsigned long)(pmd_val(pmd) & PAGE_MASK))
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#define pmd_page(pmd) virt_to_page(pmd_val(pmd))
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/*
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* pte status.
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*/
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#define pte_none(pte) (pte_val(pte) == _PAGE_INVALID)
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#define pte_present(pte) \
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(((pte_val(pte) & _PAGE_CA_MASK) != _PAGE_INVALID) \
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|| ((pte_val(pte) & _PAGE_PROTNONE) == _PAGE_PROTNONE))
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#define pte_clear(mm,addr,ptep) \
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do { update_pte(ptep, __pte(_PAGE_INVALID)); } while(0)
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#define pmd_none(pmd) (!pmd_val(pmd))
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#define pmd_present(pmd) (pmd_val(pmd) & PAGE_MASK)
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#define pmd_bad(pmd) (pmd_val(pmd) & ~PAGE_MASK)
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#define pmd_clear(pmdp) do { set_pmd(pmdp, __pmd(0)); } while (0)
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static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITABLE; }
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static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; }
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static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
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static inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE; }
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static inline int pte_special(pte_t pte) { return 0; }
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static inline pte_t pte_wrprotect(pte_t pte)
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{ pte_val(pte) &= ~(_PAGE_WRITABLE | _PAGE_HW_WRITE); return pte; }
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static inline pte_t pte_mkclean(pte_t pte)
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{ pte_val(pte) &= ~(_PAGE_DIRTY | _PAGE_HW_WRITE); return pte; }
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static inline pte_t pte_mkold(pte_t pte)
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{ pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
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static inline pte_t pte_mkdirty(pte_t pte)
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{ pte_val(pte) |= _PAGE_DIRTY; return pte; }
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static inline pte_t pte_mkyoung(pte_t pte)
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{ pte_val(pte) |= _PAGE_ACCESSED; return pte; }
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static inline pte_t pte_mkwrite(pte_t pte)
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{ pte_val(pte) |= _PAGE_WRITABLE; return pte; }
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static inline pte_t pte_mkspecial(pte_t pte)
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{ return pte; }
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/*
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* Conversion functions: convert a page and protection to a page entry,
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* and a page entry and page directory to the page they refer to.
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*/
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#define pte_pfn(pte) (pte_val(pte) >> PAGE_SHIFT)
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#define pte_same(a,b) (pte_val(a) == pte_val(b))
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#define pte_page(x) pfn_to_page(pte_pfn(x))
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#define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
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#define mk_pte(page, prot) pfn_pte(page_to_pfn(page), prot)
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static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
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{
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return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot));
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}
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/*
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* Certain architectures need to do special things when pte's
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* within a page table are directly modified. Thus, the following
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* hook is made available.
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*/
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static inline void update_pte(pte_t *ptep, pte_t pteval)
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{
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*ptep = pteval;
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#if (DCACHE_WAY_SIZE > PAGE_SIZE) && XCHAL_DCACHE_IS_WRITEBACK
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__asm__ __volatile__ ("dhwb %0, 0" :: "a" (ptep));
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#endif
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}
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struct mm_struct;
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static inline void
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set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep, pte_t pteval)
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{
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update_pte(ptep, pteval);
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}
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static inline void
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set_pmd(pmd_t *pmdp, pmd_t pmdval)
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{
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*pmdp = pmdval;
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}
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struct vm_area_struct;
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static inline int
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ptep_test_and_clear_young(struct vm_area_struct *vma, unsigned long addr,
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pte_t *ptep)
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{
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pte_t pte = *ptep;
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if (!pte_young(pte))
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return 0;
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update_pte(ptep, pte_mkold(pte));
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return 1;
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}
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static inline pte_t
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ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
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{
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pte_t pte = *ptep;
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pte_clear(mm, addr, ptep);
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return pte;
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}
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static inline void
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ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
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{
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pte_t pte = *ptep;
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update_pte(ptep, pte_wrprotect(pte));
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}
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/* to find an entry in a kernel page-table-directory */
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#define pgd_offset_k(address) pgd_offset(&init_mm, address)
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/* to find an entry in a page-table-directory */
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#define pgd_offset(mm,address) ((mm)->pgd + pgd_index(address))
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#define pgd_index(address) ((address) >> PGDIR_SHIFT)
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/* Find an entry in the second-level page table.. */
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#define pmd_offset(dir,address) ((pmd_t*)(dir))
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/* Find an entry in the third-level page table.. */
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#define pte_index(address) (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
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#define pte_offset_kernel(dir,addr) \
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((pte_t*) pmd_page_vaddr(*(dir)) + pte_index(addr))
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#define pte_offset_map(dir,addr) pte_offset_kernel((dir),(addr))
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#define pte_offset_map_nested(dir,addr) pte_offset_kernel((dir),(addr))
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#define pte_unmap(pte) do { } while (0)
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#define pte_unmap_nested(pte) do { } while (0)
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/*
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* Encode and decode a swap entry.
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*
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* Format of swap pte:
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* bit 0 MBZ
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* bit 1 page-file (must be zero)
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* bits 2 - 3 page hw access mode (must be 11: _PAGE_INVALID)
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* bits 4 - 5 ring protection (must be 01: _PAGE_USER)
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* bits 6 - 10 swap type (5 bits -> 32 types)
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* bits 11 - 31 swap offset / PAGE_SIZE (21 bits -> 8GB)
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* Format of file pte:
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* bit 0 MBZ
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* bit 1 page-file (must be one: _PAGE_FILE)
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* bits 2 - 3 page hw access mode (must be 11: _PAGE_INVALID)
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* bits 4 - 5 ring protection (must be 01: _PAGE_USER)
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* bits 6 - 31 file offset / PAGE_SIZE
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*/
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#define __swp_type(entry) (((entry).val >> 6) & 0x1f)
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#define __swp_offset(entry) ((entry).val >> 11)
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#define __swp_entry(type,offs) \
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((swp_entry_t) {((type) << 6) | ((offs) << 11) | _PAGE_INVALID})
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#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
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#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
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#define PTE_FILE_MAX_BITS 28
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#define pte_to_pgoff(pte) (pte_val(pte) >> 4)
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#define pgoff_to_pte(off) \
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((pte_t) { ((off) << 4) | _PAGE_INVALID | _PAGE_FILE })
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#endif /* !defined (__ASSEMBLY__) */
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#ifdef __ASSEMBLY__
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/* Assembly macro _PGD_INDEX is the same as C pgd_index(unsigned long),
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* _PGD_OFFSET as C pgd_offset(struct mm_struct*, unsigned long),
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* _PMD_OFFSET as C pmd_offset(pgd_t*, unsigned long)
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* _PTE_OFFSET as C pte_offset(pmd_t*, unsigned long)
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*
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* Note: We require an additional temporary register which can be the same as
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* the register that holds the address.
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*
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* ((pte_t*) ((unsigned long)(pmd_val(*pmd) & PAGE_MASK)) + pte_index(addr))
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*
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*/
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#define _PGD_INDEX(rt,rs) extui rt, rs, PGDIR_SHIFT, 32-PGDIR_SHIFT
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#define _PTE_INDEX(rt,rs) extui rt, rs, PAGE_SHIFT, PTRS_PER_PTE_SHIFT
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#define _PGD_OFFSET(mm,adr,tmp) l32i mm, mm, MM_PGD; \
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_PGD_INDEX(tmp, adr); \
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addx4 mm, tmp, mm
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#define _PTE_OFFSET(pmd,adr,tmp) _PTE_INDEX(tmp, adr); \
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srli pmd, pmd, PAGE_SHIFT; \
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slli pmd, pmd, PAGE_SHIFT; \
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addx4 pmd, tmp, pmd
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#else
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#define kern_addr_valid(addr) (1)
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extern void update_mmu_cache(struct vm_area_struct * vma,
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unsigned long address, pte_t pte);
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/*
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* remap a physical page `pfn' of size `size' with page protection `prot'
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* into virtual address `from'
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*/
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#define io_remap_pfn_range(vma,from,pfn,size,prot) \
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remap_pfn_range(vma, from, pfn, size, prot)
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typedef pte_t *pte_addr_t;
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#endif /* !defined (__ASSEMBLY__) */
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#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
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#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
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#define __HAVE_ARCH_PTEP_SET_WRPROTECT
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#define __HAVE_ARCH_PTEP_MKDIRTY
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#define __HAVE_ARCH_PTE_SAME
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#include <asm-generic/pgtable.h>
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#endif /* _XTENSA_PGTABLE_H */
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