454 lines
17 KiB
C
Executable File
454 lines
17 KiB
C
Executable File
/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef _A300_REG_H
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#define _A300_REG_H
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/* Interrupt bit positions within RBBM_INT_0 */
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#define A3XX_INT_RBBM_GPU_IDLE 0
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#define A3XX_INT_RBBM_AHB_ERROR 1
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#define A3XX_INT_RBBM_REG_TIMEOUT 2
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#define A3XX_INT_RBBM_ME_MS_TIMEOUT 3
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#define A3XX_INT_RBBM_PFP_MS_TIMEOUT 4
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#define A3XX_INT_RBBM_ATB_BUS_OVERFLOW 5
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#define A3XX_INT_VFD_ERROR 6
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#define A3XX_INT_CP_SW_INT 7
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#define A3XX_INT_CP_T0_PACKET_IN_IB 8
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#define A3XX_INT_CP_OPCODE_ERROR 9
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#define A3XX_INT_CP_RESERVED_BIT_ERROR 10
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#define A3XX_INT_CP_HW_FAULT 11
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#define A3xx_INT_CP_DMA 12
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#define A3XX_INT_CP_IB2_INT 13
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#define A3XX_INT_CP_IB1_INT 14
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#define A3XX_INT_CP_RB_INT 15
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#define A3XX_INT_CP_REG_PROTECT_FAULT 16
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#define A3XX_INT_CP_RB_DONE_TS 17
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#define A3XX_INT_CP_VS_DONE_TS 18
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#define A3XX_INT_CP_PS_DONE_TS 19
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#define A3XX_INT_CACHE_FLUSH_TS 20
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#define A3XX_INT_CP_AHB_ERROR_HALT 21
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#define A3XX_INT_MISC_HANG_DETECT 24
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#define A3XX_INT_UCHE_OOB_ACCESS 25
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/* Register definitions */
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#define A3XX_RBBM_HW_VERSION 0x000
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#define A3XX_RBBM_HW_RELEASE 0x001
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#define A3XX_RBBM_HW_CONFIGURATION 0x002
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#define A3XX_RBBM_SW_RESET_CMD 0x018
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#define A3XX_RBBM_AHB_CTL0 0x020
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#define A3XX_RBBM_AHB_CTL1 0x021
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#define A3XX_RBBM_AHB_CMD 0x022
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#define A3XX_RBBM_AHB_ERROR_STATUS 0x027
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#define A3XX_RBBM_GPR0_CTL 0x02E
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/* This the same register as on A2XX, just in a different place */
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#define A3XX_RBBM_STATUS 0x030
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#define A3XX_RBBM_INTERFACE_HANG_INT_CTL 0x50
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#define A3XX_RBBM_INTERFACE_HANG_MASK_CTL0 0x51
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#define A3XX_RBBM_INTERFACE_HANG_MASK_CTL1 0x54
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#define A3XX_RBBM_INTERFACE_HANG_MASK_CTL2 0x57
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#define A3XX_RBBM_INTERFACE_HANG_MASK_CTL3 0x5A
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#define A3XX_RBBM_INT_CLEAR_CMD 0x061
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#define A3XX_RBBM_INT_0_MASK 0x063
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#define A3XX_RBBM_INT_0_STATUS 0x064
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#define A3XX_RBBM_GPU_BUSY_MASKED 0x88
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#define A3XX_RBBM_RBBM_CTL 0x100
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#define A3XX_RBBM_RBBM_CTL 0x100
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#define A3XX_RBBM_PERFCTR_PWR_1_LO 0x0EC
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#define A3XX_RBBM_PERFCTR_PWR_1_HI 0x0ED
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/* Following two are same as on A2XX, just in a different place */
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#define A3XX_CP_PFP_UCODE_ADDR 0x1C9
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#define A3XX_CP_PFP_UCODE_DATA 0x1CA
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#define A3XX_CP_HW_FAULT 0x45C
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#define A3XX_CP_AHB_FAULT 0x54D
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#define A3XX_CP_PROTECT_CTRL 0x45E
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#define A3XX_CP_PROTECT_STATUS 0x45F
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#define A3XX_CP_PROTECT_REG_0 0x460
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#define A3XX_CP_PROTECT_REG_1 0x461
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#define A3XX_CP_PROTECT_REG_2 0x462
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#define A3XX_CP_PROTECT_REG_3 0x463
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#define A3XX_CP_PROTECT_REG_4 0x464
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#define A3XX_CP_PROTECT_REG_5 0x465
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#define A3XX_CP_PROTECT_REG_6 0x466
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#define A3XX_CP_PROTECT_REG_7 0x467
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#define A3XX_CP_PROTECT_REG_8 0x468
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#define A3XX_CP_PROTECT_REG_9 0x469
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#define A3XX_CP_PROTECT_REG_A 0x46A
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#define A3XX_CP_PROTECT_REG_B 0x46B
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#define A3XX_CP_PROTECT_REG_C 0x46C
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#define A3XX_CP_PROTECT_REG_D 0x46D
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#define A3XX_CP_PROTECT_REG_E 0x46E
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#define A3XX_CP_PROTECT_REG_F 0x46F
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#define A3XX_CP_SCRATCH_REG2 0x57A
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#define A3XX_CP_SCRATCH_REG3 0x57B
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#define A3XX_VSC_BIN_SIZE 0xC01
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#define A3XX_VSC_SIZE_ADDRESS 0xC02
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#define A3XX_VSC_PIPE_CONFIG_0 0xC06
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#define A3XX_VSC_PIPE_DATA_ADDRESS_0 0xC07
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#define A3XX_VSC_PIPE_DATA_LENGTH_0 0xC08
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#define A3XX_VSC_PIPE_CONFIG_1 0xC09
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#define A3XX_VSC_PIPE_DATA_ADDRESS_1 0xC0A
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#define A3XX_VSC_PIPE_DATA_LENGTH_1 0xC0B
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#define A3XX_VSC_PIPE_CONFIG_2 0xC0C
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#define A3XX_VSC_PIPE_DATA_ADDRESS_2 0xC0D
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#define A3XX_VSC_PIPE_DATA_LENGTH_2 0xC0E
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#define A3XX_VSC_PIPE_CONFIG_3 0xC0F
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#define A3XX_VSC_PIPE_DATA_ADDRESS_3 0xC10
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#define A3XX_VSC_PIPE_DATA_LENGTH_3 0xC11
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#define A3XX_VSC_PIPE_CONFIG_4 0xC12
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#define A3XX_VSC_PIPE_DATA_ADDRESS_4 0xC13
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#define A3XX_VSC_PIPE_DATA_LENGTH_4 0xC14
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#define A3XX_VSC_PIPE_CONFIG_5 0xC15
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#define A3XX_VSC_PIPE_DATA_ADDRESS_5 0xC16
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#define A3XX_VSC_PIPE_DATA_LENGTH_5 0xC17
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#define A3XX_VSC_PIPE_CONFIG_6 0xC18
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#define A3XX_VSC_PIPE_DATA_ADDRESS_6 0xC19
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#define A3XX_VSC_PIPE_DATA_LENGTH_6 0xC1A
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#define A3XX_VSC_PIPE_CONFIG_7 0xC1B
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#define A3XX_VSC_PIPE_DATA_ADDRESS_7 0xC1C
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#define A3XX_VSC_PIPE_DATA_LENGTH_7 0xC1D
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#define A3XX_GRAS_CL_USER_PLANE_X0 0xCA0
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#define A3XX_GRAS_CL_USER_PLANE_Y0 0xCA1
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#define A3XX_GRAS_CL_USER_PLANE_Z0 0xCA2
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#define A3XX_GRAS_CL_USER_PLANE_W0 0xCA3
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#define A3XX_GRAS_CL_USER_PLANE_X1 0xCA4
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#define A3XX_GRAS_CL_USER_PLANE_Y1 0xCA5
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#define A3XX_GRAS_CL_USER_PLANE_Z1 0xCA6
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#define A3XX_GRAS_CL_USER_PLANE_W1 0xCA7
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#define A3XX_GRAS_CL_USER_PLANE_X2 0xCA8
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#define A3XX_GRAS_CL_USER_PLANE_Y2 0xCA9
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#define A3XX_GRAS_CL_USER_PLANE_Z2 0xCAA
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#define A3XX_GRAS_CL_USER_PLANE_W2 0xCAB
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#define A3XX_GRAS_CL_USER_PLANE_X3 0xCAC
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#define A3XX_GRAS_CL_USER_PLANE_Y3 0xCAD
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#define A3XX_GRAS_CL_USER_PLANE_Z3 0xCAE
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#define A3XX_GRAS_CL_USER_PLANE_W3 0xCAF
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#define A3XX_GRAS_CL_USER_PLANE_X4 0xCB0
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#define A3XX_GRAS_CL_USER_PLANE_Y4 0xCB1
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#define A3XX_GRAS_CL_USER_PLANE_Z4 0xCB2
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#define A3XX_GRAS_CL_USER_PLANE_W4 0xCB3
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#define A3XX_GRAS_CL_USER_PLANE_X5 0xCB4
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#define A3XX_GRAS_CL_USER_PLANE_Y5 0xCB5
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#define A3XX_GRAS_CL_USER_PLANE_Z5 0xCB6
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#define A3XX_GRAS_CL_USER_PLANE_W5 0xCB7
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#define A3XX_UCHE_CACHE_INVALIDATE0_REG 0xEA0
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#define A3XX_GRAS_CL_CLIP_CNTL 0x2040
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#define A3XX_GRAS_CL_GB_CLIP_ADJ 0x2044
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#define A3XX_GRAS_CL_VPORT_XOFFSET 0x2048
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#define A3XX_GRAS_CL_VPORT_ZOFFSET 0x204C
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#define A3XX_GRAS_CL_VPORT_ZSCALE 0x204D
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#define A3XX_GRAS_SU_POINT_MINMAX 0x2068
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#define A3XX_GRAS_SU_POINT_SIZE 0x2069
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#define A3XX_GRAS_SU_POLY_OFFSET_SCALE 0x206C
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#define A3XX_GRAS_SU_POLY_OFFSET_OFFSET 0x206D
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#define A3XX_GRAS_SU_MODE_CONTROL 0x2070
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#define A3XX_GRAS_SC_CONTROL 0x2072
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#define A3XX_GRAS_SC_SCREEN_SCISSOR_TL 0x2074
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#define A3XX_GRAS_SC_SCREEN_SCISSOR_BR 0x2075
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#define A3XX_GRAS_SC_WINDOW_SCISSOR_TL 0x2079
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#define A3XX_GRAS_SC_WINDOW_SCISSOR_BR 0x207A
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#define A3XX_RB_MODE_CONTROL 0x20C0
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#define A3XX_RB_RENDER_CONTROL 0x20C1
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#define A3XX_RB_MSAA_CONTROL 0x20C2
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#define A3XX_RB_MRT_CONTROL0 0x20C4
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#define A3XX_RB_MRT_BUF_INFO0 0x20C5
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#define A3XX_RB_MRT_BLEND_CONTROL0 0x20C7
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#define A3XX_RB_MRT_BLEND_CONTROL1 0x20CB
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#define A3XX_RB_MRT_BLEND_CONTROL2 0x20CF
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#define A3XX_RB_MRT_BLEND_CONTROL3 0x20D3
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#define A3XX_RB_BLEND_RED 0x20E4
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#define A3XX_RB_COPY_CONTROL 0x20EC
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#define A3XX_RB_COPY_DEST_INFO 0x20EF
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#define A3XX_RB_DEPTH_CONTROL 0x2100
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#define A3XX_RB_STENCIL_CONTROL 0x2104
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#define A3XX_PC_VSTREAM_CONTROL 0x21E4
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#define A3XX_PC_VERTEX_REUSE_BLOCK_CNTL 0x21EA
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#define A3XX_PC_PRIM_VTX_CNTL 0x21EC
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#define A3XX_PC_RESTART_INDEX 0x21ED
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#define A3XX_HLSQ_CONTROL_0_REG 0x2200
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#define A3XX_HLSQ_VS_CONTROL_REG 0x2204
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#define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG 0x2207
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#define A3XX_HLSQ_CL_NDRANGE_0_REG 0x220A
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#define A3XX_HLSQ_CL_NDRANGE_2_REG 0x220C
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#define A3XX_HLSQ_CL_CONTROL_0_REG 0x2211
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#define A3XX_HLSQ_CL_CONTROL_1_REG 0x2212
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#define A3XX_HLSQ_CL_KERNEL_CONST_REG 0x2214
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#define A3XX_HLSQ_CL_KERNEL_GROUP_X_REG 0x2215
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#define A3XX_HLSQ_CL_KERNEL_GROUP_Z_REG 0x2217
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#define A3XX_HLSQ_CL_WG_OFFSET_REG 0x221A
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#define A3XX_VFD_CONTROL_0 0x2240
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#define A3XX_VFD_INDEX_MIN 0x2242
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#define A3XX_VFD_FETCH_INSTR_0_0 0x2246
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#define A3XX_VFD_FETCH_INSTR_0_4 0x224E
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#define A3XX_VFD_DECODE_INSTR_0 0x2266
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#define A3XX_VFD_VS_THREADING_THRESHOLD 0x227E
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#define A3XX_VPC_ATTR 0x2280
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#define A3XX_VPC_VARY_CYLWRAP_ENABLE_1 0x228B
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#define A3XX_SP_SP_CTRL_REG 0x22C0
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#define A3XX_SP_VS_CTRL_REG0 0x22C4
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#define A3XX_SP_VS_CTRL_REG1 0x22C5
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#define A3XX_SP_VS_PARAM_REG 0x22C6
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#define A3XX_SP_VS_OUT_REG_7 0x22CE
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#define A3XX_SP_VS_VPC_DST_REG_0 0x22D0
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#define A3XX_SP_VS_OBJ_OFFSET_REG 0x22D4
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#define A3XX_SP_VS_PVT_MEM_SIZE_REG 0x22D8
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#define A3XX_SP_VS_LENGTH_REG 0x22DF
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#define A3XX_SP_FS_CTRL_REG0 0x22E0
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#define A3XX_SP_FS_CTRL_REG1 0x22E1
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#define A3XX_SP_FS_OBJ_OFFSET_REG 0x22E2
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#define A3XX_SP_FS_PVT_MEM_SIZE_REG 0x22E6
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#define A3XX_SP_FS_FLAT_SHAD_MODE_REG_0 0x22E8
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#define A3XX_SP_FS_FLAT_SHAD_MODE_REG_1 0x22E9
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#define A3XX_SP_FS_OUTPUT_REG 0x22EC
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#define A3XX_SP_FS_MRT_REG_0 0x22F0
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#define A3XX_SP_FS_IMAGE_OUTPUT_REG_0 0x22F4
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#define A3XX_SP_FS_IMAGE_OUTPUT_REG_3 0x22F7
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#define A3XX_SP_FS_LENGTH_REG 0x22FF
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#define A3XX_TPL1_TP_VS_TEX_OFFSET 0x2340
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#define A3XX_TPL1_TP_FS_TEX_OFFSET 0x2342
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#define A3XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR 0x2343
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#define A3XX_VBIF_FIXED_SORT_EN 0x300C
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#define A3XX_VBIF_FIXED_SORT_SEL0 0x300D
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#define A3XX_VBIF_FIXED_SORT_SEL1 0x300E
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/* Bit flags for RBBM_CTL */
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#define RBBM_RBBM_CTL_RESET_PWR_CTR1 (1 << 1)
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#define RBBM_RBBM_CTL_ENABLE_PWR_CTR1 (17 << 1)
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/* Various flags used by the context switch code */
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#define SP_MULTI 0
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#define SP_BUFFER_MODE 1
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#define SP_TWO_VTX_QUADS 0
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#define SP_PIXEL_BASED 0
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#define SP_R8G8B8A8_UNORM 8
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#define SP_FOUR_PIX_QUADS 1
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#define HLSQ_DIRECT 0
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#define HLSQ_BLOCK_ID_SP_VS 4
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#define HLSQ_SP_VS_INSTR 0
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#define HLSQ_SP_FS_INSTR 0
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#define HLSQ_BLOCK_ID_SP_FS 6
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#define HLSQ_TWO_PIX_QUADS 0
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#define HLSQ_TWO_VTX_QUADS 0
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#define HLSQ_BLOCK_ID_TP_TEX 2
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#define HLSQ_TP_TEX_SAMPLERS 0
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#define HLSQ_TP_TEX_MEMOBJ 1
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#define HLSQ_BLOCK_ID_TP_MIPMAP 3
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#define HLSQ_TP_MIPMAP_BASE 1
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#define HLSQ_FOUR_PIX_QUADS 1
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#define RB_FACTOR_ONE 1
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#define RB_BLEND_OP_ADD 0
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#define RB_FACTOR_ZERO 0
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#define RB_DITHER_DISABLE 0
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#define RB_DITHER_ALWAYS 1
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#define RB_FRAG_NEVER 0
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#define RB_ENDIAN_NONE 0
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#define RB_R8G8B8A8_UNORM 8
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#define RB_RESOLVE_PASS 2
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#define RB_CLEAR_MODE_RESOLVE 1
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#define RB_TILINGMODE_LINEAR 0
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#define RB_REF_NEVER 0
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#define RB_STENCIL_KEEP 0
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#define RB_RENDERING_PASS 0
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#define RB_TILINGMODE_32X32 2
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#define PC_DRAW_TRIANGLES 2
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#define PC_DI_PT_RECTLIST 8
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#define PC_DI_SRC_SEL_AUTO_INDEX 2
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#define PC_DI_INDEX_SIZE_16_BIT 0
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#define PC_DI_IGNORE_VISIBILITY 0
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#define PC_DI_PT_TRILIST 4
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#define PC_DI_SRC_SEL_IMMEDIATE 1
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#define PC_DI_INDEX_SIZE_32_BIT 1
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#define UCHE_ENTIRE_CACHE 1
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#define UCHE_OP_INVALIDATE 1
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/*
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* The following are bit field shifts within some of the registers defined
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* above. These are used in the context switch code in conjunction with the
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* _SET macro
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*/
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#define GRAS_CL_CLIP_CNTL_CLIP_DISABLE 16
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#define GRAS_CL_CLIP_CNTL_IJ_PERSP_CENTER 12
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#define GRAS_CL_CLIP_CNTL_PERSP_DIVISION_DISABLE 21
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#define GRAS_CL_CLIP_CNTL_VP_CLIP_CODE_IGNORE 19
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#define GRAS_CL_CLIP_CNTL_VP_XFORM_DISABLE 20
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#define GRAS_CL_CLIP_CNTL_ZFAR_CLIP_DISABLE 17
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#define GRAS_CL_VPORT_XSCALE_VPORT_XSCALE 0
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#define GRAS_CL_VPORT_YSCALE_VPORT_YSCALE 0
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#define GRAS_CL_VPORT_ZSCALE_VPORT_ZSCALE 0
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#define GRAS_SC_CONTROL_RASTER_MODE 12
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#define GRAS_SC_CONTROL_RENDER_MODE 4
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#define GRAS_SC_SCREEN_SCISSOR_BR_BR_X 0
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#define GRAS_SC_SCREEN_SCISSOR_BR_BR_Y 16
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#define GRAS_SC_WINDOW_SCISSOR_BR_BR_X 0
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#define GRAS_SC_WINDOW_SCISSOR_BR_BR_Y 16
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#define HLSQ_CONSTFSPRESERVEDRANGEREG_ENDENTRY 16
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#define HLSQ_CONSTFSPRESERVEDRANGEREG_STARTENTRY 0
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#define HLSQ_CTRL0REG_CHUNKDISABLE 26
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#define HLSQ_CTRL0REG_CONSTSWITCHMODE 27
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#define HLSQ_CTRL0REG_FSSUPERTHREADENABLE 6
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#define HLSQ_CTRL0REG_FSTHREADSIZE 4
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#define HLSQ_CTRL0REG_LAZYUPDATEDISABLE 28
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#define HLSQ_CTRL0REG_RESERVED2 10
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#define HLSQ_CTRL0REG_SPCONSTFULLUPDATE 29
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#define HLSQ_CTRL0REG_SPSHADERRESTART 9
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#define HLSQ_CTRL0REG_TPFULLUPDATE 30
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#define HLSQ_CTRL1REG_RESERVED1 9
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#define HLSQ_CTRL1REG_VSSUPERTHREADENABLE 8
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#define HLSQ_CTRL1REG_VSTHREADSIZE 6
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#define HLSQ_CTRL2REG_PRIMALLOCTHRESHOLD 26
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#define HLSQ_FSCTRLREG_FSCONSTLENGTH 0
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#define HLSQ_FSCTRLREG_FSCONSTSTARTOFFSET 12
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#define HLSQ_FSCTRLREG_FSINSTRLENGTH 24
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#define HLSQ_VSCTRLREG_VSINSTRLENGTH 24
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#define PC_PRIM_VTX_CONTROL_POLYMODE_BACK_PTYPE 8
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#define PC_PRIM_VTX_CONTROL_POLYMODE_FRONT_PTYPE 5
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#define PC_PRIM_VTX_CONTROL_PROVOKING_VTX_LAST 25
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#define PC_PRIM_VTX_CONTROL_STRIDE_IN_VPC 0
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#define PC_DRAW_INITIATOR_PRIM_TYPE 0
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#define PC_DRAW_INITIATOR_SOURCE_SELECT 6
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#define PC_DRAW_INITIATOR_VISIBILITY_CULLING_MODE 9
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#define PC_DRAW_INITIATOR_INDEX_SIZE 0x0B
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#define PC_DRAW_INITIATOR_SMALL_INDEX 0x0D
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#define PC_DRAW_INITIATOR_PRE_DRAW_INITIATOR_ENABLE 0x0E
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#define RB_COPYCONTROL_COPY_GMEM_BASE 14
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#define RB_COPYCONTROL_RESOLVE_CLEAR_MODE 4
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#define RB_COPYDESTBASE_COPY_DEST_BASE 4
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#define RB_COPYDESTINFO_COPY_COMPONENT_ENABLE 14
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#define RB_COPYDESTINFO_COPY_DEST_ENDIAN 18
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#define RB_COPYDESTINFO_COPY_DEST_FORMAT 2
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#define RB_COPYDESTINFO_COPY_DEST_TILE 0
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#define RB_COPYDESTPITCH_COPY_DEST_PITCH 0
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#define RB_DEPTHCONTROL_Z_TEST_FUNC 4
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#define RB_MODECONTROL_RENDER_MODE 8
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#define RB_MODECONTROL_MARB_CACHE_SPLIT_MODE 15
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#define RB_MODECONTROL_PACKER_TIMER_ENABLE 16
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#define RB_MRTBLENDCONTROL_ALPHA_BLEND_OPCODE 21
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#define RB_MRTBLENDCONTROL_ALPHA_DEST_FACTOR 24
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#define RB_MRTBLENDCONTROL_ALPHA_SRC_FACTOR 16
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#define RB_MRTBLENDCONTROL_CLAMP_ENABLE 29
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#define RB_MRTBLENDCONTROL_RGB_BLEND_OPCODE 5
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#define RB_MRTBLENDCONTROL_RGB_DEST_FACTOR 8
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#define RB_MRTBLENDCONTROL_RGB_SRC_FACTOR 0
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#define RB_MRTBUFBASE_COLOR_BUF_BASE 4
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#define RB_MRTBUFINFO_COLOR_BUF_PITCH 17
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#define RB_MRTBUFINFO_COLOR_FORMAT 0
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#define RB_MRTBUFINFO_COLOR_TILE_MODE 6
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#define RB_MRTCONTROL_COMPONENT_ENABLE 24
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#define RB_MRTCONTROL_DITHER_MODE 12
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#define RB_MRTCONTROL_READ_DEST_ENABLE 3
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#define RB_MRTCONTROL_ROP_CODE 8
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#define RB_MSAACONTROL_MSAA_DISABLE 10
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#define RB_MSAACONTROL_SAMPLE_MASK 16
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#define RB_RENDERCONTROL_ALPHA_TEST_FUNC 24
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#define RB_RENDERCONTROL_BIN_WIDTH 4
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#define RB_RENDERCONTROL_DISABLE_COLOR_PIPE 12
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#define RB_STENCILCONTROL_STENCIL_FAIL 11
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#define RB_STENCILCONTROL_STENCIL_FAIL_BF 23
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#define RB_STENCILCONTROL_STENCIL_FUNC 8
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#define RB_STENCILCONTROL_STENCIL_FUNC_BF 20
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#define RB_STENCILCONTROL_STENCIL_ZFAIL 17
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#define RB_STENCILCONTROL_STENCIL_ZFAIL_BF 29
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#define RB_STENCILCONTROL_STENCIL_ZPASS 14
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#define RB_STENCILCONTROL_STENCIL_ZPASS_BF 26
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#define SP_FSCTRLREG0_FSFULLREGFOOTPRINT 10
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#define SP_FSCTRLREG0_FSICACHEINVALID 2
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#define SP_FSCTRLREG0_FSINOUTREGOVERLAP 18
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#define SP_FSCTRLREG0_FSINSTRBUFFERMODE 1
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#define SP_FSCTRLREG0_FSLENGTH 24
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#define SP_FSCTRLREG0_FSSUPERTHREADMODE 21
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#define SP_FSCTRLREG0_FSTHREADMODE 0
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#define SP_FSCTRLREG0_FSTHREADSIZE 20
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#define SP_FSCTRLREG0_PIXLODENABLE 22
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#define SP_FSCTRLREG1_FSCONSTLENGTH 0
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#define SP_FSCTRLREG1_FSINITIALOUTSTANDING 20
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#define SP_FSCTRLREG1_HALFPRECVAROFFSET 24
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#define SP_FSMRTREG_REGID 0
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#define SP_FSOUTREG_PAD0 2
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#define SP_IMAGEOUTPUTREG_MRTFORMAT 0
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#define SP_IMAGEOUTPUTREG_PAD0 6
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#define SP_OBJOFFSETREG_CONSTOBJECTSTARTOFFSET 16
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#define SP_OBJOFFSETREG_SHADEROBJOFFSETINIC 25
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#define SP_SHADERLENGTH_LEN 0
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#define SP_SPCTRLREG_CONSTMODE 18
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#define SP_SPCTRLREG_SLEEPMODE 20
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#define SP_VSCTRLREG0_VSFULLREGFOOTPRINT 10
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#define SP_VSCTRLREG0_VSICACHEINVALID 2
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#define SP_VSCTRLREG0_VSINSTRBUFFERMODE 1
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#define SP_VSCTRLREG0_VSLENGTH 24
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#define SP_VSCTRLREG0_VSSUPERTHREADMODE 21
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#define SP_VSCTRLREG0_VSTHREADMODE 0
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#define SP_VSCTRLREG0_VSTHREADSIZE 20
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#define SP_VSCTRLREG1_VSINITIALOUTSTANDING 24
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#define SP_VSOUTREG_COMPMASK0 9
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#define SP_VSPARAMREG_POSREGID 0
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#define SP_VSPARAMREG_PSIZEREGID 8
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#define SP_VSPARAMREG_TOTALVSOUTVAR 20
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#define SP_VSVPCDSTREG_OUTLOC0 0
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#define TPL1_TPTEXOFFSETREG_BASETABLEPTR 16
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#define TPL1_TPTEXOFFSETREG_MEMOBJOFFSET 8
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#define TPL1_TPTEXOFFSETREG_SAMPLEROFFSET 0
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#define UCHE_INVALIDATE1REG_OPCODE 0x1C
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#define UCHE_INVALIDATE1REG_ALLORPORTION 0x1F
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#define VFD_BASEADDR_BASEADDR 0
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#define VFD_CTRLREG0_PACKETSIZE 18
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#define VFD_CTRLREG0_STRMDECINSTRCNT 22
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#define VFD_CTRLREG0_STRMFETCHINSTRCNT 27
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#define VFD_CTRLREG0_TOTALATTRTOVS 0
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#define VFD_CTRLREG1_MAXSTORAGE 0
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#define VFD_CTRLREG1_REGID4INST 24
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#define VFD_CTRLREG1_REGID4VTX 16
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#define VFD_DECODEINSTRUCTIONS_CONSTFILL 4
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#define VFD_DECODEINSTRUCTIONS_FORMAT 6
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#define VFD_DECODEINSTRUCTIONS_LASTCOMPVALID 29
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#define VFD_DECODEINSTRUCTIONS_REGID 12
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#define VFD_DECODEINSTRUCTIONS_SHIFTCNT 24
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#define VFD_DECODEINSTRUCTIONS_SWITCHNEXT 30
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#define VFD_DECODEINSTRUCTIONS_WRITEMASK 0
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#define VFD_FETCHINSTRUCTIONS_BUFSTRIDE 7
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#define VFD_FETCHINSTRUCTIONS_FETCHSIZE 0
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#define VFD_FETCHINSTRUCTIONS_INDEXDECODE 18
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#define VFD_FETCHINSTRUCTIONS_STEPRATE 24
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#define VFD_FETCHINSTRUCTIONS_SWITCHNEXT 17
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#define VFD_THREADINGTHRESHOLD_REGID_VTXCNT 8
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#define VFD_THREADINGTHRESHOLD_RESERVED6 4
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#define VPC_VPCATTR_LMSIZE 28
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#define VPC_VPCATTR_THRHDASSIGN 12
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#define VPC_VPCATTR_TOTALATTR 0
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#define VPC_VPCPACK_NUMFPNONPOSVAR 8
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#define VPC_VPCPACK_NUMNONPOSVSVAR 16
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#define VPC_VPCVARPSREPLMODE_COMPONENT08 0
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#define VPC_VPCVARPSREPLMODE_COMPONENT09 2
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|
#define VPC_VPCVARPSREPLMODE_COMPONENT0A 4
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#define VPC_VPCVARPSREPLMODE_COMPONENT0B 6
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#define VPC_VPCVARPSREPLMODE_COMPONENT0C 8
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#define VPC_VPCVARPSREPLMODE_COMPONENT0D 10
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#define VPC_VPCVARPSREPLMODE_COMPONENT0E 12
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#define VPC_VPCVARPSREPLMODE_COMPONENT0F 14
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#define VPC_VPCVARPSREPLMODE_COMPONENT10 16
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#define VPC_VPCVARPSREPLMODE_COMPONENT11 18
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#define VPC_VPCVARPSREPLMODE_COMPONENT12 20
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#define VPC_VPCVARPSREPLMODE_COMPONENT13 22
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#define VPC_VPCVARPSREPLMODE_COMPONENT14 24
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|
#define VPC_VPCVARPSREPLMODE_COMPONENT15 26
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|
#define VPC_VPCVARPSREPLMODE_COMPONENT16 28
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#define VPC_VPCVARPSREPLMODE_COMPONENT17 30
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#endif
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