msm: kgsl: Add support for the A3XX family of GPUs
Add support for the A320, the first of the new generation of Adreno GPUs.
This commit is contained in:
SecureCRT
parent
be4c38e2f5
commit
0885149512
1
drivers/gpu/msm/Makefile
Normal file → Executable file
1
drivers/gpu/msm/Makefile
Normal file → Executable file
@ -19,6 +19,7 @@ msm_adreno-y += \
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adreno_drawctxt.o \
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adreno_postmortem.o \
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adreno_a2xx.o \
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adreno_a3xx.o \
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adreno.o
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msm_adreno-$(CONFIG_DEBUG_FS) += adreno_debugfs.o
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453
drivers/gpu/msm/a3xx_reg.h
Executable file
453
drivers/gpu/msm/a3xx_reg.h
Executable file
@ -0,0 +1,453 @@
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/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef _A300_REG_H
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#define _A300_REG_H
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/* Interrupt bit positions within RBBM_INT_0 */
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#define A3XX_INT_RBBM_GPU_IDLE 0
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#define A3XX_INT_RBBM_AHB_ERROR 1
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#define A3XX_INT_RBBM_REG_TIMEOUT 2
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#define A3XX_INT_RBBM_ME_MS_TIMEOUT 3
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#define A3XX_INT_RBBM_PFP_MS_TIMEOUT 4
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#define A3XX_INT_RBBM_ATB_BUS_OVERFLOW 5
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#define A3XX_INT_VFD_ERROR 6
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#define A3XX_INT_CP_SW_INT 7
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#define A3XX_INT_CP_T0_PACKET_IN_IB 8
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#define A3XX_INT_CP_OPCODE_ERROR 9
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#define A3XX_INT_CP_RESERVED_BIT_ERROR 10
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#define A3XX_INT_CP_HW_FAULT 11
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#define A3xx_INT_CP_DMA 12
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#define A3XX_INT_CP_IB2_INT 13
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#define A3XX_INT_CP_IB1_INT 14
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#define A3XX_INT_CP_RB_INT 15
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#define A3XX_INT_CP_REG_PROTECT_FAULT 16
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#define A3XX_INT_CP_RB_DONE_TS 17
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#define A3XX_INT_CP_VS_DONE_TS 18
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#define A3XX_INT_CP_PS_DONE_TS 19
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#define A3XX_INT_CACHE_FLUSH_TS 20
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#define A3XX_INT_CP_AHB_ERROR_HALT 21
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#define A3XX_INT_MISC_HANG_DETECT 24
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#define A3XX_INT_UCHE_OOB_ACCESS 25
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/* Register definitions */
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#define A3XX_RBBM_HW_VERSION 0x000
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#define A3XX_RBBM_HW_RELEASE 0x001
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#define A3XX_RBBM_HW_CONFIGURATION 0x002
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#define A3XX_RBBM_SW_RESET_CMD 0x018
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#define A3XX_RBBM_AHB_CTL0 0x020
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#define A3XX_RBBM_AHB_CTL1 0x021
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#define A3XX_RBBM_AHB_CMD 0x022
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#define A3XX_RBBM_AHB_ERROR_STATUS 0x027
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#define A3XX_RBBM_GPR0_CTL 0x02E
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/* This the same register as on A2XX, just in a different place */
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#define A3XX_RBBM_STATUS 0x030
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#define A3XX_RBBM_INTERFACE_HANG_INT_CTL 0x50
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#define A3XX_RBBM_INTERFACE_HANG_MASK_CTL0 0x51
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#define A3XX_RBBM_INTERFACE_HANG_MASK_CTL1 0x54
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#define A3XX_RBBM_INTERFACE_HANG_MASK_CTL2 0x57
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#define A3XX_RBBM_INTERFACE_HANG_MASK_CTL3 0x5A
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#define A3XX_RBBM_INT_CLEAR_CMD 0x061
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#define A3XX_RBBM_INT_0_MASK 0x063
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#define A3XX_RBBM_INT_0_STATUS 0x064
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#define A3XX_RBBM_GPU_BUSY_MASKED 0x88
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#define A3XX_RBBM_RBBM_CTL 0x100
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#define A3XX_RBBM_RBBM_CTL 0x100
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#define A3XX_RBBM_PERFCTR_PWR_1_LO 0x0EC
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#define A3XX_RBBM_PERFCTR_PWR_1_HI 0x0ED
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/* Following two are same as on A2XX, just in a different place */
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#define A3XX_CP_PFP_UCODE_ADDR 0x1C9
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#define A3XX_CP_PFP_UCODE_DATA 0x1CA
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#define A3XX_CP_HW_FAULT 0x45C
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#define A3XX_CP_AHB_FAULT 0x54D
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#define A3XX_CP_PROTECT_CTRL 0x45E
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#define A3XX_CP_PROTECT_STATUS 0x45F
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#define A3XX_CP_PROTECT_REG_0 0x460
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#define A3XX_CP_PROTECT_REG_1 0x461
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#define A3XX_CP_PROTECT_REG_2 0x462
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#define A3XX_CP_PROTECT_REG_3 0x463
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#define A3XX_CP_PROTECT_REG_4 0x464
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#define A3XX_CP_PROTECT_REG_5 0x465
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#define A3XX_CP_PROTECT_REG_6 0x466
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#define A3XX_CP_PROTECT_REG_7 0x467
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#define A3XX_CP_PROTECT_REG_8 0x468
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#define A3XX_CP_PROTECT_REG_9 0x469
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#define A3XX_CP_PROTECT_REG_A 0x46A
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#define A3XX_CP_PROTECT_REG_B 0x46B
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#define A3XX_CP_PROTECT_REG_C 0x46C
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#define A3XX_CP_PROTECT_REG_D 0x46D
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#define A3XX_CP_PROTECT_REG_E 0x46E
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#define A3XX_CP_PROTECT_REG_F 0x46F
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#define A3XX_CP_SCRATCH_REG2 0x57A
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#define A3XX_CP_SCRATCH_REG3 0x57B
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#define A3XX_VSC_BIN_SIZE 0xC01
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#define A3XX_VSC_SIZE_ADDRESS 0xC02
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#define A3XX_VSC_PIPE_CONFIG_0 0xC06
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#define A3XX_VSC_PIPE_DATA_ADDRESS_0 0xC07
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#define A3XX_VSC_PIPE_DATA_LENGTH_0 0xC08
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#define A3XX_VSC_PIPE_CONFIG_1 0xC09
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#define A3XX_VSC_PIPE_DATA_ADDRESS_1 0xC0A
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#define A3XX_VSC_PIPE_DATA_LENGTH_1 0xC0B
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#define A3XX_VSC_PIPE_CONFIG_2 0xC0C
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#define A3XX_VSC_PIPE_DATA_ADDRESS_2 0xC0D
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#define A3XX_VSC_PIPE_DATA_LENGTH_2 0xC0E
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#define A3XX_VSC_PIPE_CONFIG_3 0xC0F
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#define A3XX_VSC_PIPE_DATA_ADDRESS_3 0xC10
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#define A3XX_VSC_PIPE_DATA_LENGTH_3 0xC11
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#define A3XX_VSC_PIPE_CONFIG_4 0xC12
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#define A3XX_VSC_PIPE_DATA_ADDRESS_4 0xC13
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#define A3XX_VSC_PIPE_DATA_LENGTH_4 0xC14
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#define A3XX_VSC_PIPE_CONFIG_5 0xC15
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#define A3XX_VSC_PIPE_DATA_ADDRESS_5 0xC16
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#define A3XX_VSC_PIPE_DATA_LENGTH_5 0xC17
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#define A3XX_VSC_PIPE_CONFIG_6 0xC18
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#define A3XX_VSC_PIPE_DATA_ADDRESS_6 0xC19
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#define A3XX_VSC_PIPE_DATA_LENGTH_6 0xC1A
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#define A3XX_VSC_PIPE_CONFIG_7 0xC1B
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#define A3XX_VSC_PIPE_DATA_ADDRESS_7 0xC1C
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#define A3XX_VSC_PIPE_DATA_LENGTH_7 0xC1D
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#define A3XX_GRAS_CL_USER_PLANE_X0 0xCA0
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#define A3XX_GRAS_CL_USER_PLANE_Y0 0xCA1
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#define A3XX_GRAS_CL_USER_PLANE_Z0 0xCA2
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#define A3XX_GRAS_CL_USER_PLANE_W0 0xCA3
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#define A3XX_GRAS_CL_USER_PLANE_X1 0xCA4
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#define A3XX_GRAS_CL_USER_PLANE_Y1 0xCA5
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#define A3XX_GRAS_CL_USER_PLANE_Z1 0xCA6
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#define A3XX_GRAS_CL_USER_PLANE_W1 0xCA7
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#define A3XX_GRAS_CL_USER_PLANE_X2 0xCA8
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#define A3XX_GRAS_CL_USER_PLANE_Y2 0xCA9
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#define A3XX_GRAS_CL_USER_PLANE_Z2 0xCAA
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#define A3XX_GRAS_CL_USER_PLANE_W2 0xCAB
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#define A3XX_GRAS_CL_USER_PLANE_X3 0xCAC
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#define A3XX_GRAS_CL_USER_PLANE_Y3 0xCAD
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#define A3XX_GRAS_CL_USER_PLANE_Z3 0xCAE
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#define A3XX_GRAS_CL_USER_PLANE_W3 0xCAF
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#define A3XX_GRAS_CL_USER_PLANE_X4 0xCB0
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#define A3XX_GRAS_CL_USER_PLANE_Y4 0xCB1
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#define A3XX_GRAS_CL_USER_PLANE_Z4 0xCB2
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#define A3XX_GRAS_CL_USER_PLANE_W4 0xCB3
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#define A3XX_GRAS_CL_USER_PLANE_X5 0xCB4
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#define A3XX_GRAS_CL_USER_PLANE_Y5 0xCB5
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#define A3XX_GRAS_CL_USER_PLANE_Z5 0xCB6
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#define A3XX_GRAS_CL_USER_PLANE_W5 0xCB7
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#define A3XX_UCHE_CACHE_INVALIDATE0_REG 0xEA0
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#define A3XX_GRAS_CL_CLIP_CNTL 0x2040
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#define A3XX_GRAS_CL_GB_CLIP_ADJ 0x2044
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#define A3XX_GRAS_CL_VPORT_XOFFSET 0x2048
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#define A3XX_GRAS_CL_VPORT_ZOFFSET 0x204C
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#define A3XX_GRAS_CL_VPORT_ZSCALE 0x204D
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#define A3XX_GRAS_SU_POINT_MINMAX 0x2068
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#define A3XX_GRAS_SU_POINT_SIZE 0x2069
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#define A3XX_GRAS_SU_POLY_OFFSET_SCALE 0x206C
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#define A3XX_GRAS_SU_POLY_OFFSET_OFFSET 0x206D
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#define A3XX_GRAS_SU_MODE_CONTROL 0x2070
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#define A3XX_GRAS_SC_CONTROL 0x2072
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#define A3XX_GRAS_SC_SCREEN_SCISSOR_TL 0x2074
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#define A3XX_GRAS_SC_SCREEN_SCISSOR_BR 0x2075
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#define A3XX_GRAS_SC_WINDOW_SCISSOR_TL 0x2079
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#define A3XX_GRAS_SC_WINDOW_SCISSOR_BR 0x207A
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#define A3XX_RB_MODE_CONTROL 0x20C0
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#define A3XX_RB_RENDER_CONTROL 0x20C1
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#define A3XX_RB_MSAA_CONTROL 0x20C2
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#define A3XX_RB_MRT_CONTROL0 0x20C4
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#define A3XX_RB_MRT_BUF_INFO0 0x20C5
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#define A3XX_RB_MRT_BLEND_CONTROL0 0x20C7
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#define A3XX_RB_MRT_BLEND_CONTROL1 0x20CB
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#define A3XX_RB_MRT_BLEND_CONTROL2 0x20CF
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#define A3XX_RB_MRT_BLEND_CONTROL3 0x20D3
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#define A3XX_RB_BLEND_RED 0x20E4
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#define A3XX_RB_COPY_CONTROL 0x20EC
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#define A3XX_RB_COPY_DEST_INFO 0x20EF
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#define A3XX_RB_DEPTH_CONTROL 0x2100
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#define A3XX_RB_STENCIL_CONTROL 0x2104
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#define A3XX_PC_VSTREAM_CONTROL 0x21E4
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#define A3XX_PC_VERTEX_REUSE_BLOCK_CNTL 0x21EA
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#define A3XX_PC_PRIM_VTX_CNTL 0x21EC
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#define A3XX_PC_RESTART_INDEX 0x21ED
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#define A3XX_HLSQ_CONTROL_0_REG 0x2200
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#define A3XX_HLSQ_VS_CONTROL_REG 0x2204
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#define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG 0x2207
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#define A3XX_HLSQ_CL_NDRANGE_0_REG 0x220A
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#define A3XX_HLSQ_CL_NDRANGE_2_REG 0x220C
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#define A3XX_HLSQ_CL_CONTROL_0_REG 0x2211
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#define A3XX_HLSQ_CL_CONTROL_1_REG 0x2212
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#define A3XX_HLSQ_CL_KERNEL_CONST_REG 0x2214
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#define A3XX_HLSQ_CL_KERNEL_GROUP_X_REG 0x2215
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#define A3XX_HLSQ_CL_KERNEL_GROUP_Z_REG 0x2217
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#define A3XX_HLSQ_CL_WG_OFFSET_REG 0x221A
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#define A3XX_VFD_CONTROL_0 0x2240
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#define A3XX_VFD_INDEX_MIN 0x2242
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#define A3XX_VFD_FETCH_INSTR_0_0 0x2246
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#define A3XX_VFD_FETCH_INSTR_0_4 0x224E
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#define A3XX_VFD_DECODE_INSTR_0 0x2266
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#define A3XX_VFD_VS_THREADING_THRESHOLD 0x227E
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#define A3XX_VPC_ATTR 0x2280
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#define A3XX_VPC_VARY_CYLWRAP_ENABLE_1 0x228B
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#define A3XX_SP_SP_CTRL_REG 0x22C0
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#define A3XX_SP_VS_CTRL_REG0 0x22C4
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#define A3XX_SP_VS_CTRL_REG1 0x22C5
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#define A3XX_SP_VS_PARAM_REG 0x22C6
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#define A3XX_SP_VS_OUT_REG_7 0x22CE
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#define A3XX_SP_VS_VPC_DST_REG_0 0x22D0
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#define A3XX_SP_VS_OBJ_OFFSET_REG 0x22D4
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#define A3XX_SP_VS_PVT_MEM_SIZE_REG 0x22D8
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#define A3XX_SP_VS_LENGTH_REG 0x22DF
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#define A3XX_SP_FS_CTRL_REG0 0x22E0
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#define A3XX_SP_FS_CTRL_REG1 0x22E1
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#define A3XX_SP_FS_OBJ_OFFSET_REG 0x22E2
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#define A3XX_SP_FS_PVT_MEM_SIZE_REG 0x22E6
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#define A3XX_SP_FS_FLAT_SHAD_MODE_REG_0 0x22E8
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#define A3XX_SP_FS_FLAT_SHAD_MODE_REG_1 0x22E9
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#define A3XX_SP_FS_OUTPUT_REG 0x22EC
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#define A3XX_SP_FS_MRT_REG_0 0x22F0
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#define A3XX_SP_FS_IMAGE_OUTPUT_REG_0 0x22F4
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#define A3XX_SP_FS_IMAGE_OUTPUT_REG_3 0x22F7
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#define A3XX_SP_FS_LENGTH_REG 0x22FF
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#define A3XX_TPL1_TP_VS_TEX_OFFSET 0x2340
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#define A3XX_TPL1_TP_FS_TEX_OFFSET 0x2342
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#define A3XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR 0x2343
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#define A3XX_VBIF_FIXED_SORT_EN 0x300C
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#define A3XX_VBIF_FIXED_SORT_SEL0 0x300D
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#define A3XX_VBIF_FIXED_SORT_SEL1 0x300E
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/* Bit flags for RBBM_CTL */
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#define RBBM_RBBM_CTL_RESET_PWR_CTR1 (1 << 1)
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#define RBBM_RBBM_CTL_ENABLE_PWR_CTR1 (17 << 1)
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/* Various flags used by the context switch code */
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#define SP_MULTI 0
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#define SP_BUFFER_MODE 1
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#define SP_TWO_VTX_QUADS 0
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#define SP_PIXEL_BASED 0
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#define SP_R8G8B8A8_UNORM 8
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#define SP_FOUR_PIX_QUADS 1
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#define HLSQ_DIRECT 0
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#define HLSQ_BLOCK_ID_SP_VS 4
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#define HLSQ_SP_VS_INSTR 0
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#define HLSQ_SP_FS_INSTR 0
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#define HLSQ_BLOCK_ID_SP_FS 6
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#define HLSQ_TWO_PIX_QUADS 0
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#define HLSQ_TWO_VTX_QUADS 0
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#define HLSQ_BLOCK_ID_TP_TEX 2
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#define HLSQ_TP_TEX_SAMPLERS 0
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#define HLSQ_TP_TEX_MEMOBJ 1
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#define HLSQ_BLOCK_ID_TP_MIPMAP 3
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#define HLSQ_TP_MIPMAP_BASE 1
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#define HLSQ_FOUR_PIX_QUADS 1
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#define RB_FACTOR_ONE 1
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#define RB_BLEND_OP_ADD 0
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#define RB_FACTOR_ZERO 0
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#define RB_DITHER_DISABLE 0
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#define RB_DITHER_ALWAYS 1
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#define RB_FRAG_NEVER 0
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#define RB_ENDIAN_NONE 0
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#define RB_R8G8B8A8_UNORM 8
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#define RB_RESOLVE_PASS 2
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#define RB_CLEAR_MODE_RESOLVE 1
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#define RB_TILINGMODE_LINEAR 0
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#define RB_REF_NEVER 0
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#define RB_STENCIL_KEEP 0
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#define RB_RENDERING_PASS 0
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#define RB_TILINGMODE_32X32 2
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#define PC_DRAW_TRIANGLES 2
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#define PC_DI_PT_RECTLIST 8
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#define PC_DI_SRC_SEL_AUTO_INDEX 2
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#define PC_DI_INDEX_SIZE_16_BIT 0
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#define PC_DI_IGNORE_VISIBILITY 0
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#define PC_DI_PT_TRILIST 4
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#define PC_DI_SRC_SEL_IMMEDIATE 1
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#define PC_DI_INDEX_SIZE_32_BIT 1
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#define UCHE_ENTIRE_CACHE 1
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#define UCHE_OP_INVALIDATE 1
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/*
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* The following are bit field shifts within some of the registers defined
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* above. These are used in the context switch code in conjunction with the
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* _SET macro
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*/
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#define GRAS_CL_CLIP_CNTL_CLIP_DISABLE 16
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#define GRAS_CL_CLIP_CNTL_IJ_PERSP_CENTER 12
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#define GRAS_CL_CLIP_CNTL_PERSP_DIVISION_DISABLE 21
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#define GRAS_CL_CLIP_CNTL_VP_CLIP_CODE_IGNORE 19
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#define GRAS_CL_CLIP_CNTL_VP_XFORM_DISABLE 20
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#define GRAS_CL_CLIP_CNTL_ZFAR_CLIP_DISABLE 17
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#define GRAS_CL_VPORT_XSCALE_VPORT_XSCALE 0
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#define GRAS_CL_VPORT_YSCALE_VPORT_YSCALE 0
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#define GRAS_CL_VPORT_ZSCALE_VPORT_ZSCALE 0
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#define GRAS_SC_CONTROL_RASTER_MODE 12
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#define GRAS_SC_CONTROL_RENDER_MODE 4
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#define GRAS_SC_SCREEN_SCISSOR_BR_BR_X 0
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#define GRAS_SC_SCREEN_SCISSOR_BR_BR_Y 16
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#define GRAS_SC_WINDOW_SCISSOR_BR_BR_X 0
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#define GRAS_SC_WINDOW_SCISSOR_BR_BR_Y 16
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#define HLSQ_CONSTFSPRESERVEDRANGEREG_ENDENTRY 16
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#define HLSQ_CONSTFSPRESERVEDRANGEREG_STARTENTRY 0
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#define HLSQ_CTRL0REG_CHUNKDISABLE 26
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#define HLSQ_CTRL0REG_CONSTSWITCHMODE 27
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#define HLSQ_CTRL0REG_FSSUPERTHREADENABLE 6
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#define HLSQ_CTRL0REG_FSTHREADSIZE 4
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#define HLSQ_CTRL0REG_LAZYUPDATEDISABLE 28
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||||
#define HLSQ_CTRL0REG_RESERVED2 10
|
||||
#define HLSQ_CTRL0REG_SPCONSTFULLUPDATE 29
|
||||
#define HLSQ_CTRL0REG_SPSHADERRESTART 9
|
||||
#define HLSQ_CTRL0REG_TPFULLUPDATE 30
|
||||
#define HLSQ_CTRL1REG_RESERVED1 9
|
||||
#define HLSQ_CTRL1REG_VSSUPERTHREADENABLE 8
|
||||
#define HLSQ_CTRL1REG_VSTHREADSIZE 6
|
||||
#define HLSQ_CTRL2REG_PRIMALLOCTHRESHOLD 26
|
||||
#define HLSQ_FSCTRLREG_FSCONSTLENGTH 0
|
||||
#define HLSQ_FSCTRLREG_FSCONSTSTARTOFFSET 12
|
||||
#define HLSQ_FSCTRLREG_FSINSTRLENGTH 24
|
||||
#define HLSQ_VSCTRLREG_VSINSTRLENGTH 24
|
||||
#define PC_PRIM_VTX_CONTROL_POLYMODE_BACK_PTYPE 8
|
||||
#define PC_PRIM_VTX_CONTROL_POLYMODE_FRONT_PTYPE 5
|
||||
#define PC_PRIM_VTX_CONTROL_PROVOKING_VTX_LAST 25
|
||||
#define PC_PRIM_VTX_CONTROL_STRIDE_IN_VPC 0
|
||||
#define PC_DRAW_INITIATOR_PRIM_TYPE 0
|
||||
#define PC_DRAW_INITIATOR_SOURCE_SELECT 6
|
||||
#define PC_DRAW_INITIATOR_VISIBILITY_CULLING_MODE 9
|
||||
#define PC_DRAW_INITIATOR_INDEX_SIZE 0x0B
|
||||
#define PC_DRAW_INITIATOR_SMALL_INDEX 0x0D
|
||||
#define PC_DRAW_INITIATOR_PRE_DRAW_INITIATOR_ENABLE 0x0E
|
||||
#define RB_COPYCONTROL_COPY_GMEM_BASE 14
|
||||
#define RB_COPYCONTROL_RESOLVE_CLEAR_MODE 4
|
||||
#define RB_COPYDESTBASE_COPY_DEST_BASE 4
|
||||
#define RB_COPYDESTINFO_COPY_COMPONENT_ENABLE 14
|
||||
#define RB_COPYDESTINFO_COPY_DEST_ENDIAN 18
|
||||
#define RB_COPYDESTINFO_COPY_DEST_FORMAT 2
|
||||
#define RB_COPYDESTINFO_COPY_DEST_TILE 0
|
||||
#define RB_COPYDESTPITCH_COPY_DEST_PITCH 0
|
||||
#define RB_DEPTHCONTROL_Z_TEST_FUNC 4
|
||||
#define RB_MODECONTROL_RENDER_MODE 8
|
||||
#define RB_MODECONTROL_MARB_CACHE_SPLIT_MODE 15
|
||||
#define RB_MODECONTROL_PACKER_TIMER_ENABLE 16
|
||||
#define RB_MRTBLENDCONTROL_ALPHA_BLEND_OPCODE 21
|
||||
#define RB_MRTBLENDCONTROL_ALPHA_DEST_FACTOR 24
|
||||
#define RB_MRTBLENDCONTROL_ALPHA_SRC_FACTOR 16
|
||||
#define RB_MRTBLENDCONTROL_CLAMP_ENABLE 29
|
||||
#define RB_MRTBLENDCONTROL_RGB_BLEND_OPCODE 5
|
||||
#define RB_MRTBLENDCONTROL_RGB_DEST_FACTOR 8
|
||||
#define RB_MRTBLENDCONTROL_RGB_SRC_FACTOR 0
|
||||
#define RB_MRTBUFBASE_COLOR_BUF_BASE 4
|
||||
#define RB_MRTBUFINFO_COLOR_BUF_PITCH 17
|
||||
#define RB_MRTBUFINFO_COLOR_FORMAT 0
|
||||
#define RB_MRTBUFINFO_COLOR_TILE_MODE 6
|
||||
#define RB_MRTCONTROL_COMPONENT_ENABLE 24
|
||||
#define RB_MRTCONTROL_DITHER_MODE 12
|
||||
#define RB_MRTCONTROL_READ_DEST_ENABLE 3
|
||||
#define RB_MRTCONTROL_ROP_CODE 8
|
||||
#define RB_MSAACONTROL_MSAA_DISABLE 10
|
||||
#define RB_MSAACONTROL_SAMPLE_MASK 16
|
||||
#define RB_RENDERCONTROL_ALPHA_TEST_FUNC 24
|
||||
#define RB_RENDERCONTROL_BIN_WIDTH 4
|
||||
#define RB_RENDERCONTROL_DISABLE_COLOR_PIPE 12
|
||||
#define RB_STENCILCONTROL_STENCIL_FAIL 11
|
||||
#define RB_STENCILCONTROL_STENCIL_FAIL_BF 23
|
||||
#define RB_STENCILCONTROL_STENCIL_FUNC 8
|
||||
#define RB_STENCILCONTROL_STENCIL_FUNC_BF 20
|
||||
#define RB_STENCILCONTROL_STENCIL_ZFAIL 17
|
||||
#define RB_STENCILCONTROL_STENCIL_ZFAIL_BF 29
|
||||
#define RB_STENCILCONTROL_STENCIL_ZPASS 14
|
||||
#define RB_STENCILCONTROL_STENCIL_ZPASS_BF 26
|
||||
#define SP_FSCTRLREG0_FSFULLREGFOOTPRINT 10
|
||||
#define SP_FSCTRLREG0_FSICACHEINVALID 2
|
||||
#define SP_FSCTRLREG0_FSINOUTREGOVERLAP 18
|
||||
#define SP_FSCTRLREG0_FSINSTRBUFFERMODE 1
|
||||
#define SP_FSCTRLREG0_FSLENGTH 24
|
||||
#define SP_FSCTRLREG0_FSSUPERTHREADMODE 21
|
||||
#define SP_FSCTRLREG0_FSTHREADMODE 0
|
||||
#define SP_FSCTRLREG0_FSTHREADSIZE 20
|
||||
#define SP_FSCTRLREG0_PIXLODENABLE 22
|
||||
#define SP_FSCTRLREG1_FSCONSTLENGTH 0
|
||||
#define SP_FSCTRLREG1_FSINITIALOUTSTANDING 20
|
||||
#define SP_FSCTRLREG1_HALFPRECVAROFFSET 24
|
||||
#define SP_FSMRTREG_REGID 0
|
||||
#define SP_FSOUTREG_PAD0 2
|
||||
#define SP_IMAGEOUTPUTREG_MRTFORMAT 0
|
||||
#define SP_IMAGEOUTPUTREG_PAD0 6
|
||||
#define SP_OBJOFFSETREG_CONSTOBJECTSTARTOFFSET 16
|
||||
#define SP_OBJOFFSETREG_SHADEROBJOFFSETINIC 25
|
||||
#define SP_SHADERLENGTH_LEN 0
|
||||
#define SP_SPCTRLREG_CONSTMODE 18
|
||||
#define SP_SPCTRLREG_SLEEPMODE 20
|
||||
#define SP_VSCTRLREG0_VSFULLREGFOOTPRINT 10
|
||||
#define SP_VSCTRLREG0_VSICACHEINVALID 2
|
||||
#define SP_VSCTRLREG0_VSINSTRBUFFERMODE 1
|
||||
#define SP_VSCTRLREG0_VSLENGTH 24
|
||||
#define SP_VSCTRLREG0_VSSUPERTHREADMODE 21
|
||||
#define SP_VSCTRLREG0_VSTHREADMODE 0
|
||||
#define SP_VSCTRLREG0_VSTHREADSIZE 20
|
||||
#define SP_VSCTRLREG1_VSINITIALOUTSTANDING 24
|
||||
#define SP_VSOUTREG_COMPMASK0 9
|
||||
#define SP_VSPARAMREG_POSREGID 0
|
||||
#define SP_VSPARAMREG_PSIZEREGID 8
|
||||
#define SP_VSPARAMREG_TOTALVSOUTVAR 20
|
||||
#define SP_VSVPCDSTREG_OUTLOC0 0
|
||||
#define TPL1_TPTEXOFFSETREG_BASETABLEPTR 16
|
||||
#define TPL1_TPTEXOFFSETREG_MEMOBJOFFSET 8
|
||||
#define TPL1_TPTEXOFFSETREG_SAMPLEROFFSET 0
|
||||
#define UCHE_INVALIDATE1REG_OPCODE 0x1C
|
||||
#define UCHE_INVALIDATE1REG_ALLORPORTION 0x1F
|
||||
#define VFD_BASEADDR_BASEADDR 0
|
||||
#define VFD_CTRLREG0_PACKETSIZE 18
|
||||
#define VFD_CTRLREG0_STRMDECINSTRCNT 22
|
||||
#define VFD_CTRLREG0_STRMFETCHINSTRCNT 27
|
||||
#define VFD_CTRLREG0_TOTALATTRTOVS 0
|
||||
#define VFD_CTRLREG1_MAXSTORAGE 0
|
||||
#define VFD_CTRLREG1_REGID4INST 24
|
||||
#define VFD_CTRLREG1_REGID4VTX 16
|
||||
#define VFD_DECODEINSTRUCTIONS_CONSTFILL 4
|
||||
#define VFD_DECODEINSTRUCTIONS_FORMAT 6
|
||||
#define VFD_DECODEINSTRUCTIONS_LASTCOMPVALID 29
|
||||
#define VFD_DECODEINSTRUCTIONS_REGID 12
|
||||
#define VFD_DECODEINSTRUCTIONS_SHIFTCNT 24
|
||||
#define VFD_DECODEINSTRUCTIONS_SWITCHNEXT 30
|
||||
#define VFD_DECODEINSTRUCTIONS_WRITEMASK 0
|
||||
#define VFD_FETCHINSTRUCTIONS_BUFSTRIDE 7
|
||||
#define VFD_FETCHINSTRUCTIONS_FETCHSIZE 0
|
||||
#define VFD_FETCHINSTRUCTIONS_INDEXDECODE 18
|
||||
#define VFD_FETCHINSTRUCTIONS_STEPRATE 24
|
||||
#define VFD_FETCHINSTRUCTIONS_SWITCHNEXT 17
|
||||
#define VFD_THREADINGTHRESHOLD_REGID_VTXCNT 8
|
||||
#define VFD_THREADINGTHRESHOLD_RESERVED6 4
|
||||
#define VPC_VPCATTR_LMSIZE 28
|
||||
#define VPC_VPCATTR_THRHDASSIGN 12
|
||||
#define VPC_VPCATTR_TOTALATTR 0
|
||||
#define VPC_VPCPACK_NUMFPNONPOSVAR 8
|
||||
#define VPC_VPCPACK_NUMNONPOSVSVAR 16
|
||||
#define VPC_VPCVARPSREPLMODE_COMPONENT08 0
|
||||
#define VPC_VPCVARPSREPLMODE_COMPONENT09 2
|
||||
#define VPC_VPCVARPSREPLMODE_COMPONENT0A 4
|
||||
#define VPC_VPCVARPSREPLMODE_COMPONENT0B 6
|
||||
#define VPC_VPCVARPSREPLMODE_COMPONENT0C 8
|
||||
#define VPC_VPCVARPSREPLMODE_COMPONENT0D 10
|
||||
#define VPC_VPCVARPSREPLMODE_COMPONENT0E 12
|
||||
#define VPC_VPCVARPSREPLMODE_COMPONENT0F 14
|
||||
#define VPC_VPCVARPSREPLMODE_COMPONENT10 16
|
||||
#define VPC_VPCVARPSREPLMODE_COMPONENT11 18
|
||||
#define VPC_VPCVARPSREPLMODE_COMPONENT12 20
|
||||
#define VPC_VPCVARPSREPLMODE_COMPONENT13 22
|
||||
#define VPC_VPCVARPSREPLMODE_COMPONENT14 24
|
||||
#define VPC_VPCVARPSREPLMODE_COMPONENT15 26
|
||||
#define VPC_VPCVARPSREPLMODE_COMPONENT16 28
|
||||
#define VPC_VPCVARPSREPLMODE_COMPONENT17 30
|
||||
|
||||
#endif
|
||||
@ -156,38 +156,16 @@ static const struct {
|
||||
{ ADRENO_REV_A225, 2, 2, 0, 5,
|
||||
"a225p5_pm4.fw", "a225_pfp.fw", &adreno_a2xx_gpudev,
|
||||
1536, 768 },
|
||||
{ ADRENO_REV_A225, 2, 2, 0, 6,
|
||||
"a225_pm4.fw", "a225_pfp.fw", &adreno_a2xx_gpudev,
|
||||
1536, 768 },
|
||||
{ ADRENO_REV_A225, 2, 2, ANY_ID, ANY_ID,
|
||||
"a225_pm4.fw", "a225_pfp.fw", &adreno_a2xx_gpudev,
|
||||
1536, 768 },
|
||||
{ ADRENO_REV_A320, 3, 1, ANY_ID, ANY_ID,
|
||||
"a300_pm4.fw", "a300_pfp.fw", &adreno_a3xx_gpudev },
|
||||
};
|
||||
|
||||
static void adreno_gmeminit(struct adreno_device *adreno_dev)
|
||||
{
|
||||
struct kgsl_device *device = &adreno_dev->dev;
|
||||
union reg_rb_edram_info rb_edram_info;
|
||||
unsigned int gmem_size;
|
||||
unsigned int edram_value = 0;
|
||||
|
||||
/* make sure edram range is aligned to size */
|
||||
BUG_ON(adreno_dev->gmemspace.gpu_base &
|
||||
(adreno_dev->gmemspace.sizebytes - 1));
|
||||
|
||||
/* get edram_size value equivalent */
|
||||
gmem_size = (adreno_dev->gmemspace.sizebytes >> 14);
|
||||
while (gmem_size >>= 1)
|
||||
edram_value++;
|
||||
|
||||
rb_edram_info.val = 0;
|
||||
|
||||
rb_edram_info.f.edram_size = edram_value;
|
||||
rb_edram_info.f.edram_mapping_mode = 0; /* EDRAM_MAP_UPPER */
|
||||
|
||||
/* must be aligned to size */
|
||||
rb_edram_info.f.edram_range = (adreno_dev->gmemspace.gpu_base >> 14);
|
||||
|
||||
adreno_regwrite(device, REG_RB_EDRAM_INFO, rb_edram_info.val);
|
||||
}
|
||||
|
||||
static irqreturn_t adreno_isr(int irq, void *data)
|
||||
{
|
||||
irqreturn_t result;
|
||||
@ -492,7 +470,6 @@ static int adreno_start(struct kgsl_device *device, unsigned int init_ram)
|
||||
{
|
||||
int status = -EINVAL;
|
||||
struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
|
||||
int init_reftimestamp = 0x7fffffff;
|
||||
|
||||
device->state = KGSL_STATE_INIT;
|
||||
device->requested_state = KGSL_STATE_NONE;
|
||||
@ -520,80 +497,22 @@ static int adreno_start(struct kgsl_device *device, unsigned int init_ram)
|
||||
|
||||
kgsl_mh_start(device);
|
||||
|
||||
if (kgsl_mmu_start(device))
|
||||
status = kgsl_mmu_start(device);
|
||||
if (status)
|
||||
goto error_clk_off;
|
||||
|
||||
/*We need to make sure all blocks are powered up and clocked before
|
||||
*issuing a soft reset. The overrides will then be turned off (set to 0)
|
||||
*/
|
||||
adreno_regwrite(device, REG_RBBM_PM_OVERRIDE1, 0xfffffffe);
|
||||
adreno_regwrite(device, REG_RBBM_PM_OVERRIDE2, 0xffffffff);
|
||||
|
||||
/* Only reset CP block if all blocks have previously been reset */
|
||||
if (!(device->flags & KGSL_FLAGS_SOFT_RESET) ||
|
||||
!adreno_is_a22x(adreno_dev)) {
|
||||
adreno_regwrite(device, REG_RBBM_SOFT_RESET, 0xFFFFFFFF);
|
||||
device->flags |= KGSL_FLAGS_SOFT_RESET;
|
||||
} else
|
||||
adreno_regwrite(device, REG_RBBM_SOFT_RESET, 0x00000001);
|
||||
|
||||
/* The core is in an indeterminate state until the reset completes
|
||||
* after 30ms.
|
||||
*/
|
||||
msleep(30);
|
||||
|
||||
adreno_regwrite(device, REG_RBBM_SOFT_RESET, 0x00000000);
|
||||
|
||||
adreno_regwrite(device, REG_RBBM_CNTL, 0x00004442);
|
||||
|
||||
if (adreno_is_a225(adreno_dev)) {
|
||||
/* Enable large instruction store for A225 */
|
||||
adreno_regwrite(device, REG_SQ_FLOW_CONTROL, 0x18000000);
|
||||
}
|
||||
|
||||
adreno_regwrite(device, REG_SQ_VS_PROGRAM, 0x00000000);
|
||||
adreno_regwrite(device, REG_SQ_PS_PROGRAM, 0x00000000);
|
||||
|
||||
if (cpu_is_msm8960() || cpu_is_msm8930())
|
||||
adreno_regwrite(device, REG_RBBM_PM_OVERRIDE1, 0x200);
|
||||
else
|
||||
adreno_regwrite(device, REG_RBBM_PM_OVERRIDE1, 0);
|
||||
|
||||
if (!adreno_is_a22x(adreno_dev))
|
||||
adreno_regwrite(device, REG_RBBM_PM_OVERRIDE2, 0);
|
||||
else
|
||||
adreno_regwrite(device, REG_RBBM_PM_OVERRIDE2, 0x80);
|
||||
|
||||
kgsl_sharedmem_set(&device->memstore, 0, 0, device->memstore.size);
|
||||
|
||||
kgsl_sharedmem_writel(&device->memstore,
|
||||
KGSL_DEVICE_MEMSTORE_OFFSET(ref_wait_ts),
|
||||
init_reftimestamp);
|
||||
|
||||
adreno_regwrite(device, REG_RBBM_DEBUG, 0x00080000);
|
||||
|
||||
/* Make sure interrupts are disabled */
|
||||
|
||||
adreno_regwrite(device, REG_RBBM_INT_CNTL, 0);
|
||||
adreno_regwrite(device, REG_CP_INT_CNTL, 0);
|
||||
adreno_regwrite(device, REG_SQ_INT_CNTL, 0);
|
||||
|
||||
if (adreno_is_a22x(adreno_dev))
|
||||
adreno_dev->gmemspace.sizebytes = SZ_512K;
|
||||
else
|
||||
adreno_dev->gmemspace.sizebytes = SZ_256K;
|
||||
adreno_gmeminit(adreno_dev);
|
||||
/* Start the GPU */
|
||||
adreno_dev->gpudev->start(adreno_dev);
|
||||
|
||||
kgsl_pwrctrl_irq(device, KGSL_PWRFLAGS_ON);
|
||||
device->ftbl->irqctrl(device, 1);
|
||||
|
||||
status = adreno_ringbuffer_start(&adreno_dev->ringbuffer, init_ram);
|
||||
if (status != 0)
|
||||
goto error_irq_off;
|
||||
|
||||
if (status == 0) {
|
||||
mod_timer(&device->idle_timer, jiffies + FIRST_TIMEOUT);
|
||||
return status;
|
||||
return 0;
|
||||
}
|
||||
|
||||
error_irq_off:
|
||||
kgsl_pwrctrl_irq(device, KGSL_PWRFLAGS_OFF);
|
||||
kgsl_mmu_stop(device);
|
||||
error_clk_off:
|
||||
@ -886,7 +805,8 @@ int adreno_idle(struct kgsl_device *device, unsigned int timeout)
|
||||
unsigned int msecs_first;
|
||||
unsigned int msecs_part;
|
||||
|
||||
kgsl_cffdump_regpoll(device->id, REG_RBBM_STATUS << 2,
|
||||
kgsl_cffdump_regpoll(device->id,
|
||||
adreno_dev->gpudev->reg_rbbm_status << 2,
|
||||
0x00000000, 0x80000000);
|
||||
/* first, wait until the CP has consumed all the commands in
|
||||
* the ring buffer
|
||||
@ -917,7 +837,8 @@ retry:
|
||||
/* now, wait for the GPU to finish its operations */
|
||||
wait_time = jiffies + wait_timeout;
|
||||
while (time_before(jiffies, wait_time)) {
|
||||
adreno_regread(device, REG_RBBM_STATUS, &rbbm_status);
|
||||
adreno_regread(device, adreno_dev->gpudev->reg_rbbm_status,
|
||||
&rbbm_status);
|
||||
if (rbbm_status == 0x110)
|
||||
return 0;
|
||||
}
|
||||
@ -1295,44 +1216,29 @@ static inline s64 adreno_ticks_to_us(u32 ticks, u32 gpu_freq)
|
||||
static void adreno_power_stats(struct kgsl_device *device,
|
||||
struct kgsl_power_stats *stats)
|
||||
{
|
||||
unsigned int reg;
|
||||
struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
|
||||
struct kgsl_pwrctrl *pwr = &device->pwrctrl;
|
||||
unsigned int cycles;
|
||||
|
||||
/* Get the busy cycles counted since the counter was last reset */
|
||||
/* Calling this function also resets and restarts the counter */
|
||||
|
||||
cycles = adreno_dev->gpudev->busy_cycles(adreno_dev);
|
||||
|
||||
/* In order to calculate idle you have to have run the algorithm *
|
||||
* at least once to get a start time. */
|
||||
if (pwr->time != 0) {
|
||||
s64 tmp;
|
||||
/* Stop the performance moniter and read the current *
|
||||
* busy cycles. */
|
||||
adreno_regwrite(device,
|
||||
REG_CP_PERFMON_CNTL,
|
||||
REG_PERF_MODE_CNT |
|
||||
REG_PERF_STATE_FREEZE);
|
||||
adreno_regread(device, REG_RBBM_PERFCOUNTER1_LO, ®);
|
||||
tmp = ktime_to_us(ktime_get());
|
||||
s64 tmp = ktime_to_us(ktime_get());
|
||||
stats->total_time = tmp - pwr->time;
|
||||
pwr->time = tmp;
|
||||
stats->busy_time = adreno_ticks_to_us(reg, device->pwrctrl.
|
||||
stats->busy_time = adreno_ticks_to_us(cycles, device->pwrctrl.
|
||||
pwrlevels[device->pwrctrl.active_pwrlevel].
|
||||
gpu_freq);
|
||||
|
||||
adreno_regwrite(device,
|
||||
REG_CP_PERFMON_CNTL,
|
||||
REG_PERF_MODE_CNT |
|
||||
REG_PERF_STATE_RESET);
|
||||
} else {
|
||||
stats->total_time = 0;
|
||||
stats->busy_time = 0;
|
||||
pwr->time = ktime_to_us(ktime_get());
|
||||
}
|
||||
|
||||
/* re-enable the performance moniters */
|
||||
adreno_regread(device, REG_RBBM_PM_OVERRIDE2, ®);
|
||||
adreno_regwrite(device, REG_RBBM_PM_OVERRIDE2, (reg | 0x40));
|
||||
adreno_regwrite(device, REG_RBBM_PERFCOUNTER1_SELECT, 0x1);
|
||||
adreno_regwrite(device,
|
||||
REG_CP_PERFMON_CNTL,
|
||||
REG_PERF_MODE_CNT | REG_PERF_STATE_ENABLE);
|
||||
}
|
||||
|
||||
void adreno_irqctrl(struct kgsl_device *device, int state)
|
||||
|
||||
@ -51,6 +51,7 @@ enum adreno_gpurev {
|
||||
ADRENO_REV_A205 = 205,
|
||||
ADRENO_REV_A220 = 220,
|
||||
ADRENO_REV_A225 = 225,
|
||||
ADRENO_REV_A320 = 320,
|
||||
};
|
||||
|
||||
struct adreno_gpudev;
|
||||
@ -76,14 +77,27 @@ struct adreno_device {
|
||||
};
|
||||
|
||||
struct adreno_gpudev {
|
||||
/*
|
||||
* These registers are in a different location on A3XX, so define
|
||||
* them in the structure and use them as variables.
|
||||
*/
|
||||
unsigned int reg_rbbm_status;
|
||||
unsigned int reg_cp_pfp_ucode_data;
|
||||
unsigned int reg_cp_pfp_ucode_addr;
|
||||
|
||||
/* GPU specific function hooks */
|
||||
int (*ctxt_create)(struct adreno_device *, struct adreno_context *);
|
||||
void (*ctxt_save)(struct adreno_device *, struct adreno_context *);
|
||||
void (*ctxt_restore)(struct adreno_device *, struct adreno_context *);
|
||||
irqreturn_t (*irq_handler)(struct adreno_device *);
|
||||
void (*irq_control)(struct adreno_device *, int);
|
||||
void (*rb_init)(struct adreno_device *, struct adreno_ringbuffer *);
|
||||
void (*start)(struct adreno_device *);
|
||||
unsigned int (*busy_cycles)(struct adreno_device *);
|
||||
};
|
||||
|
||||
extern struct adreno_gpudev adreno_a2xx_gpudev;
|
||||
extern struct adreno_gpudev adreno_a3xx_gpudev;
|
||||
|
||||
int adreno_idle(struct kgsl_device *device, unsigned int timeout);
|
||||
void adreno_regread(struct kgsl_device *device, unsigned int offsetwords,
|
||||
@ -133,7 +147,12 @@ static inline int adreno_is_a22x(struct adreno_device *adreno_dev)
|
||||
|
||||
static inline int adreno_is_a2xx(struct adreno_device *adreno_dev)
|
||||
{
|
||||
return (adreno_dev->gpurev <= ADRENO_REV_A225);
|
||||
return (adreno_dev->gpurev <= 299);
|
||||
}
|
||||
|
||||
static inline int adreno_is_a3xx(struct adreno_device *adreno_dev)
|
||||
{
|
||||
return (adreno_dev->gpurev >= 300);
|
||||
}
|
||||
|
||||
/**
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* Copyright (c) 2002,2007-2011, Code Aurora Forum. All rights reserved.
|
||||
/* Copyright (c) 2002,2007-2012, Code Aurora Forum. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
@ -11,6 +11,8 @@
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/delay.h>
|
||||
|
||||
#include "kgsl.h"
|
||||
#include "kgsl_sharedmem.h"
|
||||
#include "kgsl_cffdump.h"
|
||||
@ -1665,10 +1667,207 @@ static void a2xx_irq_control(struct adreno_device *adreno_dev, int state)
|
||||
wmb();
|
||||
}
|
||||
|
||||
static void a2xx_rb_init(struct adreno_device *adreno_dev,
|
||||
struct adreno_ringbuffer *rb)
|
||||
{
|
||||
unsigned int *cmds, cmds_gpu;
|
||||
|
||||
/* ME_INIT */
|
||||
cmds = adreno_ringbuffer_allocspace(rb, 19);
|
||||
cmds_gpu = rb->buffer_desc.gpuaddr + sizeof(uint)*(rb->wptr-19);
|
||||
|
||||
GSL_RB_WRITE(cmds, cmds_gpu, cp_type3_packet(CP_ME_INIT, 18));
|
||||
/* All fields present (bits 9:0) */
|
||||
GSL_RB_WRITE(cmds, cmds_gpu, 0x000003ff);
|
||||
/* Disable/Enable Real-Time Stream processing (present but ignored) */
|
||||
GSL_RB_WRITE(cmds, cmds_gpu, 0x00000000);
|
||||
/* Enable (2D <-> 3D) implicit synchronization (present but ignored) */
|
||||
GSL_RB_WRITE(cmds, cmds_gpu, 0x00000000);
|
||||
|
||||
GSL_RB_WRITE(cmds, cmds_gpu,
|
||||
SUBBLOCK_OFFSET(REG_RB_SURFACE_INFO));
|
||||
GSL_RB_WRITE(cmds, cmds_gpu,
|
||||
SUBBLOCK_OFFSET(REG_PA_SC_WINDOW_OFFSET));
|
||||
GSL_RB_WRITE(cmds, cmds_gpu,
|
||||
SUBBLOCK_OFFSET(REG_VGT_MAX_VTX_INDX));
|
||||
GSL_RB_WRITE(cmds, cmds_gpu,
|
||||
SUBBLOCK_OFFSET(REG_SQ_PROGRAM_CNTL));
|
||||
GSL_RB_WRITE(cmds, cmds_gpu,
|
||||
SUBBLOCK_OFFSET(REG_RB_DEPTHCONTROL));
|
||||
GSL_RB_WRITE(cmds, cmds_gpu,
|
||||
SUBBLOCK_OFFSET(REG_PA_SU_POINT_SIZE));
|
||||
GSL_RB_WRITE(cmds, cmds_gpu,
|
||||
SUBBLOCK_OFFSET(REG_PA_SC_LINE_CNTL));
|
||||
GSL_RB_WRITE(cmds, cmds_gpu,
|
||||
SUBBLOCK_OFFSET(REG_PA_SU_POLY_OFFSET_FRONT_SCALE));
|
||||
|
||||
/* Instruction memory size: */
|
||||
GSL_RB_WRITE(cmds, cmds_gpu,
|
||||
(adreno_encode_istore_size(adreno_dev)
|
||||
| adreno_dev->pix_shader_start));
|
||||
/* Maximum Contexts */
|
||||
GSL_RB_WRITE(cmds, cmds_gpu, 0x00000001);
|
||||
/* Write Confirm Interval and The CP will wait the
|
||||
* wait_interval * 16 clocks between polling */
|
||||
GSL_RB_WRITE(cmds, cmds_gpu, 0x00000000);
|
||||
|
||||
/* NQ and External Memory Swap */
|
||||
GSL_RB_WRITE(cmds, cmds_gpu, 0x00000000);
|
||||
/* Protected mode error checking */
|
||||
GSL_RB_WRITE(cmds, cmds_gpu, GSL_RB_PROTECTED_MODE_CONTROL);
|
||||
/* Disable header dumping and Header dump address */
|
||||
GSL_RB_WRITE(cmds, cmds_gpu, 0x00000000);
|
||||
/* Header dump size */
|
||||
GSL_RB_WRITE(cmds, cmds_gpu, 0x00000000);
|
||||
|
||||
adreno_ringbuffer_submit(rb);
|
||||
}
|
||||
|
||||
static unsigned int a2xx_busy_cycles(struct adreno_device *adreno_dev)
|
||||
{
|
||||
struct kgsl_device *device = &adreno_dev->dev;
|
||||
unsigned int reg, val;
|
||||
|
||||
/* Freeze the counter */
|
||||
adreno_regwrite(device, REG_CP_PERFMON_CNTL,
|
||||
REG_PERF_MODE_CNT | REG_PERF_STATE_FREEZE);
|
||||
|
||||
/* Get the value */
|
||||
adreno_regread(device, REG_RBBM_PERFCOUNTER1_LO, &val);
|
||||
|
||||
/* Reset the counter */
|
||||
adreno_regwrite(device, REG_CP_PERFMON_CNTL,
|
||||
REG_PERF_MODE_CNT | REG_PERF_STATE_RESET);
|
||||
|
||||
/* Re-Enable the performance monitors */
|
||||
adreno_regread(device, REG_RBBM_PM_OVERRIDE2, ®);
|
||||
adreno_regwrite(device, REG_RBBM_PM_OVERRIDE2, (reg | 0x40));
|
||||
adreno_regwrite(device, REG_RBBM_PERFCOUNTER1_SELECT, 0x1);
|
||||
adreno_regwrite(device, REG_CP_PERFMON_CNTL,
|
||||
REG_PERF_MODE_CNT | REG_PERF_STATE_ENABLE);
|
||||
|
||||
return val;
|
||||
}
|
||||
|
||||
static void a2xx_gmeminit(struct adreno_device *adreno_dev)
|
||||
{
|
||||
struct kgsl_device *device = &adreno_dev->dev;
|
||||
union reg_rb_edram_info rb_edram_info;
|
||||
unsigned int gmem_size;
|
||||
unsigned int edram_value = 0;
|
||||
|
||||
/* make sure edram range is aligned to size */
|
||||
BUG_ON(adreno_dev->gmemspace.gpu_base &
|
||||
(adreno_dev->gmemspace.sizebytes - 1));
|
||||
|
||||
/* get edram_size value equivalent */
|
||||
gmem_size = (adreno_dev->gmemspace.sizebytes >> 14);
|
||||
while (gmem_size >>= 1)
|
||||
edram_value++;
|
||||
|
||||
rb_edram_info.val = 0;
|
||||
|
||||
rb_edram_info.f.edram_size = edram_value;
|
||||
rb_edram_info.f.edram_mapping_mode = 0; /* EDRAM_MAP_UPPER */
|
||||
|
||||
/* must be aligned to size */
|
||||
rb_edram_info.f.edram_range = (adreno_dev->gmemspace.gpu_base >> 14);
|
||||
|
||||
adreno_regwrite(device, REG_RB_EDRAM_INFO, rb_edram_info.val);
|
||||
}
|
||||
|
||||
static void a2xx_start(struct adreno_device *adreno_dev)
|
||||
{
|
||||
struct kgsl_device *device = &adreno_dev->dev;
|
||||
int init_reftimestamp = 0x7fffffff;
|
||||
|
||||
/*
|
||||
* We need to make sure all blocks are powered up and clocked
|
||||
* before issuing a soft reset. The overrides will then be
|
||||
* turned off (set to 0)
|
||||
*/
|
||||
adreno_regwrite(device, REG_RBBM_PM_OVERRIDE1, 0xfffffffe);
|
||||
adreno_regwrite(device, REG_RBBM_PM_OVERRIDE2, 0xffffffff);
|
||||
|
||||
/*
|
||||
* Only reset CP block if all blocks have previously been
|
||||
* reset
|
||||
*/
|
||||
if (!(device->flags & KGSL_FLAGS_SOFT_RESET) ||
|
||||
!adreno_is_a22x(adreno_dev)) {
|
||||
adreno_regwrite(device, REG_RBBM_SOFT_RESET,
|
||||
0xFFFFFFFF);
|
||||
device->flags |= KGSL_FLAGS_SOFT_RESET;
|
||||
} else {
|
||||
adreno_regwrite(device, REG_RBBM_SOFT_RESET,
|
||||
0x00000001);
|
||||
}
|
||||
/*
|
||||
* The core is in an indeterminate state until the reset
|
||||
* completes after 30ms.
|
||||
*/
|
||||
msleep(30);
|
||||
|
||||
adreno_regwrite(device, REG_RBBM_SOFT_RESET, 0x00000000);
|
||||
|
||||
if (adreno_is_a225(adreno_dev)) {
|
||||
/* Enable large instruction store for A225 */
|
||||
adreno_regwrite(device, REG_SQ_FLOW_CONTROL,
|
||||
0x18000000);
|
||||
}
|
||||
|
||||
adreno_regwrite(device, REG_RBBM_CNTL, 0x00004442);
|
||||
|
||||
adreno_regwrite(device, REG_SQ_VS_PROGRAM, 0x00000000);
|
||||
adreno_regwrite(device, REG_SQ_PS_PROGRAM, 0x00000000);
|
||||
|
||||
// if (cpu_is_msm8960() || cpu_is_msm8930())
|
||||
if(0)
|
||||
adreno_regwrite(device, REG_RBBM_PM_OVERRIDE1, 0x200);
|
||||
else
|
||||
adreno_regwrite(device, REG_RBBM_PM_OVERRIDE1, 0);
|
||||
|
||||
if (!adreno_is_a22x(adreno_dev))
|
||||
adreno_regwrite(device, REG_RBBM_PM_OVERRIDE2, 0);
|
||||
else
|
||||
adreno_regwrite(device, REG_RBBM_PM_OVERRIDE2, 0x80);
|
||||
|
||||
kgsl_sharedmem_set(&device->memstore, 0, 0, device->memstore.size);
|
||||
|
||||
kgsl_sharedmem_writel(&device->memstore,
|
||||
KGSL_DEVICE_MEMSTORE_OFFSET(ref_wait_ts),
|
||||
init_reftimestamp);
|
||||
|
||||
adreno_regwrite(device, REG_RBBM_DEBUG, 0x00080000);
|
||||
|
||||
/* Make sure interrupts are disabled */
|
||||
adreno_regwrite(device, REG_RBBM_INT_CNTL, 0);
|
||||
adreno_regwrite(device, REG_CP_INT_CNTL, 0);
|
||||
adreno_regwrite(device, REG_SQ_INT_CNTL, 0);
|
||||
|
||||
if (adreno_is_a22x(adreno_dev))
|
||||
adreno_dev->gmemspace.sizebytes = SZ_512K;
|
||||
else
|
||||
adreno_dev->gmemspace.sizebytes = SZ_256K;
|
||||
|
||||
a2xx_gmeminit(adreno_dev);
|
||||
}
|
||||
|
||||
/* Defined in adreno_a2xx_snapshot.c */
|
||||
void *a2xx_snapshot(struct adreno_device *adreno_dev, void *snapshot,
|
||||
int *remain, int hang);
|
||||
|
||||
struct adreno_gpudev adreno_a2xx_gpudev = {
|
||||
.reg_rbbm_status = REG_RBBM_STATUS,
|
||||
.reg_cp_pfp_ucode_addr = REG_CP_PFP_UCODE_ADDR,
|
||||
.reg_cp_pfp_ucode_data = REG_CP_PFP_UCODE_DATA,
|
||||
|
||||
.ctxt_create = a2xx_drawctxt_create,
|
||||
.ctxt_save = a2xx_drawctxt_save,
|
||||
.ctxt_restore = a2xx_drawctxt_restore,
|
||||
.irq_handler = a2xx_irq_handler,
|
||||
.irq_control = a2xx_irq_control,
|
||||
.rb_init = a2xx_rb_init,
|
||||
.busy_cycles = a2xx_busy_cycles,
|
||||
.start = a2xx_start,
|
||||
};
|
||||
|
||||
2547
drivers/gpu/msm/adreno_a3xx.c
Executable file
2547
drivers/gpu/msm/adreno_a3xx.c
Executable file
File diff suppressed because it is too large
Load Diff
@ -19,6 +19,7 @@
|
||||
|
||||
/* quad for copying GMEM to context shadow */
|
||||
#define QUAD_LEN 12
|
||||
#define QUAD_RESTORE_LEN 14
|
||||
|
||||
static unsigned int gmem_copy_quad[QUAD_LEN] = {
|
||||
0x00000000, 0x00000000, 0x3f800000,
|
||||
@ -27,6 +28,14 @@ static unsigned int gmem_copy_quad[QUAD_LEN] = {
|
||||
0x00000000, 0x00000000, 0x3f800000
|
||||
};
|
||||
|
||||
static unsigned int gmem_restore_quad[QUAD_RESTORE_LEN] = {
|
||||
0x00000000, 0x3f800000, 0x3f800000,
|
||||
0x00000000, 0x00000000, 0x00000000,
|
||||
0x3f800000, 0x00000000, 0x00000000,
|
||||
0x3f800000, 0x00000000, 0x00000000,
|
||||
0x3f800000, 0x3f800000,
|
||||
};
|
||||
|
||||
#define TEXCOORD_LEN 8
|
||||
|
||||
static unsigned int gmem_copy_texcoord[TEXCOORD_LEN] = {
|
||||
@ -73,12 +82,12 @@ static void set_gmem_copy_quad(struct gmem_shadow_t *shadow)
|
||||
gmem_copy_quad[4] = uint2float(shadow->height);
|
||||
gmem_copy_quad[9] = uint2float(shadow->width);
|
||||
|
||||
gmem_copy_quad[0] = 0;
|
||||
gmem_copy_quad[6] = 0;
|
||||
gmem_copy_quad[7] = 0;
|
||||
gmem_copy_quad[10] = 0;
|
||||
gmem_restore_quad[5] = uint2float(shadow->height);
|
||||
gmem_restore_quad[7] = uint2float(shadow->width);
|
||||
|
||||
memcpy(shadow->quad_vertices.hostptr, gmem_copy_quad, QUAD_LEN << 2);
|
||||
memcpy(shadow->quad_vertices_restore.hostptr, gmem_copy_quad,
|
||||
QUAD_RESTORE_LEN << 2);
|
||||
|
||||
memcpy(shadow->quad_texcoords.hostptr, gmem_copy_texcoord,
|
||||
TEXCOORD_LEN << 2);
|
||||
@ -103,6 +112,13 @@ void build_quad_vtxbuff(struct adreno_context *drawctxt,
|
||||
|
||||
cmd += QUAD_LEN;
|
||||
|
||||
/* Used by A3XX, but define for both to make the code easier */
|
||||
shadow->quad_vertices_restore.hostptr = cmd;
|
||||
shadow->quad_vertices_restore.gpuaddr =
|
||||
virt2gpu(cmd, &drawctxt->gpustate);
|
||||
|
||||
cmd += QUAD_RESTORE_LEN;
|
||||
|
||||
/* tex coord buffer location (in GPU space) */
|
||||
shadow->quad_texcoords.hostptr = cmd;
|
||||
shadow->quad_texcoords.gpuaddr = virt2gpu(cmd, &drawctxt->gpustate);
|
||||
|
||||
@ -50,37 +50,56 @@ struct kgsl_context;
|
||||
struct gmem_shadow_t {
|
||||
struct kgsl_memdesc gmemshadow; /* Shadow buffer address */
|
||||
|
||||
/* 256 KB GMEM surface = 4 bytes-per-pixel x 256 pixels/row x
|
||||
* 256 rows. */
|
||||
/* width & height must be a multiples of 32, in case tiled textures
|
||||
* are used. */
|
||||
enum COLORFORMATX format;
|
||||
/*
|
||||
* 256 KB GMEM surface = 4 bytes-per-pixel x 256 pixels/row x
|
||||
* 256 rows. Width & height must be multiples of 32 in case tiled
|
||||
* textures are used
|
||||
*/
|
||||
|
||||
enum COLORFORMATX format; /* Unused on A3XX */
|
||||
unsigned int size; /* Size of surface used to store GMEM */
|
||||
unsigned int width; /* Width of surface used to store GMEM */
|
||||
unsigned int height; /* Height of surface used to store GMEM */
|
||||
unsigned int pitch; /* Pitch of surface used to store GMEM */
|
||||
unsigned int gmem_pitch; /* Pitch value used for GMEM */
|
||||
unsigned int *gmem_save_commands;
|
||||
unsigned int *gmem_restore_commands;
|
||||
unsigned int *gmem_save_commands; /* Unused on A3XX */
|
||||
unsigned int *gmem_restore_commands; /* Unused on A3XX */
|
||||
unsigned int gmem_save[3];
|
||||
unsigned int gmem_restore[3];
|
||||
struct kgsl_memdesc quad_vertices;
|
||||
struct kgsl_memdesc quad_texcoords;
|
||||
struct kgsl_memdesc quad_vertices_restore;
|
||||
};
|
||||
|
||||
struct adreno_context {
|
||||
uint32_t flags;
|
||||
struct kgsl_pagetable *pagetable;
|
||||
struct kgsl_memdesc gpustate;
|
||||
unsigned int reg_save[3];
|
||||
unsigned int reg_restore[3];
|
||||
unsigned int shader_save[3];
|
||||
unsigned int shader_fixup[3];
|
||||
unsigned int shader_restore[3];
|
||||
unsigned int chicken_restore[3];
|
||||
unsigned int bin_base_offset;
|
||||
|
||||
/* Information of the GMEM shadow that is created in context create */
|
||||
struct gmem_shadow_t context_gmem_shadow;
|
||||
|
||||
/* A2XX specific items */
|
||||
unsigned int reg_save[3];
|
||||
unsigned int shader_fixup[3];
|
||||
unsigned int chicken_restore[3];
|
||||
unsigned int bin_base_offset;
|
||||
|
||||
/* A3XX specific items */
|
||||
unsigned int regconstant_save[3];
|
||||
unsigned int constant_restore[3];
|
||||
unsigned int hlsqcontrol_restore[3];
|
||||
unsigned int save_fixup[3];
|
||||
unsigned int restore_fixup[3];
|
||||
struct kgsl_memdesc shader_load_commands[2];
|
||||
struct kgsl_memdesc shader_save_commands[4];
|
||||
struct kgsl_memdesc constant_save_commands[3];
|
||||
struct kgsl_memdesc constant_load_commands[3];
|
||||
struct kgsl_memdesc cond_execs[4];
|
||||
struct kgsl_memdesc hlsqcontrol_restore_commands[1];
|
||||
};
|
||||
|
||||
int adreno_drawctxt_create(struct kgsl_device *device,
|
||||
|
||||
14
drivers/gpu/msm/adreno_pm4types.h
Normal file → Executable file
14
drivers/gpu/msm/adreno_pm4types.h
Normal file → Executable file
@ -1,4 +1,4 @@
|
||||
/* Copyright (c) 2002,2007-2011, Code Aurora Forum. All rights reserved.
|
||||
/* Copyright (c) 2002,2007-2012, Code Aurora Forum. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
@ -157,6 +157,18 @@
|
||||
|
||||
#define CP_SET_PROTECTED_MODE 0x5f /* sets the register protection mode */
|
||||
|
||||
/*
|
||||
* for a3xx
|
||||
*/
|
||||
|
||||
#define CP_LOAD_STATE 0x30 /* load high level sequencer command */
|
||||
|
||||
#define CP_LOADSTATE_DSTOFFSET_SHIFT 0x00000000
|
||||
#define CP_LOADSTATE_STATESRC_SHIFT 0x00000010
|
||||
#define CP_LOADSTATE_STATEBLOCKID_SHIFT 0x00000013
|
||||
#define CP_LOADSTATE_NUMOFUNITS_SHIFT 0x00000016
|
||||
#define CP_LOADSTATE_STATETYPE_SHIFT 0x00000000
|
||||
#define CP_LOADSTATE_EXTSRCADDR_SHIFT 0x00000002
|
||||
|
||||
/* packet header building macros */
|
||||
#define cp_type0_packet(regindx, cnt) \
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* Copyright (c) 2002,2007-2011, Code Aurora Forum. All rights reserved.
|
||||
/* Copyright (c) 2002,2007-2012, Code Aurora Forum. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
@ -24,28 +24,11 @@
|
||||
#include "adreno_ringbuffer.h"
|
||||
|
||||
#include "a2xx_reg.h"
|
||||
#include "a3xx_reg.h"
|
||||
|
||||
#define GSL_RB_NOP_SIZEDWORDS 2
|
||||
/* protected mode error checking below register address 0x800
|
||||
* note: if CP_INTERRUPT packet is used then checking needs
|
||||
* to change to below register address 0x7C8
|
||||
*/
|
||||
#define GSL_RB_PROTECTED_MODE_CONTROL 0x200001F2
|
||||
|
||||
/* Firmware file names
|
||||
* Legacy names must remain but replacing macro names to
|
||||
* match current kgsl model.
|
||||
* a200 is yamato
|
||||
* a220 is leia
|
||||
*/
|
||||
#define A200_PFP_FW "yamato_pfp.fw"
|
||||
#define A200_PM4_FW "yamato_pm4.fw"
|
||||
#define A220_PFP_470_FW "leia_pfp_470.fw"
|
||||
#define A220_PM4_470_FW "leia_pm4_470.fw"
|
||||
#define A225_PFP_FW "a225_pfp.fw"
|
||||
#define A225_PM4_FW "a225_pm4.fw"
|
||||
|
||||
static void adreno_ringbuffer_submit(struct adreno_ringbuffer *rb)
|
||||
void adreno_ringbuffer_submit(struct adreno_ringbuffer *rb)
|
||||
{
|
||||
BUG_ON(rb->wptr == 0);
|
||||
|
||||
@ -104,8 +87,7 @@ adreno_ringbuffer_waitspace(struct adreno_ringbuffer *rb, unsigned int numcmds,
|
||||
} while ((freecmds != 0) && (freecmds <= numcmds));
|
||||
}
|
||||
|
||||
|
||||
static unsigned int *adreno_ringbuffer_allocspace(struct adreno_ringbuffer *rb,
|
||||
unsigned int *adreno_ringbuffer_allocspace(struct adreno_ringbuffer *rb,
|
||||
unsigned int numcmds)
|
||||
{
|
||||
unsigned int *ptr = NULL;
|
||||
@ -231,9 +213,10 @@ static int adreno_ringbuffer_load_pfp_ucode(struct kgsl_device *device)
|
||||
KGSL_DRV_INFO(device, "loading pfp ucode version: %d\n",
|
||||
adreno_dev->pfp_fw[0]);
|
||||
|
||||
adreno_regwrite(device, REG_CP_PFP_UCODE_ADDR, 0);
|
||||
adreno_regwrite(device, adreno_dev->gpudev->reg_cp_pfp_ucode_addr, 0);
|
||||
for (i = 1; i < adreno_dev->pfp_fw_size; i++)
|
||||
adreno_regwrite(device, REG_CP_PFP_UCODE_DATA,
|
||||
adreno_regwrite(device,
|
||||
adreno_dev->gpudev->reg_cp_pfp_ucode_data,
|
||||
adreno_dev->pfp_fw[i]);
|
||||
err:
|
||||
return ret;
|
||||
@ -244,10 +227,9 @@ int adreno_ringbuffer_start(struct adreno_ringbuffer *rb, unsigned int init_ram)
|
||||
int status;
|
||||
/*cp_rb_cntl_u cp_rb_cntl; */
|
||||
union reg_cp_rb_cntl cp_rb_cntl;
|
||||
unsigned int *cmds, rb_cntl;
|
||||
unsigned int rb_cntl;
|
||||
struct kgsl_device *device = rb->device;
|
||||
struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
|
||||
uint cmds_gpu;
|
||||
|
||||
if (rb->flags & KGSL_FLAGS_STARTED)
|
||||
return 0;
|
||||
@ -263,12 +245,15 @@ int adreno_ringbuffer_start(struct adreno_ringbuffer *rb, unsigned int init_ram)
|
||||
kgsl_sharedmem_set(&rb->buffer_desc, 0, 0xAA,
|
||||
(rb->sizedwords << 2));
|
||||
|
||||
if (adreno_is_a2xx(adreno_dev)) {
|
||||
adreno_regwrite(device, REG_CP_RB_WPTR_BASE,
|
||||
(rb->memptrs_desc.gpuaddr
|
||||
+ GSL_RB_MEMPTRS_WPTRPOLL_OFFSET));
|
||||
|
||||
/* setup WPTR delay */
|
||||
adreno_regwrite(device, REG_CP_RB_WPTR_DELAY, 0 /*0x70000010 */);
|
||||
adreno_regwrite(device, REG_CP_RB_WPTR_DELAY,
|
||||
0 /*0x70000010 */);
|
||||
}
|
||||
|
||||
/*setup REG_CP_RB_CNTL */
|
||||
adreno_regread(device, REG_CP_RB_CNTL, &rb_cntl);
|
||||
@ -287,7 +272,11 @@ int adreno_ringbuffer_start(struct adreno_ringbuffer *rb, unsigned int init_ram)
|
||||
*/
|
||||
cp_rb_cntl.f.rb_blksz = ilog2(KGSL_RB_BLKSIZE >> 3);
|
||||
|
||||
cp_rb_cntl.f.rb_poll_en = GSL_RB_CNTL_POLL_EN; /* WPTR polling */
|
||||
if (adreno_is_a2xx(adreno_dev)) {
|
||||
/* WPTR polling */
|
||||
cp_rb_cntl.f.rb_poll_en = GSL_RB_CNTL_POLL_EN;
|
||||
}
|
||||
|
||||
/* mem RPTR writebacks */
|
||||
cp_rb_cntl.f.rb_no_update = GSL_RB_CNTL_NO_UPDATE;
|
||||
|
||||
@ -299,8 +288,36 @@ int adreno_ringbuffer_start(struct adreno_ringbuffer *rb, unsigned int init_ram)
|
||||
rb->memptrs_desc.gpuaddr +
|
||||
GSL_RB_MEMPTRS_RPTR_OFFSET);
|
||||
|
||||
if (adreno_is_a3xx(adreno_dev)) {
|
||||
/* enable access protection to privileged registers */
|
||||
adreno_regwrite(device, A3XX_CP_PROTECT_CTRL, 0x00000007);
|
||||
|
||||
/* RBBM registers */
|
||||
adreno_regwrite(device, A3XX_CP_PROTECT_REG_0, 0x63000040);
|
||||
adreno_regwrite(device, A3XX_CP_PROTECT_REG_1, 0x62000080);
|
||||
adreno_regwrite(device, A3XX_CP_PROTECT_REG_2, 0x600000CC);
|
||||
adreno_regwrite(device, A3XX_CP_PROTECT_REG_3, 0x60000108);
|
||||
adreno_regwrite(device, A3XX_CP_PROTECT_REG_4, 0x64000140);
|
||||
adreno_regwrite(device, A3XX_CP_PROTECT_REG_5, 0x66000400);
|
||||
|
||||
/* CP registers */
|
||||
adreno_regwrite(device, A3XX_CP_PROTECT_REG_6, 0x65000700);
|
||||
adreno_regwrite(device, A3XX_CP_PROTECT_REG_7, 0x610007D8);
|
||||
adreno_regwrite(device, A3XX_CP_PROTECT_REG_8, 0x620007E0);
|
||||
adreno_regwrite(device, A3XX_CP_PROTECT_REG_9, 0x61001178);
|
||||
adreno_regwrite(device, A3XX_CP_PROTECT_REG_A, 0x64001180);
|
||||
|
||||
/* RB registers */
|
||||
adreno_regwrite(device, A3XX_CP_PROTECT_REG_B, 0x60003300);
|
||||
|
||||
/* VBIF registers */
|
||||
adreno_regwrite(device, A3XX_CP_PROTECT_REG_C, 0x6B00C000);
|
||||
}
|
||||
|
||||
if (adreno_is_a2xx(adreno_dev)) {
|
||||
/* explicitly clear all cp interrupts */
|
||||
adreno_regwrite(device, REG_CP_INT_ACK, 0xFFFFFFFF);
|
||||
}
|
||||
|
||||
/* setup scratch/timestamp */
|
||||
adreno_regwrite(device, REG_SCRATCH_ADDR,
|
||||
@ -334,55 +351,8 @@ int adreno_ringbuffer_start(struct adreno_ringbuffer *rb, unsigned int init_ram)
|
||||
/* clear ME_HALT to start micro engine */
|
||||
adreno_regwrite(device, REG_CP_ME_CNTL, 0);
|
||||
|
||||
/* ME_INIT */
|
||||
cmds = adreno_ringbuffer_allocspace(rb, 19);
|
||||
cmds_gpu = rb->buffer_desc.gpuaddr + sizeof(uint)*(rb->wptr-19);
|
||||
|
||||
GSL_RB_WRITE(cmds, cmds_gpu, CP_HDR_ME_INIT);
|
||||
/* All fields present (bits 9:0) */
|
||||
GSL_RB_WRITE(cmds, cmds_gpu, 0x000003ff);
|
||||
/* Disable/Enable Real-Time Stream processing (present but ignored) */
|
||||
GSL_RB_WRITE(cmds, cmds_gpu, 0x00000000);
|
||||
/* Enable (2D <-> 3D) implicit synchronization (present but ignored) */
|
||||
GSL_RB_WRITE(cmds, cmds_gpu, 0x00000000);
|
||||
|
||||
GSL_RB_WRITE(cmds, cmds_gpu,
|
||||
SUBBLOCK_OFFSET(REG_RB_SURFACE_INFO));
|
||||
GSL_RB_WRITE(cmds, cmds_gpu,
|
||||
SUBBLOCK_OFFSET(REG_PA_SC_WINDOW_OFFSET));
|
||||
GSL_RB_WRITE(cmds, cmds_gpu,
|
||||
SUBBLOCK_OFFSET(REG_VGT_MAX_VTX_INDX));
|
||||
GSL_RB_WRITE(cmds, cmds_gpu,
|
||||
SUBBLOCK_OFFSET(REG_SQ_PROGRAM_CNTL));
|
||||
GSL_RB_WRITE(cmds, cmds_gpu,
|
||||
SUBBLOCK_OFFSET(REG_RB_DEPTHCONTROL));
|
||||
GSL_RB_WRITE(cmds, cmds_gpu,
|
||||
SUBBLOCK_OFFSET(REG_PA_SU_POINT_SIZE));
|
||||
GSL_RB_WRITE(cmds, cmds_gpu,
|
||||
SUBBLOCK_OFFSET(REG_PA_SC_LINE_CNTL));
|
||||
GSL_RB_WRITE(cmds, cmds_gpu,
|
||||
SUBBLOCK_OFFSET(REG_PA_SU_POLY_OFFSET_FRONT_SCALE));
|
||||
|
||||
/* Instruction memory size: */
|
||||
GSL_RB_WRITE(cmds, cmds_gpu,
|
||||
(adreno_encode_istore_size(adreno_dev)
|
||||
| adreno_dev->pix_shader_start));
|
||||
/* Maximum Contexts */
|
||||
GSL_RB_WRITE(cmds, cmds_gpu, 0x00000001);
|
||||
/* Write Confirm Interval and The CP will wait the
|
||||
* wait_interval * 16 clocks between polling */
|
||||
GSL_RB_WRITE(cmds, cmds_gpu, 0x00000000);
|
||||
|
||||
/* NQ and External Memory Swap */
|
||||
GSL_RB_WRITE(cmds, cmds_gpu, 0x00000000);
|
||||
/* Protected mode error checking */
|
||||
GSL_RB_WRITE(cmds, cmds_gpu, GSL_RB_PROTECTED_MODE_CONTROL);
|
||||
/* Disable header dumping and Header dump address */
|
||||
GSL_RB_WRITE(cmds, cmds_gpu, 0x00000000);
|
||||
/* Header dump size */
|
||||
GSL_RB_WRITE(cmds, cmds_gpu, 0x00000000);
|
||||
|
||||
adreno_ringbuffer_submit(rb);
|
||||
/* ME init is GPU specific, so jump into the sub-function */
|
||||
adreno_dev->gpudev->rb_init(adreno_dev, rb);
|
||||
|
||||
/* idle device to validate ME INIT */
|
||||
status = adreno_idle(device, KGSL_TIMEOUT_DEFAULT);
|
||||
@ -463,6 +433,7 @@ adreno_ringbuffer_addcmds(struct adreno_ringbuffer *rb,
|
||||
unsigned int flags, unsigned int *cmds,
|
||||
int sizedwords)
|
||||
{
|
||||
struct adreno_device *adreno_dev = ADRENO_DEVICE(rb->device);
|
||||
unsigned int *ringcmds;
|
||||
unsigned int timestamp;
|
||||
unsigned int total_sizedwords = sizedwords + 6;
|
||||
@ -476,6 +447,9 @@ adreno_ringbuffer_addcmds(struct adreno_ringbuffer *rb,
|
||||
total_sizedwords += !(flags & KGSL_CMD_FLAGS_NO_TS_CMP) ? 7 : 0;
|
||||
total_sizedwords += !(flags & KGSL_CMD_FLAGS_NOT_KERNEL_CMD) ? 2 : 0;
|
||||
|
||||
if (adreno_is_a3xx(adreno_dev))
|
||||
total_sizedwords += 7;
|
||||
|
||||
ringcmds = adreno_ringbuffer_allocspace(rb, total_sizedwords);
|
||||
rcmd_gpu = rb->buffer_desc.gpuaddr
|
||||
+ sizeof(uint)*(rb->wptr-total_sizedwords);
|
||||
@ -509,6 +483,21 @@ adreno_ringbuffer_addcmds(struct adreno_ringbuffer *rb,
|
||||
/* start-of-pipeline and end-of-pipeline timestamps */
|
||||
GSL_RB_WRITE(ringcmds, rcmd_gpu, cp_type0_packet(REG_CP_TIMESTAMP, 1));
|
||||
GSL_RB_WRITE(ringcmds, rcmd_gpu, rb->timestamp);
|
||||
|
||||
if (adreno_is_a3xx(adreno_dev)) {
|
||||
/*
|
||||
* FLush HLSQ lazy updates to make sure there are no
|
||||
* rsources pending for indirect loads after the timestamp
|
||||
*/
|
||||
|
||||
GSL_RB_WRITE(ringcmds, rcmd_gpu,
|
||||
cp_type3_packet(CP_EVENT_WRITE, 1));
|
||||
GSL_RB_WRITE(ringcmds, rcmd_gpu, 0x07); /* HLSQ_FLUSH */
|
||||
GSL_RB_WRITE(ringcmds, rcmd_gpu,
|
||||
cp_type3_packet(CP_WAIT_FOR_IDLE, 1));
|
||||
GSL_RB_WRITE(ringcmds, rcmd_gpu, 0x00);
|
||||
}
|
||||
|
||||
GSL_RB_WRITE(ringcmds, rcmd_gpu, cp_type3_packet(CP_EVENT_WRITE, 3));
|
||||
GSL_RB_WRITE(ringcmds, rcmd_gpu, CACHE_FLUSH_TS);
|
||||
GSL_RB_WRITE(ringcmds, rcmd_gpu,
|
||||
@ -532,6 +521,15 @@ adreno_ringbuffer_addcmds(struct adreno_ringbuffer *rb,
|
||||
GSL_RB_WRITE(ringcmds, rcmd_gpu, CP_INT_CNTL__RB_INT_MASK);
|
||||
}
|
||||
|
||||
if (adreno_is_a3xx(adreno_dev)) {
|
||||
/* Dummy set-constant to trigger context rollover */
|
||||
GSL_RB_WRITE(ringcmds, rcmd_gpu,
|
||||
cp_type3_packet(CP_SET_CONSTANT, 2));
|
||||
GSL_RB_WRITE(ringcmds, rcmd_gpu,
|
||||
(0x4<<16)|(A3XX_HLSQ_CL_KERNEL_GROUP_X_REG - 0x2000));
|
||||
GSL_RB_WRITE(ringcmds, rcmd_gpu, 0);
|
||||
}
|
||||
|
||||
adreno_ringbuffer_submit(rb);
|
||||
|
||||
/* return timestamp of issued coREG_ands */
|
||||
|
||||
@ -1,5 +1,4 @@
|
||||
/* Copyright (c) 2002,2007-2011, Code Aurora Forum. All rights reserved.
|
||||
* Copyright (C) 2011 Sony Ericsson Mobile Communications AB.
|
||||
/* Copyright (c) 2002,2007-2012, Code Aurora Forum. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
@ -105,6 +104,13 @@ struct adreno_ringbuffer {
|
||||
|
||||
#define GSL_RB_CNTL_POLL_EN 0x0 /* disable */
|
||||
|
||||
/*
|
||||
* protected mode error checking below register address 0x800
|
||||
* note: if CP_INTERRUPT packet is used then checking needs
|
||||
* to change to below register address 0x7C8
|
||||
*/
|
||||
#define GSL_RB_PROTECTED_MODE_CONTROL 0x200001F2
|
||||
|
||||
int adreno_ringbuffer_issueibcmds(struct kgsl_device_private *dev_priv,
|
||||
struct kgsl_context *context,
|
||||
struct kgsl_ibdesc *ibdesc,
|
||||
@ -126,6 +132,8 @@ void adreno_ringbuffer_issuecmds(struct kgsl_device *device,
|
||||
unsigned int *cmdaddr,
|
||||
int sizedwords);
|
||||
|
||||
void adreno_ringbuffer_submit(struct adreno_ringbuffer *rb);
|
||||
|
||||
void kgsl_cp_intrcallback(struct kgsl_device *device);
|
||||
|
||||
int adreno_ringbuffer_extract(struct adreno_ringbuffer *rb,
|
||||
@ -136,6 +144,9 @@ void
|
||||
adreno_ringbuffer_restore(struct adreno_ringbuffer *rb, unsigned int *rb_buff,
|
||||
int num_rb_contents);
|
||||
|
||||
unsigned int *adreno_ringbuffer_allocspace(struct adreno_ringbuffer *rb,
|
||||
unsigned int numcmds);
|
||||
|
||||
static inline int adreno_ringbuffer_count(struct adreno_ringbuffer *rb,
|
||||
unsigned int rptr)
|
||||
{
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user