182 lines
4.1 KiB
C
182 lines
4.1 KiB
C
/*
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* Copyright (C) 2008
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* Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
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*
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* Copyright (C) 2005-2007 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef _IPU_H_
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#define _IPU_H_
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#include <linux/types.h>
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#include <linux/dmaengine.h>
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/* IPU DMA Controller channel definitions. */
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enum ipu_channel {
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IDMAC_IC_0 = 0, /* IC (encoding task) to memory */
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IDMAC_IC_1 = 1, /* IC (viewfinder task) to memory */
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IDMAC_ADC_0 = 1,
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IDMAC_IC_2 = 2,
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IDMAC_ADC_1 = 2,
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IDMAC_IC_3 = 3,
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IDMAC_IC_4 = 4,
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IDMAC_IC_5 = 5,
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IDMAC_IC_6 = 6,
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IDMAC_IC_7 = 7, /* IC (sensor data) to memory */
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IDMAC_IC_8 = 8,
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IDMAC_IC_9 = 9,
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IDMAC_IC_10 = 10,
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IDMAC_IC_11 = 11,
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IDMAC_IC_12 = 12,
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IDMAC_IC_13 = 13,
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IDMAC_SDC_0 = 14, /* Background synchronous display data */
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IDMAC_SDC_1 = 15, /* Foreground data (overlay) */
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IDMAC_SDC_2 = 16,
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IDMAC_SDC_3 = 17,
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IDMAC_ADC_2 = 18,
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IDMAC_ADC_3 = 19,
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IDMAC_ADC_4 = 20,
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IDMAC_ADC_5 = 21,
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IDMAC_ADC_6 = 22,
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IDMAC_ADC_7 = 23,
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IDMAC_PF_0 = 24,
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IDMAC_PF_1 = 25,
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IDMAC_PF_2 = 26,
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IDMAC_PF_3 = 27,
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IDMAC_PF_4 = 28,
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IDMAC_PF_5 = 29,
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IDMAC_PF_6 = 30,
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IDMAC_PF_7 = 31,
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};
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/* Order significant! */
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enum ipu_channel_status {
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IPU_CHANNEL_FREE,
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IPU_CHANNEL_INITIALIZED,
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IPU_CHANNEL_READY,
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IPU_CHANNEL_ENABLED,
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};
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#define IPU_CHANNELS_NUM 32
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enum pixel_fmt {
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/* 1 byte */
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IPU_PIX_FMT_GENERIC,
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IPU_PIX_FMT_RGB332,
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IPU_PIX_FMT_YUV420P,
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IPU_PIX_FMT_YUV422P,
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IPU_PIX_FMT_YUV420P2,
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IPU_PIX_FMT_YVU422P,
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/* 2 bytes */
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IPU_PIX_FMT_RGB565,
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IPU_PIX_FMT_RGB666,
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IPU_PIX_FMT_BGR666,
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IPU_PIX_FMT_YUYV,
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IPU_PIX_FMT_UYVY,
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/* 3 bytes */
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IPU_PIX_FMT_RGB24,
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IPU_PIX_FMT_BGR24,
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/* 4 bytes */
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IPU_PIX_FMT_GENERIC_32,
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IPU_PIX_FMT_RGB32,
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IPU_PIX_FMT_BGR32,
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IPU_PIX_FMT_ABGR32,
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IPU_PIX_FMT_BGRA32,
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IPU_PIX_FMT_RGBA32,
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};
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enum ipu_color_space {
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IPU_COLORSPACE_RGB,
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IPU_COLORSPACE_YCBCR,
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IPU_COLORSPACE_YUV
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};
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/*
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* Enumeration of IPU rotation modes
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*/
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enum ipu_rotate_mode {
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/* Note the enum values correspond to BAM value */
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IPU_ROTATE_NONE = 0,
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IPU_ROTATE_VERT_FLIP = 1,
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IPU_ROTATE_HORIZ_FLIP = 2,
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IPU_ROTATE_180 = 3,
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IPU_ROTATE_90_RIGHT = 4,
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IPU_ROTATE_90_RIGHT_VFLIP = 5,
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IPU_ROTATE_90_RIGHT_HFLIP = 6,
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IPU_ROTATE_90_LEFT = 7,
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};
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struct ipu_platform_data {
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unsigned int irq_base;
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};
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/*
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* Enumeration of DI ports for ADC.
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*/
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enum display_port {
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DISP0,
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DISP1,
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DISP2,
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DISP3
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};
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struct idmac_video_param {
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unsigned short in_width;
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unsigned short in_height;
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uint32_t in_pixel_fmt;
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unsigned short out_width;
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unsigned short out_height;
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uint32_t out_pixel_fmt;
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unsigned short out_stride;
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bool graphics_combine_en;
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bool global_alpha_en;
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bool key_color_en;
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enum display_port disp;
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unsigned short out_left;
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unsigned short out_top;
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};
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/*
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* Union of initialization parameters for a logical channel. So far only video
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* parameters are used.
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*/
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union ipu_channel_param {
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struct idmac_video_param video;
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};
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struct idmac_tx_desc {
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struct dma_async_tx_descriptor txd;
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struct scatterlist *sg; /* scatterlist for this */
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unsigned int sg_len; /* tx-descriptor. */
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struct list_head list;
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};
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struct idmac_channel {
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struct dma_chan dma_chan;
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dma_cookie_t completed; /* last completed cookie */
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union ipu_channel_param params;
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enum ipu_channel link; /* input channel, linked to the output */
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enum ipu_channel_status status;
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void *client; /* Only one client per channel */
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unsigned int n_tx_desc;
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struct idmac_tx_desc *desc; /* allocated tx-descriptors */
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struct scatterlist *sg[2]; /* scatterlist elements in buffer-0 and -1 */
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struct list_head free_list; /* free tx-descriptors */
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struct list_head queue; /* queued tx-descriptors */
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spinlock_t lock; /* protects sg[0,1], queue */
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struct mutex chan_mutex; /* protects status, cookie, free_list */
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bool sec_chan_en;
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int active_buffer;
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unsigned int eof_irq;
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char eof_name[16]; /* EOF IRQ name for request_irq() */
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};
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#define to_tx_desc(tx) container_of(tx, struct idmac_tx_desc, txd)
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#define to_idmac_chan(c) container_of(c, struct idmac_channel, dma_chan)
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#endif
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