678 lines
15 KiB
C
678 lines
15 KiB
C
/* linux/arch/arm/plat-s3c24xx/irq.c
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*
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* Copyright (c) 2003,2004 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/sysdev.h>
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#include <asm/irq.h>
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#include <asm/mach/irq.h>
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#include <plat/regs-irqtype.h>
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#include <plat/cpu.h>
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#include <plat/pm.h>
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#include <plat/irq.h>
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static void
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s3c_irq_mask(unsigned int irqno)
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{
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unsigned long mask;
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irqno -= IRQ_EINT0;
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mask = __raw_readl(S3C2410_INTMSK);
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mask |= 1UL << irqno;
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__raw_writel(mask, S3C2410_INTMSK);
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}
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static inline void
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s3c_irq_ack(unsigned int irqno)
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{
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unsigned long bitval = 1UL << (irqno - IRQ_EINT0);
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__raw_writel(bitval, S3C2410_SRCPND);
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__raw_writel(bitval, S3C2410_INTPND);
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}
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static inline void
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s3c_irq_maskack(unsigned int irqno)
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{
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unsigned long bitval = 1UL << (irqno - IRQ_EINT0);
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unsigned long mask;
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mask = __raw_readl(S3C2410_INTMSK);
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__raw_writel(mask|bitval, S3C2410_INTMSK);
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__raw_writel(bitval, S3C2410_SRCPND);
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__raw_writel(bitval, S3C2410_INTPND);
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}
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static void
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s3c_irq_unmask(unsigned int irqno)
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{
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unsigned long mask;
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if (irqno != IRQ_TIMER4 && irqno != IRQ_EINT8t23)
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irqdbf2("s3c_irq_unmask %d\n", irqno);
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irqno -= IRQ_EINT0;
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mask = __raw_readl(S3C2410_INTMSK);
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mask &= ~(1UL << irqno);
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__raw_writel(mask, S3C2410_INTMSK);
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}
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struct irq_chip s3c_irq_level_chip = {
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.name = "s3c-level",
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.ack = s3c_irq_maskack,
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.mask = s3c_irq_mask,
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.unmask = s3c_irq_unmask,
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.set_wake = s3c_irq_wake
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};
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struct irq_chip s3c_irq_chip = {
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.name = "s3c",
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.ack = s3c_irq_ack,
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.mask = s3c_irq_mask,
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.unmask = s3c_irq_unmask,
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.set_wake = s3c_irq_wake
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};
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static void
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s3c_irqext_mask(unsigned int irqno)
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{
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unsigned long mask;
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irqno -= EXTINT_OFF;
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mask = __raw_readl(S3C24XX_EINTMASK);
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mask |= ( 1UL << irqno);
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__raw_writel(mask, S3C24XX_EINTMASK);
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}
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static void
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s3c_irqext_ack(unsigned int irqno)
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{
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unsigned long req;
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unsigned long bit;
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unsigned long mask;
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bit = 1UL << (irqno - EXTINT_OFF);
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mask = __raw_readl(S3C24XX_EINTMASK);
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__raw_writel(bit, S3C24XX_EINTPEND);
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req = __raw_readl(S3C24XX_EINTPEND);
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req &= ~mask;
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/* not sure if we should be acking the parent irq... */
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if (irqno <= IRQ_EINT7 ) {
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if ((req & 0xf0) == 0)
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s3c_irq_ack(IRQ_EINT4t7);
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} else {
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if ((req >> 8) == 0)
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s3c_irq_ack(IRQ_EINT8t23);
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}
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}
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static void
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s3c_irqext_unmask(unsigned int irqno)
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{
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unsigned long mask;
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irqno -= EXTINT_OFF;
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mask = __raw_readl(S3C24XX_EINTMASK);
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mask &= ~( 1UL << irqno);
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__raw_writel(mask, S3C24XX_EINTMASK);
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}
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int
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s3c_irqext_type(unsigned int irq, unsigned int type)
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{
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void __iomem *extint_reg;
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void __iomem *gpcon_reg;
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unsigned long gpcon_offset, extint_offset;
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unsigned long newvalue = 0, value;
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if ((irq >= IRQ_EINT0) && (irq <= IRQ_EINT3))
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{
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gpcon_reg = S3C2410_GPFCON;
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extint_reg = S3C24XX_EXTINT0;
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gpcon_offset = (irq - IRQ_EINT0) * 2;
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extint_offset = (irq - IRQ_EINT0) * 4;
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}
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else if ((irq >= IRQ_EINT4) && (irq <= IRQ_EINT7))
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{
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gpcon_reg = S3C2410_GPFCON;
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extint_reg = S3C24XX_EXTINT0;
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gpcon_offset = (irq - (EXTINT_OFF)) * 2;
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extint_offset = (irq - (EXTINT_OFF)) * 4;
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}
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else if ((irq >= IRQ_EINT8) && (irq <= IRQ_EINT15))
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{
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gpcon_reg = S3C2410_GPGCON;
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extint_reg = S3C24XX_EXTINT1;
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gpcon_offset = (irq - IRQ_EINT8) * 2;
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extint_offset = (irq - IRQ_EINT8) * 4;
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}
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else if ((irq >= IRQ_EINT16) && (irq <= IRQ_EINT23))
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{
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gpcon_reg = S3C2410_GPGCON;
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extint_reg = S3C24XX_EXTINT2;
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gpcon_offset = (irq - IRQ_EINT8) * 2;
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extint_offset = (irq - IRQ_EINT16) * 4;
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} else
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return -1;
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/* Set the GPIO to external interrupt mode */
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value = __raw_readl(gpcon_reg);
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value = (value & ~(3 << gpcon_offset)) | (0x02 << gpcon_offset);
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__raw_writel(value, gpcon_reg);
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/* Set the external interrupt to pointed trigger type */
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switch (type)
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{
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case IRQ_TYPE_NONE:
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printk(KERN_WARNING "No edge setting!\n");
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break;
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case IRQ_TYPE_EDGE_RISING:
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newvalue = S3C2410_EXTINT_RISEEDGE;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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newvalue = S3C2410_EXTINT_FALLEDGE;
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break;
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case IRQ_TYPE_EDGE_BOTH:
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newvalue = S3C2410_EXTINT_BOTHEDGE;
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break;
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case IRQ_TYPE_LEVEL_LOW:
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newvalue = S3C2410_EXTINT_LOWLEV;
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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newvalue = S3C2410_EXTINT_HILEV;
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break;
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default:
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printk(KERN_ERR "No such irq type %d", type);
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return -1;
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}
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value = __raw_readl(extint_reg);
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value = (value & ~(7 << extint_offset)) | (newvalue << extint_offset);
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__raw_writel(value, extint_reg);
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return 0;
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}
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static struct irq_chip s3c_irqext_chip = {
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.name = "s3c-ext",
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.mask = s3c_irqext_mask,
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.unmask = s3c_irqext_unmask,
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.ack = s3c_irqext_ack,
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.set_type = s3c_irqext_type,
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.set_wake = s3c_irqext_wake
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};
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static struct irq_chip s3c_irq_eint0t4 = {
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.name = "s3c-ext0",
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.ack = s3c_irq_ack,
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.mask = s3c_irq_mask,
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.unmask = s3c_irq_unmask,
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.set_wake = s3c_irq_wake,
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.set_type = s3c_irqext_type,
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};
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/* mask values for the parent registers for each of the interrupt types */
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#define INTMSK_UART0 (1UL << (IRQ_UART0 - IRQ_EINT0))
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#define INTMSK_UART1 (1UL << (IRQ_UART1 - IRQ_EINT0))
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#define INTMSK_UART2 (1UL << (IRQ_UART2 - IRQ_EINT0))
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#define INTMSK_ADCPARENT (1UL << (IRQ_ADCPARENT - IRQ_EINT0))
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/* UART0 */
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static void
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s3c_irq_uart0_mask(unsigned int irqno)
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{
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s3c_irqsub_mask(irqno, INTMSK_UART0, 7);
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}
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static void
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s3c_irq_uart0_unmask(unsigned int irqno)
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{
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s3c_irqsub_unmask(irqno, INTMSK_UART0);
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}
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static void
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s3c_irq_uart0_ack(unsigned int irqno)
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{
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s3c_irqsub_maskack(irqno, INTMSK_UART0, 7);
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}
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static struct irq_chip s3c_irq_uart0 = {
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.name = "s3c-uart0",
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.mask = s3c_irq_uart0_mask,
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.unmask = s3c_irq_uart0_unmask,
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.ack = s3c_irq_uart0_ack,
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};
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/* UART1 */
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static void
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s3c_irq_uart1_mask(unsigned int irqno)
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{
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s3c_irqsub_mask(irqno, INTMSK_UART1, 7 << 3);
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}
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static void
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s3c_irq_uart1_unmask(unsigned int irqno)
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{
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s3c_irqsub_unmask(irqno, INTMSK_UART1);
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}
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static void
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s3c_irq_uart1_ack(unsigned int irqno)
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{
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s3c_irqsub_maskack(irqno, INTMSK_UART1, 7 << 3);
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}
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static struct irq_chip s3c_irq_uart1 = {
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.name = "s3c-uart1",
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.mask = s3c_irq_uart1_mask,
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.unmask = s3c_irq_uart1_unmask,
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.ack = s3c_irq_uart1_ack,
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};
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/* UART2 */
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static void
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s3c_irq_uart2_mask(unsigned int irqno)
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{
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s3c_irqsub_mask(irqno, INTMSK_UART2, 7 << 6);
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}
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static void
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s3c_irq_uart2_unmask(unsigned int irqno)
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{
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s3c_irqsub_unmask(irqno, INTMSK_UART2);
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}
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static void
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s3c_irq_uart2_ack(unsigned int irqno)
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{
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s3c_irqsub_maskack(irqno, INTMSK_UART2, 7 << 6);
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}
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static struct irq_chip s3c_irq_uart2 = {
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.name = "s3c-uart2",
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.mask = s3c_irq_uart2_mask,
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.unmask = s3c_irq_uart2_unmask,
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.ack = s3c_irq_uart2_ack,
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};
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/* ADC and Touchscreen */
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static void
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s3c_irq_adc_mask(unsigned int irqno)
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{
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s3c_irqsub_mask(irqno, INTMSK_ADCPARENT, 3 << 9);
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}
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static void
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s3c_irq_adc_unmask(unsigned int irqno)
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{
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s3c_irqsub_unmask(irqno, INTMSK_ADCPARENT);
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}
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static void
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s3c_irq_adc_ack(unsigned int irqno)
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{
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s3c_irqsub_ack(irqno, INTMSK_ADCPARENT, 3 << 9);
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}
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static struct irq_chip s3c_irq_adc = {
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.name = "s3c-adc",
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.mask = s3c_irq_adc_mask,
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.unmask = s3c_irq_adc_unmask,
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.ack = s3c_irq_adc_ack,
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};
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/* irq demux for adc */
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static void s3c_irq_demux_adc(unsigned int irq,
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struct irq_desc *desc)
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{
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unsigned int subsrc, submsk;
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unsigned int offset = 9;
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/* read the current pending interrupts, and the mask
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* for what it is available */
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subsrc = __raw_readl(S3C2410_SUBSRCPND);
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submsk = __raw_readl(S3C2410_INTSUBMSK);
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subsrc &= ~submsk;
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subsrc >>= offset;
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subsrc &= 3;
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if (subsrc != 0) {
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if (subsrc & 1) {
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generic_handle_irq(IRQ_TC);
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}
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if (subsrc & 2) {
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generic_handle_irq(IRQ_ADC);
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}
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}
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}
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static void s3c_irq_demux_uart(unsigned int start)
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{
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unsigned int subsrc, submsk;
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unsigned int offset = start - IRQ_S3CUART_RX0;
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/* read the current pending interrupts, and the mask
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* for what it is available */
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subsrc = __raw_readl(S3C2410_SUBSRCPND);
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submsk = __raw_readl(S3C2410_INTSUBMSK);
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irqdbf2("s3c_irq_demux_uart: start=%d (%d), subsrc=0x%08x,0x%08x\n",
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start, offset, subsrc, submsk);
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subsrc &= ~submsk;
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subsrc >>= offset;
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subsrc &= 7;
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if (subsrc != 0) {
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if (subsrc & 1)
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generic_handle_irq(start);
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if (subsrc & 2)
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generic_handle_irq(start+1);
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if (subsrc & 4)
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generic_handle_irq(start+2);
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}
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}
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/* uart demux entry points */
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static void
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s3c_irq_demux_uart0(unsigned int irq,
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struct irq_desc *desc)
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{
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irq = irq;
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s3c_irq_demux_uart(IRQ_S3CUART_RX0);
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}
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static void
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s3c_irq_demux_uart1(unsigned int irq,
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struct irq_desc *desc)
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{
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irq = irq;
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s3c_irq_demux_uart(IRQ_S3CUART_RX1);
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}
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static void
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s3c_irq_demux_uart2(unsigned int irq,
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struct irq_desc *desc)
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{
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irq = irq;
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s3c_irq_demux_uart(IRQ_S3CUART_RX2);
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}
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static void
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s3c_irq_demux_extint8(unsigned int irq,
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struct irq_desc *desc)
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{
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unsigned long eintpnd = __raw_readl(S3C24XX_EINTPEND);
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unsigned long eintmsk = __raw_readl(S3C24XX_EINTMASK);
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eintpnd &= ~eintmsk;
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eintpnd &= ~0xff; /* ignore lower irqs */
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/* we may as well handle all the pending IRQs here */
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while (eintpnd) {
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irq = __ffs(eintpnd);
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eintpnd &= ~(1<<irq);
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irq += (IRQ_EINT4 - 4);
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generic_handle_irq(irq);
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}
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}
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static void
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s3c_irq_demux_extint4t7(unsigned int irq,
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struct irq_desc *desc)
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{
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unsigned long eintpnd = __raw_readl(S3C24XX_EINTPEND);
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unsigned long eintmsk = __raw_readl(S3C24XX_EINTMASK);
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eintpnd &= ~eintmsk;
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eintpnd &= 0xff; /* only lower irqs */
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/* we may as well handle all the pending IRQs here */
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while (eintpnd) {
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irq = __ffs(eintpnd);
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eintpnd &= ~(1<<irq);
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irq += (IRQ_EINT4 - 4);
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generic_handle_irq(irq);
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}
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}
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#ifdef CONFIG_FIQ
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/**
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* s3c24xx_set_fiq - set the FIQ routing
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* @irq: IRQ number to route to FIQ on processor.
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* @on: Whether to route @irq to the FIQ, or to remove the FIQ routing.
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*
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* Change the state of the IRQ to FIQ routing depending on @irq and @on. If
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* @on is true, the @irq is checked to see if it can be routed and the
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* interrupt controller updated to route the IRQ. If @on is false, the FIQ
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* routing is cleared, regardless of which @irq is specified.
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*/
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int s3c24xx_set_fiq(unsigned int irq, bool on)
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{
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u32 intmod;
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unsigned offs;
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if (on) {
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offs = irq - FIQ_START;
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if (offs > 31)
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return -EINVAL;
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intmod = 1 << offs;
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} else {
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intmod = 0;
|
|
}
|
|
|
|
__raw_writel(intmod, S3C2410_INTMOD);
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
|
|
/* s3c24xx_init_irq
|
|
*
|
|
* Initialise S3C2410 IRQ system
|
|
*/
|
|
|
|
void __init s3c24xx_init_irq(void)
|
|
{
|
|
unsigned long pend;
|
|
unsigned long last;
|
|
int irqno;
|
|
int i;
|
|
|
|
#ifdef CONFIG_FIQ
|
|
init_FIQ();
|
|
#endif
|
|
|
|
irqdbf("s3c2410_init_irq: clearing interrupt status flags\n");
|
|
|
|
/* first, clear all interrupts pending... */
|
|
|
|
last = 0;
|
|
for (i = 0; i < 4; i++) {
|
|
pend = __raw_readl(S3C24XX_EINTPEND);
|
|
|
|
if (pend == 0 || pend == last)
|
|
break;
|
|
|
|
__raw_writel(pend, S3C24XX_EINTPEND);
|
|
printk("irq: clearing pending ext status %08x\n", (int)pend);
|
|
last = pend;
|
|
}
|
|
|
|
last = 0;
|
|
for (i = 0; i < 4; i++) {
|
|
pend = __raw_readl(S3C2410_INTPND);
|
|
|
|
if (pend == 0 || pend == last)
|
|
break;
|
|
|
|
__raw_writel(pend, S3C2410_SRCPND);
|
|
__raw_writel(pend, S3C2410_INTPND);
|
|
printk("irq: clearing pending status %08x\n", (int)pend);
|
|
last = pend;
|
|
}
|
|
|
|
last = 0;
|
|
for (i = 0; i < 4; i++) {
|
|
pend = __raw_readl(S3C2410_SUBSRCPND);
|
|
|
|
if (pend == 0 || pend == last)
|
|
break;
|
|
|
|
printk("irq: clearing subpending status %08x\n", (int)pend);
|
|
__raw_writel(pend, S3C2410_SUBSRCPND);
|
|
last = pend;
|
|
}
|
|
|
|
/* register the main interrupts */
|
|
|
|
irqdbf("s3c2410_init_irq: registering s3c2410 interrupt handlers\n");
|
|
|
|
for (irqno = IRQ_EINT4t7; irqno <= IRQ_ADCPARENT; irqno++) {
|
|
/* set all the s3c2410 internal irqs */
|
|
|
|
switch (irqno) {
|
|
/* deal with the special IRQs (cascaded) */
|
|
|
|
case IRQ_EINT4t7:
|
|
case IRQ_EINT8t23:
|
|
case IRQ_UART0:
|
|
case IRQ_UART1:
|
|
case IRQ_UART2:
|
|
case IRQ_ADCPARENT:
|
|
set_irq_chip(irqno, &s3c_irq_level_chip);
|
|
set_irq_handler(irqno, handle_level_irq);
|
|
break;
|
|
|
|
case IRQ_RESERVED6:
|
|
case IRQ_RESERVED24:
|
|
/* no IRQ here */
|
|
break;
|
|
|
|
default:
|
|
//irqdbf("registering irq %d (s3c irq)\n", irqno);
|
|
set_irq_chip(irqno, &s3c_irq_chip);
|
|
set_irq_handler(irqno, handle_edge_irq);
|
|
set_irq_flags(irqno, IRQF_VALID);
|
|
}
|
|
}
|
|
|
|
/* setup the cascade irq handlers */
|
|
|
|
set_irq_chained_handler(IRQ_EINT4t7, s3c_irq_demux_extint4t7);
|
|
set_irq_chained_handler(IRQ_EINT8t23, s3c_irq_demux_extint8);
|
|
|
|
set_irq_chained_handler(IRQ_UART0, s3c_irq_demux_uart0);
|
|
set_irq_chained_handler(IRQ_UART1, s3c_irq_demux_uart1);
|
|
set_irq_chained_handler(IRQ_UART2, s3c_irq_demux_uart2);
|
|
set_irq_chained_handler(IRQ_ADCPARENT, s3c_irq_demux_adc);
|
|
|
|
/* external interrupts */
|
|
|
|
for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) {
|
|
irqdbf("registering irq %d (ext int)\n", irqno);
|
|
set_irq_chip(irqno, &s3c_irq_eint0t4);
|
|
set_irq_handler(irqno, handle_edge_irq);
|
|
set_irq_flags(irqno, IRQF_VALID);
|
|
}
|
|
|
|
for (irqno = IRQ_EINT4; irqno <= IRQ_EINT23; irqno++) {
|
|
irqdbf("registering irq %d (extended s3c irq)\n", irqno);
|
|
set_irq_chip(irqno, &s3c_irqext_chip);
|
|
set_irq_handler(irqno, handle_edge_irq);
|
|
set_irq_flags(irqno, IRQF_VALID);
|
|
}
|
|
|
|
/* register the uart interrupts */
|
|
|
|
irqdbf("s3c2410: registering external interrupts\n");
|
|
|
|
for (irqno = IRQ_S3CUART_RX0; irqno <= IRQ_S3CUART_ERR0; irqno++) {
|
|
irqdbf("registering irq %d (s3c uart0 irq)\n", irqno);
|
|
set_irq_chip(irqno, &s3c_irq_uart0);
|
|
set_irq_handler(irqno, handle_level_irq);
|
|
set_irq_flags(irqno, IRQF_VALID);
|
|
}
|
|
|
|
for (irqno = IRQ_S3CUART_RX1; irqno <= IRQ_S3CUART_ERR1; irqno++) {
|
|
irqdbf("registering irq %d (s3c uart1 irq)\n", irqno);
|
|
set_irq_chip(irqno, &s3c_irq_uart1);
|
|
set_irq_handler(irqno, handle_level_irq);
|
|
set_irq_flags(irqno, IRQF_VALID);
|
|
}
|
|
|
|
for (irqno = IRQ_S3CUART_RX2; irqno <= IRQ_S3CUART_ERR2; irqno++) {
|
|
irqdbf("registering irq %d (s3c uart2 irq)\n", irqno);
|
|
set_irq_chip(irqno, &s3c_irq_uart2);
|
|
set_irq_handler(irqno, handle_level_irq);
|
|
set_irq_flags(irqno, IRQF_VALID);
|
|
}
|
|
|
|
for (irqno = IRQ_TC; irqno <= IRQ_ADC; irqno++) {
|
|
irqdbf("registering irq %d (s3c adc irq)\n", irqno);
|
|
set_irq_chip(irqno, &s3c_irq_adc);
|
|
set_irq_handler(irqno, handle_edge_irq);
|
|
set_irq_flags(irqno, IRQF_VALID);
|
|
}
|
|
|
|
irqdbf("s3c2410: registered interrupt handlers\n");
|
|
}
|