147 lines
4.1 KiB
C
147 lines
4.1 KiB
C
/*
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* Low-Level PCI Support for the SH7780
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*
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* Copyright (C) 2005 - 2009 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/errno.h>
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#include <linux/delay.h>
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#include "pci-sh4.h"
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static struct resource sh7785_io_resource = {
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.name = "SH7785_IO",
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.start = SH7780_PCI_IO_BASE,
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.end = SH7780_PCI_IO_BASE + SH7780_PCI_IO_SIZE - 1,
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.flags = IORESOURCE_IO
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};
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static struct resource sh7785_mem_resource = {
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.name = "SH7785_mem",
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.start = SH7780_PCI_MEMORY_BASE,
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.end = SH7780_PCI_MEMORY_BASE + SH7780_PCI_MEM_SIZE - 1,
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.flags = IORESOURCE_MEM
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};
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static struct pci_channel sh7780_pci_controller = {
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.pci_ops = &sh4_pci_ops,
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.mem_resource = &sh7785_mem_resource,
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.mem_offset = 0x00000000,
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.io_resource = &sh7785_io_resource,
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.io_offset = 0x00000000,
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.io_map_base = SH7780_PCI_IO_BASE,
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};
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static struct sh4_pci_address_map sh7780_pci_map = {
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.window0 = {
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#if defined(CONFIG_32BIT)
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.base = SH7780_32BIT_DDR_BASE_ADDR,
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.size = 0x40000000,
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#else
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.base = SH7780_CS0_BASE_ADDR,
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.size = 0x20000000,
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#endif
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},
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};
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static int __init sh7780_pci_init(void)
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{
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struct pci_channel *chan = &sh7780_pci_controller;
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unsigned int id;
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const char *type = NULL;
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int ret;
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u32 word;
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printk(KERN_NOTICE "PCI: Starting intialization.\n");
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chan->reg_base = 0xfe040000;
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/* Enable CPU access to the PCIC registers. */
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__raw_writel(PCIECR_ENBL, PCIECR);
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id = __raw_readw(chan->reg_base + SH7780_PCIVID);
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if (id != SH7780_VENDOR_ID) {
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printk(KERN_ERR "PCI: Unknown vendor ID 0x%04x.\n", id);
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return -ENODEV;
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}
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id = __raw_readw(chan->reg_base + SH7780_PCIDID);
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type = (id == SH7763_DEVICE_ID) ? "SH7763" :
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(id == SH7780_DEVICE_ID) ? "SH7780" :
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(id == SH7781_DEVICE_ID) ? "SH7781" :
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(id == SH7785_DEVICE_ID) ? "SH7785" :
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NULL;
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if (unlikely(!type)) {
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printk(KERN_ERR "PCI: Found an unsupported Renesas host "
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"controller, device id 0x%04x.\n", id);
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return -EINVAL;
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}
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printk(KERN_NOTICE "PCI: Found a Renesas %s host "
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"controller, revision %d.\n", type,
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__raw_readb(chan->reg_base + SH7780_PCIRID));
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if ((ret = sh4_pci_check_direct(chan)) != 0)
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return ret;
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/*
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* Set the class and sub-class codes.
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*/
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__raw_writeb(PCI_CLASS_BRIDGE_HOST >> 8,
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chan->reg_base + SH7780_PCIBCC);
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__raw_writeb(PCI_CLASS_BRIDGE_HOST & 0xff,
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chan->reg_base + SH7780_PCISUB);
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/*
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* Set IO and Mem windows to local address
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* Make PCI and local address the same for easy 1 to 1 mapping
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*/
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pci_write_reg(chan, sh7780_pci_map.window0.size - 0xfffff, SH4_PCILSR0);
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/* Set the values on window 0 PCI config registers */
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pci_write_reg(chan, sh7780_pci_map.window0.base, SH4_PCILAR0);
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pci_write_reg(chan, sh7780_pci_map.window0.base, SH7780_PCIMBAR0);
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pci_write_reg(chan, 0x0000380f, SH4_PCIAINTM);
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/* Set up standard PCI config registers */
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__raw_writew(0xFB00, chan->reg_base + SH7780_PCISTATUS);
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__raw_writew(0x0047, chan->reg_base + SH7780_PCICMD);
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__raw_writew(0x1912, chan->reg_base + SH7780_PCISVID);
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__raw_writew(0x0001, chan->reg_base + SH7780_PCISID);
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__raw_writeb(0x00, chan->reg_base + SH7780_PCIPIF);
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/* Apply any last-minute PCIC fixups */
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pci_fixup_pcic(chan);
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pci_write_reg(chan, 0xfd000000, SH7780_PCIMBR0);
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pci_write_reg(chan, 0x00fc0000, SH7780_PCIMBMR0);
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#ifdef CONFIG_32BIT
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pci_write_reg(chan, 0xc0000000, SH7780_PCIMBR2);
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pci_write_reg(chan, 0x20000000 - SH7780_PCI_IO_SIZE, SH7780_PCIMBMR2);
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#endif
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/* Set IOBR for windows containing area specified in pci.h */
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pci_write_reg(chan, chan->io_resource->start & ~(SH7780_PCI_IO_SIZE-1),
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SH7780_PCIIOBR);
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pci_write_reg(chan, ((SH7780_PCI_IO_SIZE-1) & (7<<18)),
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SH7780_PCIIOBMR);
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/* SH7780 init done, set central function init complete */
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/* use round robin mode to stop a device starving/overruning */
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word = SH4_PCICR_PREFIX | SH4_PCICR_CFIN | SH4_PCICR_FTO;
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pci_write_reg(chan, word, SH4_PCICR);
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register_pci_controller(chan);
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return 0;
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}
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arch_initcall(sh7780_pci_init);
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