348 lines
9.5 KiB
C
348 lines
9.5 KiB
C
/* Copyright (C) 2000 Philipp Rumpf <prumpf@tux.org>
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* Copyright (C) 2006 Kyle McMartin <kyle@parisc-linux.org>
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*/
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#ifndef _ASM_PARISC_ATOMIC_H_
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#define _ASM_PARISC_ATOMIC_H_
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#include <linux/types.h>
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#include <asm/system.h>
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/*
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* Atomic operations that C can't guarantee us. Useful for
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* resource counting etc..
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*
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* And probably incredibly slow on parisc. OTOH, we don't
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* have to write any serious assembly. prumpf
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*/
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#ifdef CONFIG_SMP
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#include <asm/spinlock.h>
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#include <asm/cache.h> /* we use L1_CACHE_BYTES */
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/* Use an array of spinlocks for our atomic_ts.
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* Hash function to index into a different SPINLOCK.
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* Since "a" is usually an address, use one spinlock per cacheline.
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*/
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# define ATOMIC_HASH_SIZE 4
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# define ATOMIC_HASH(a) (&(__atomic_hash[ (((unsigned long) (a))/L1_CACHE_BYTES) & (ATOMIC_HASH_SIZE-1) ]))
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extern raw_spinlock_t __atomic_hash[ATOMIC_HASH_SIZE] __lock_aligned;
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/* Can't use raw_spin_lock_irq because of #include problems, so
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* this is the substitute */
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#define _atomic_spin_lock_irqsave(l,f) do { \
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raw_spinlock_t *s = ATOMIC_HASH(l); \
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local_irq_save(f); \
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__raw_spin_lock(s); \
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} while(0)
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#define _atomic_spin_unlock_irqrestore(l,f) do { \
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raw_spinlock_t *s = ATOMIC_HASH(l); \
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__raw_spin_unlock(s); \
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local_irq_restore(f); \
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} while(0)
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#else
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# define _atomic_spin_lock_irqsave(l,f) do { local_irq_save(f); } while (0)
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# define _atomic_spin_unlock_irqrestore(l,f) do { local_irq_restore(f); } while (0)
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#endif
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/* This should get optimized out since it's never called.
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** Or get a link error if xchg is used "wrong".
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*/
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extern void __xchg_called_with_bad_pointer(void);
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/* __xchg32/64 defined in arch/parisc/lib/bitops.c */
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extern unsigned long __xchg8(char, char *);
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extern unsigned long __xchg32(int, int *);
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#ifdef CONFIG_64BIT
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extern unsigned long __xchg64(unsigned long, unsigned long *);
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#endif
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/* optimizer better get rid of switch since size is a constant */
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static __inline__ unsigned long
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__xchg(unsigned long x, __volatile__ void * ptr, int size)
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{
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switch(size) {
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#ifdef CONFIG_64BIT
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case 8: return __xchg64(x,(unsigned long *) ptr);
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#endif
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case 4: return __xchg32((int) x, (int *) ptr);
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case 1: return __xchg8((char) x, (char *) ptr);
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}
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__xchg_called_with_bad_pointer();
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return x;
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}
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/*
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** REVISIT - Abandoned use of LDCW in xchg() for now:
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** o need to test sizeof(*ptr) to avoid clearing adjacent bytes
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** o and while we are at it, could CONFIG_64BIT code use LDCD too?
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**
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** if (__builtin_constant_p(x) && (x == NULL))
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** if (((unsigned long)p & 0xf) == 0)
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** return __ldcw(p);
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*/
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#define xchg(ptr,x) \
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((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
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#define __HAVE_ARCH_CMPXCHG 1
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/* bug catcher for when unsupported size is used - won't link */
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extern void __cmpxchg_called_with_bad_pointer(void);
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/* __cmpxchg_u32/u64 defined in arch/parisc/lib/bitops.c */
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extern unsigned long __cmpxchg_u32(volatile unsigned int *m, unsigned int old, unsigned int new_);
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extern unsigned long __cmpxchg_u64(volatile unsigned long *ptr, unsigned long old, unsigned long new_);
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/* don't worry...optimizer will get rid of most of this */
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static __inline__ unsigned long
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__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new_, int size)
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{
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switch(size) {
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#ifdef CONFIG_64BIT
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case 8: return __cmpxchg_u64((unsigned long *)ptr, old, new_);
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#endif
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case 4: return __cmpxchg_u32((unsigned int *)ptr, (unsigned int) old, (unsigned int) new_);
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}
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__cmpxchg_called_with_bad_pointer();
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return old;
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}
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#define cmpxchg(ptr,o,n) \
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({ \
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__typeof__(*(ptr)) _o_ = (o); \
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__typeof__(*(ptr)) _n_ = (n); \
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(__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \
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(unsigned long)_n_, sizeof(*(ptr))); \
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})
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#include <asm-generic/cmpxchg-local.h>
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static inline unsigned long __cmpxchg_local(volatile void *ptr,
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unsigned long old,
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unsigned long new_, int size)
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{
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switch (size) {
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#ifdef CONFIG_64BIT
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case 8: return __cmpxchg_u64((unsigned long *)ptr, old, new_);
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#endif
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case 4: return __cmpxchg_u32(ptr, old, new_);
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default:
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return __cmpxchg_local_generic(ptr, old, new_, size);
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}
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}
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/*
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* cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
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* them available.
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*/
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#define cmpxchg_local(ptr, o, n) \
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((__typeof__(*(ptr)))__cmpxchg_local((ptr), (unsigned long)(o), \
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(unsigned long)(n), sizeof(*(ptr))))
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#ifdef CONFIG_64BIT
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#define cmpxchg64_local(ptr, o, n) \
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({ \
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BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
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cmpxchg_local((ptr), (o), (n)); \
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})
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#else
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#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
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#endif
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/*
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* Note that we need not lock read accesses - aligned word writes/reads
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* are atomic, so a reader never sees inconsistent values.
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*/
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/* It's possible to reduce all atomic operations to either
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* __atomic_add_return, atomic_set and atomic_read (the latter
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* is there only for consistency).
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*/
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static __inline__ int __atomic_add_return(int i, atomic_t *v)
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{
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int ret;
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unsigned long flags;
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_atomic_spin_lock_irqsave(v, flags);
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ret = (v->counter += i);
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_atomic_spin_unlock_irqrestore(v, flags);
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return ret;
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}
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static __inline__ void atomic_set(atomic_t *v, int i)
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{
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unsigned long flags;
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_atomic_spin_lock_irqsave(v, flags);
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v->counter = i;
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_atomic_spin_unlock_irqrestore(v, flags);
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}
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static __inline__ int atomic_read(const atomic_t *v)
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{
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return v->counter;
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}
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/* exported interface */
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#define atomic_cmpxchg(v, o, n) (cmpxchg(&((v)->counter), (o), (n)))
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#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
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/**
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* atomic_add_unless - add unless the number is a given value
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* @v: pointer of type atomic_t
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* @a: the amount to add to v...
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* @u: ...unless v is equal to u.
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*
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* Atomically adds @a to @v, so long as it was not @u.
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* Returns non-zero if @v was not @u, and zero otherwise.
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*/
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static __inline__ int atomic_add_unless(atomic_t *v, int a, int u)
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{
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int c, old;
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c = atomic_read(v);
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for (;;) {
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if (unlikely(c == (u)))
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break;
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old = atomic_cmpxchg((v), c, c + (a));
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if (likely(old == c))
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break;
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c = old;
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}
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return c != (u);
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}
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#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
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#define atomic_add(i,v) ((void)(__atomic_add_return( (i),(v))))
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#define atomic_sub(i,v) ((void)(__atomic_add_return(-(i),(v))))
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#define atomic_inc(v) ((void)(__atomic_add_return( 1,(v))))
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#define atomic_dec(v) ((void)(__atomic_add_return( -1,(v))))
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#define atomic_add_return(i,v) (__atomic_add_return( (i),(v)))
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#define atomic_sub_return(i,v) (__atomic_add_return(-(i),(v)))
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#define atomic_inc_return(v) (__atomic_add_return( 1,(v)))
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#define atomic_dec_return(v) (__atomic_add_return( -1,(v)))
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#define atomic_add_negative(a, v) (atomic_add_return((a), (v)) < 0)
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/*
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* atomic_inc_and_test - increment and test
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* @v: pointer of type atomic_t
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*
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* Atomically increments @v by 1
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* and returns true if the result is zero, or false for all
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* other cases.
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*/
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#define atomic_inc_and_test(v) (atomic_inc_return(v) == 0)
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#define atomic_dec_and_test(v) (atomic_dec_return(v) == 0)
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#define atomic_sub_and_test(i,v) (atomic_sub_return((i),(v)) == 0)
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#define ATOMIC_INIT(i) ((atomic_t) { (i) })
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#define smp_mb__before_atomic_dec() smp_mb()
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#define smp_mb__after_atomic_dec() smp_mb()
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#define smp_mb__before_atomic_inc() smp_mb()
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#define smp_mb__after_atomic_inc() smp_mb()
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#ifdef CONFIG_64BIT
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#define ATOMIC64_INIT(i) ((atomic64_t) { (i) })
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static __inline__ int
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__atomic64_add_return(s64 i, atomic64_t *v)
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{
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int ret;
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unsigned long flags;
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_atomic_spin_lock_irqsave(v, flags);
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ret = (v->counter += i);
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_atomic_spin_unlock_irqrestore(v, flags);
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return ret;
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}
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static __inline__ void
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atomic64_set(atomic64_t *v, s64 i)
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{
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unsigned long flags;
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_atomic_spin_lock_irqsave(v, flags);
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v->counter = i;
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_atomic_spin_unlock_irqrestore(v, flags);
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}
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static __inline__ s64
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atomic64_read(const atomic64_t *v)
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{
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return v->counter;
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}
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#define atomic64_add(i,v) ((void)(__atomic64_add_return( ((s64)(i)),(v))))
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#define atomic64_sub(i,v) ((void)(__atomic64_add_return(-((s64)(i)),(v))))
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#define atomic64_inc(v) ((void)(__atomic64_add_return( 1,(v))))
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#define atomic64_dec(v) ((void)(__atomic64_add_return( -1,(v))))
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#define atomic64_add_return(i,v) (__atomic64_add_return( ((s64)(i)),(v)))
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#define atomic64_sub_return(i,v) (__atomic64_add_return(-((s64)(i)),(v)))
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#define atomic64_inc_return(v) (__atomic64_add_return( 1,(v)))
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#define atomic64_dec_return(v) (__atomic64_add_return( -1,(v)))
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#define atomic64_add_negative(a, v) (atomic64_add_return((a), (v)) < 0)
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#define atomic64_inc_and_test(v) (atomic64_inc_return(v) == 0)
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#define atomic64_dec_and_test(v) (atomic64_dec_return(v) == 0)
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#define atomic64_sub_and_test(i,v) (atomic64_sub_return((i),(v)) == 0)
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/* exported interface */
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#define atomic64_cmpxchg(v, o, n) \
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((__typeof__((v)->counter))cmpxchg(&((v)->counter), (o), (n)))
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#define atomic64_xchg(v, new) (xchg(&((v)->counter), new))
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/**
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* atomic64_add_unless - add unless the number is a given value
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* @v: pointer of type atomic64_t
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* @a: the amount to add to v...
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* @u: ...unless v is equal to u.
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*
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* Atomically adds @a to @v, so long as it was not @u.
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* Returns non-zero if @v was not @u, and zero otherwise.
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*/
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static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u)
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{
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long c, old;
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c = atomic64_read(v);
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for (;;) {
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if (unlikely(c == (u)))
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break;
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old = atomic64_cmpxchg((v), c, c + (a));
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if (likely(old == c))
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break;
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c = old;
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}
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return c != (u);
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}
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#define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1, 0)
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#else /* CONFIG_64BIT */
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#include <asm-generic/atomic64.h>
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#endif /* !CONFIG_64BIT */
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#include <asm-generic/atomic-long.h>
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#endif /* _ASM_PARISC_ATOMIC_H_ */
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