78 lines
		
	
	
		
			2.2 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			78 lines
		
	
	
		
			2.2 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
/****************************************************************************/
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/*
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 *      mcfmbus.h -- Coldfire MBUS support defines.
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 *
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 *      (C) Copyright 1999, Martin Floeer (mfloeer@axcent.de) 
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 */
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/****************************************************************************/
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#ifndef mcfmbus_h
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#define mcfmbus_h
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#define MCFMBUS_BASE		0x280
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#define MCFMBUS_IRQ_VECTOR	0x19
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#define MCFMBUS_IRQ		0x1
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#define MCFMBUS_CLK		0x3f
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#define MCFMBUS_IRQ_LEVEL	0x07	/*IRQ Level 1*/
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#define MCFMBUS_ADDRESS		0x01
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/*
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*	Define the 5307 MBUS register set addresses
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*/
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#define MCFMBUS_MADR	0x00
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#define MCFMBUS_MFDR	0x04
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#define MCFMBUS_MBCR	0x08
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#define MCFMBUS_MBSR	0x0C
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#define MCFMBUS_MBDR	0x10
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#define MCFMBUS_MADR_ADDR(a)	(((a)&0x7F)<<0x01) /*Slave Address*/
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#define MCFMBUS_MFDR_MBC(a)	((a)&0x3F)	   /*M-Bus Clock*/
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/*
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*	Define bit flags in Control Register
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*/
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#define MCFMBUS_MBCR_MEN           (0x80)  /* M-Bus Enable                 */
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#define MCFMBUS_MBCR_MIEN          (0x40)  /* M-Bus Interrupt Enable       */
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#define MCFMBUS_MBCR_MSTA          (0x20)  /* Master/Slave Mode Select Bit */
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#define MCFMBUS_MBCR_MTX           (0x10)  /* Transmit/Rcv Mode Select Bit */
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#define MCFMBUS_MBCR_TXAK          (0x08)  /* Transmit Acknowledge Enable  */
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#define MCFMBUS_MBCR_RSTA          (0x04)  /* Repeat Start                 */
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/*
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*	Define bit flags in Status Register
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*/
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#define MCFMBUS_MBSR_MCF           (0x80)  /* Data Transfer Complete       */
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#define MCFMBUS_MBSR_MAAS          (0x40)  /* Addressed as a Slave         */
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#define MCFMBUS_MBSR_MBB           (0x20)  /* Bus Busy                     */
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#define MCFMBUS_MBSR_MAL           (0x10)  /* Arbitration Lost             */
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#define MCFMBUS_MBSR_SRW           (0x04)  /* Slave Transmit               */
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#define MCFMBUS_MBSR_MIF           (0x02)  /* M-Bus Interrupt              */
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#define MCFMBUS_MBSR_RXAK          (0x01)  /* No Acknowledge Received      */
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/*
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*	Define bit flags in DATA I/O Register
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*/
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#define MCFMBUS_MBDR_READ          (0x01)  /* 1=read 0=write MBUS */
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#define MBUSIOCSCLOCK		1
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#define MBUSIOCGCLOCK		2
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#define MBUSIOCSADDR			3
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#define MBUSIOCGADDR			4
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#define MBUSIOCSSLADDR			5
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#define MBUSIOCGSLADDR			6
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#define MBUSIOCSSUBADDR			7
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#define MBUSIOCGSUBADDR			8
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#endif
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