133 lines
3.0 KiB
C
133 lines
3.0 KiB
C
/*
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* arch/sh/include/asm/dma-sh.h
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*
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* Copyright (C) 2000 Takashi YOSHII
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* Copyright (C) 2003 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#ifndef __DMA_SH_H
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#define __DMA_SH_H
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#include <asm/dma.h>
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#include <cpu/dma.h>
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/* DMAOR contorl: The DMAOR access size is different by CPU.*/
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#if defined(CONFIG_CPU_SUBTYPE_SH7723) || \
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defined(CONFIG_CPU_SUBTYPE_SH7724) || \
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defined(CONFIG_CPU_SUBTYPE_SH7780) || \
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defined(CONFIG_CPU_SUBTYPE_SH7785)
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#define dmaor_read_reg(n) \
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(n ? ctrl_inw(SH_DMAC_BASE1 + DMAOR) \
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: ctrl_inw(SH_DMAC_BASE0 + DMAOR))
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#define dmaor_write_reg(n, data) \
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(n ? ctrl_outw(data, SH_DMAC_BASE1 + DMAOR) \
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: ctrl_outw(data, SH_DMAC_BASE0 + DMAOR))
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#else /* Other CPU */
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#define dmaor_read_reg(n) ctrl_inw(SH_DMAC_BASE0 + DMAOR)
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#define dmaor_write_reg(n, data) ctrl_outw(data, SH_DMAC_BASE0 + DMAOR)
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#endif
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static int dmte_irq_map[] __maybe_unused = {
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#if (MAX_DMA_CHANNELS >= 4)
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DMTE0_IRQ,
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DMTE0_IRQ + 1,
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DMTE0_IRQ + 2,
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DMTE0_IRQ + 3,
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#endif
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#if (MAX_DMA_CHANNELS >= 6)
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DMTE4_IRQ,
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DMTE4_IRQ + 1,
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#endif
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#if (MAX_DMA_CHANNELS >= 8)
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DMTE6_IRQ,
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DMTE6_IRQ + 1,
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#endif
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#if (MAX_DMA_CHANNELS >= 12)
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DMTE8_IRQ,
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DMTE9_IRQ,
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DMTE10_IRQ,
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DMTE11_IRQ,
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#endif
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};
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/* Definitions for the SuperH DMAC */
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#define REQ_L 0x00000000
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#define REQ_E 0x00080000
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#define RACK_H 0x00000000
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#define RACK_L 0x00040000
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#define ACK_R 0x00000000
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#define ACK_W 0x00020000
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#define ACK_H 0x00000000
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#define ACK_L 0x00010000
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#define DM_INC 0x00004000
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#define DM_DEC 0x00008000
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#define SM_INC 0x00001000
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#define SM_DEC 0x00002000
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#define RS_IN 0x00000200
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#define RS_OUT 0x00000300
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#define TS_BLK 0x00000040
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#define TM_BUR 0x00000020
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#define CHCR_DE 0x00000001
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#define CHCR_TE 0x00000002
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#define CHCR_IE 0x00000004
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/* DMAOR definitions */
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#define DMAOR_AE 0x00000004
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#define DMAOR_NMIF 0x00000002
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#define DMAOR_DME 0x00000001
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/*
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* Define the default configuration for dual address memory-memory transfer.
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* The 0x400 value represents auto-request, external->external.
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*/
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#define RS_DUAL (DM_INC | SM_INC | 0x400 | TS_32)
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/* DMA base address */
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static u32 dma_base_addr[] __maybe_unused = {
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#if (MAX_DMA_CHANNELS >= 4)
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SH_DMAC_BASE0 + 0x00, /* channel 0 */
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SH_DMAC_BASE0 + 0x10,
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SH_DMAC_BASE0 + 0x20,
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SH_DMAC_BASE0 + 0x30,
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#endif
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#if (MAX_DMA_CHANNELS >= 6)
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SH_DMAC_BASE0 + 0x50,
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SH_DMAC_BASE0 + 0x60,
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#endif
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#if (MAX_DMA_CHANNELS >= 8)
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SH_DMAC_BASE1 + 0x00,
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SH_DMAC_BASE1 + 0x10,
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#endif
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#if (MAX_DMA_CHANNELS >= 12)
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SH_DMAC_BASE1 + 0x20,
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SH_DMAC_BASE1 + 0x30,
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SH_DMAC_BASE1 + 0x50,
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SH_DMAC_BASE1 + 0x60, /* channel 11 */
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#endif
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};
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/* DMA register */
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#define SAR 0x00
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#define DAR 0x04
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#define TCR 0x08
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#define CHCR 0x0C
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#define DMAOR 0x40
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/*
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* for dma engine
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*
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* SuperH DMA mode
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*/
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#define SHDMA_MIX_IRQ (1 << 1)
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#define SHDMA_DMAOR1 (1 << 2)
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#define SHDMA_DMAE1 (1 << 3)
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struct sh_dmae_pdata {
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unsigned int mode;
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};
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#endif /* __DMA_SH_H */
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