c6e8ee54ff
Separate ib parse checking from cffdump as it is useful in other situations. This is controlled by a new debugfs file, ib_check. All ib checking is off (0) by default, because parsing and mem_entry lookup can have a performance impact on some benchmarks. Level 1 checking verifies the IB1's. Level 2 checking also verifies the IB2.
189 lines
5.4 KiB
C
Executable File
189 lines
5.4 KiB
C
Executable File
/* Copyright (c) 2008-2012, Code Aurora Forum. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef __ADRENO_H
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#define __ADRENO_H
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#include "kgsl_device.h"
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#include "adreno_drawctxt.h"
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#include "adreno_ringbuffer.h"
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#define DEVICE_3D_NAME "kgsl-3d"
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#define DEVICE_3D0_NAME "kgsl-3d0"
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#define ADRENO_DEVICE(device) \
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KGSL_CONTAINER_OF(device, struct adreno_device, dev)
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/* Flags to control command packet settings */
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#define KGSL_CMD_FLAGS_NONE 0x00000000
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#define KGSL_CMD_FLAGS_PMODE 0x00000001
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#define KGSL_CMD_FLAGS_NO_TS_CMP 0x00000002
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#define KGSL_CMD_FLAGS_NOT_KERNEL_CMD 0x00000004
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/* Command identifiers */
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#define KGSL_CONTEXT_TO_MEM_IDENTIFIER 0x2EADBEEF
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#define KGSL_CMD_IDENTIFIER 0x2EEDFACE
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#define KGSL_START_OF_IB_IDENTIFIER 0x2EADEABE
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#define KGSL_END_OF_IB_IDENTIFIER 0x2ABEDEAD
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#ifdef CONFIG_MSM_SCM
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#define ADRENO_DEFAULT_PWRSCALE_POLICY (&kgsl_pwrscale_policy_tz)
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#else
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#define ADRENO_DEFAULT_PWRSCALE_POLICY NULL
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#endif
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#define ADRENO_ISTORE_START 0x5000 /* Istore offset */
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enum adreno_gpurev {
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ADRENO_REV_UNKNOWN = 0,
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ADRENO_REV_A200 = 200,
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ADRENO_REV_A203 = 203,
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ADRENO_REV_A205 = 205,
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ADRENO_REV_A220 = 220,
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ADRENO_REV_A225 = 225,
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ADRENO_REV_A305 = 305,
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ADRENO_REV_A320 = 320,
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};
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struct adreno_gpudev;
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struct adreno_device {
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struct kgsl_device dev; /* Must be first field in this struct */
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unsigned int chip_id;
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enum adreno_gpurev gpurev;
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struct kgsl_memregion gmemspace;
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struct adreno_context *drawctxt_active;
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const char *pfp_fwfile;
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unsigned int *pfp_fw;
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size_t pfp_fw_size;
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const char *pm4_fwfile;
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unsigned int *pm4_fw;
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size_t pm4_fw_size;
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struct adreno_ringbuffer ringbuffer;
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unsigned int mharb;
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struct adreno_gpudev *gpudev;
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unsigned int wait_timeout;
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unsigned int istore_size;
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unsigned int pix_shader_start;
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unsigned int instruction_size;
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unsigned int ib_check_level;
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};
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struct adreno_gpudev {
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/*
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* These registers are in a different location on A3XX, so define
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* them in the structure and use them as variables.
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*/
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unsigned int reg_rbbm_status;
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unsigned int reg_cp_pfp_ucode_data;
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unsigned int reg_cp_pfp_ucode_addr;
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/* GPU specific function hooks */
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int (*ctxt_create)(struct adreno_device *, struct adreno_context *);
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void (*ctxt_save)(struct adreno_device *, struct adreno_context *);
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void (*ctxt_restore)(struct adreno_device *, struct adreno_context *);
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irqreturn_t (*irq_handler)(struct adreno_device *);
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void (*irq_control)(struct adreno_device *, int);
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void (*rb_init)(struct adreno_device *, struct adreno_ringbuffer *);
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void (*start)(struct adreno_device *);
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unsigned int (*busy_cycles)(struct adreno_device *);
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};
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extern struct adreno_gpudev adreno_a2xx_gpudev;
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extern struct adreno_gpudev adreno_a3xx_gpudev;
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int adreno_idle(struct kgsl_device *device, unsigned int timeout);
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void adreno_regread(struct kgsl_device *device, unsigned int offsetwords,
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unsigned int *value);
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void adreno_regwrite(struct kgsl_device *device, unsigned int offsetwords,
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unsigned int value);
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struct kgsl_memdesc *adreno_find_region(struct kgsl_device *device,
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unsigned int pt_base,
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unsigned int gpuaddr,
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unsigned int size);
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uint8_t *adreno_convertaddr(struct kgsl_device *device,
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unsigned int pt_base, unsigned int gpuaddr, unsigned int size);
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static inline int adreno_is_a200(struct adreno_device *adreno_dev)
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{
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return (adreno_dev->gpurev == ADRENO_REV_A200);
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}
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static inline int adreno_is_a203(struct adreno_device *adreno_dev)
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{
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return (adreno_dev->gpurev == ADRENO_REV_A203);
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}
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static inline int adreno_is_a205(struct adreno_device *adreno_dev)
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{
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return (adreno_dev->gpurev == ADRENO_REV_A205);
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}
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static inline int adreno_is_a20x(struct adreno_device *adreno_dev)
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{
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return (adreno_dev->gpurev <= 209);
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}
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static inline int adreno_is_a220(struct adreno_device *adreno_dev)
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{
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return (adreno_dev->gpurev == ADRENO_REV_A220);
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}
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static inline int adreno_is_a225(struct adreno_device *adreno_dev)
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{
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return (adreno_dev->gpurev == ADRENO_REV_A225);
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}
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static inline int adreno_is_a22x(struct adreno_device *adreno_dev)
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{
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return (adreno_dev->gpurev == ADRENO_REV_A220 ||
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adreno_dev->gpurev == ADRENO_REV_A225);
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}
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static inline int adreno_is_a2xx(struct adreno_device *adreno_dev)
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{
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return (adreno_dev->gpurev <= 299);
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}
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static inline int adreno_is_a3xx(struct adreno_device *adreno_dev)
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{
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return (adreno_dev->gpurev >= 300);
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}
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/**
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* adreno_encode_istore_size - encode istore size in CP format
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* @adreno_dev - The 3D device.
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*
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* Encode the istore size into the format expected that the
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* CP_SET_SHADER_BASES and CP_ME_INIT commands:
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* bits 31:29 - istore size as encoded by this function
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* bits 27:16 - vertex shader start offset in instructions
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* bits 11:0 - pixel shader start offset in instructions.
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*/
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static inline int adreno_encode_istore_size(struct adreno_device *adreno_dev)
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{
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unsigned int size;
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/* in a225 the CP microcode multiplies the encoded
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* value by 3 while decoding.
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*/
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if (adreno_is_a225(adreno_dev))
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size = adreno_dev->istore_size/3;
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else
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size = adreno_dev->istore_size;
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return (ilog2(size) - 5) << 29;
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}
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#endif /*__ADRENO_H */
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