msm: kgsl: rework ib checking
Separate ib parse checking from cffdump as it is useful in other situations. This is controlled by a new debugfs file, ib_check. All ib checking is off (0) by default, because parsing and mem_entry lookup can have a performance impact on some benchmarks. Level 1 checking verifies the IB1's. Level 2 checking also verifies the IB2.
This commit is contained in:
securecrt
parent
d842173fc6
commit
c6e8ee54ff
@ -122,8 +122,10 @@ static struct adreno_device device_3d0 = {
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.pfp_fw = NULL,
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.pm4_fw = NULL,
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.wait_timeout = 10000, /* in milliseconds */
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.ib_check_level = 0,
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};
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/*
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* This is the master list of all GPU cores that are supported by this
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* driver.
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@ -75,6 +75,7 @@ struct adreno_device {
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unsigned int istore_size;
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unsigned int pix_shader_start;
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unsigned int instruction_size;
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unsigned int ib_check_level;
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};
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struct adreno_gpudev {
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@ -444,6 +444,8 @@ void adreno_debugfs_init(struct kgsl_device *device)
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&kgsl_cff_dump_enable_fops);
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debugfs_create_u32("wait_timeout", 0644, device->d_debugfs,
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&adreno_dev->wait_timeout);
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debugfs_create_u32("ib_check", 0644, device->d_debugfs,
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&adreno_dev->ib_check_level);
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/* Create post mortem control files */
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@ -29,11 +29,6 @@
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/* skip N 32-bit words to get to the next packet */
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#define CP_NOP 0x10
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/* indirect buffer dispatch. prefetch parser uses this packet type to determine
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* whether to pre-fetch the IB
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*/
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#define CP_INDIRECT_BUFFER 0x3f
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/* indirect buffer dispatch. same as IB, but init is pipelined */
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#define CP_INDIRECT_BUFFER_PFD 0x37
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@ -117,6 +112,9 @@
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/* load constants from a location in memory */
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#define CP_LOAD_CONSTANT_CONTEXT 0x2e
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/* (A2x) sets binning configuration registers */
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#define CP_SET_BIN_DATA 0x2f
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/* selective invalidation of state pointers */
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#define CP_INVALIDATE_STATE 0x3b
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@ -197,11 +195,20 @@
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#define cp_nop_packet(cnt) \
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(CP_TYPE3_PKT | (((cnt)-1) << 16) | (CP_NOP << 8))
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#define pkt_is_type0(pkt) (((pkt) & 0XC0000000) == CP_TYPE0_PKT)
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#define type0_pkt_size(pkt) ((((pkt) >> 16) & 0x3FFF) + 1)
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#define type0_pkt_offset(pkt) ((pkt) & 0x7FFF)
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#define pkt_is_type3(pkt) (((pkt) & 0xC0000000) == CP_TYPE3_PKT)
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#define cp_type3_opcode(pkt) (((pkt) >> 8) & 0xFF)
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#define type3_pkt_size(pkt) ((((pkt) >> 16) & 0x3FFF) + 1)
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/* packet headers */
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#define CP_HDR_ME_INIT cp_type3_packet(CP_ME_INIT, 18)
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#define CP_HDR_INDIRECT_BUFFER_PFD cp_type3_packet(CP_INDIRECT_BUFFER_PFD, 2)
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#define CP_HDR_INDIRECT_BUFFER cp_type3_packet(CP_INDIRECT_BUFFER, 2)
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#define CP_HDR_INDIRECT_BUFFER_PFE cp_type3_packet(CP_INDIRECT_BUFFER_PFE, 2)
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/* dword base address of the GFX decode space */
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#define SUBBLOCK_OFFSET(reg) ((unsigned int)((reg) - (0x2000)))
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@ -52,7 +52,7 @@ static const struct pm_id_name pm3_types[] = {
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{CP_IM_LOAD, "IN__LOAD"},
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{CP_IM_LOAD_IMMEDIATE, "IM_LOADI"},
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{CP_IM_STORE, "IM_STORE"},
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{CP_INDIRECT_BUFFER, "IND_BUF_"},
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{CP_INDIRECT_BUFFER_PFE, "IND_BUF_"},
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{CP_INDIRECT_BUFFER_PFD, "IND_BUFP"},
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{CP_INTERRUPT, "PM4_INTR"},
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{CP_INVALIDATE_STATE, "INV_STAT"},
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@ -22,6 +22,7 @@
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#include "adreno.h"
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#include "adreno_pm4types.h"
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#include "adreno_ringbuffer.h"
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#include "adreno_debugfs.h"
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#include "a2xx_reg.h"
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#include "a3xx_reg.h"
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@ -550,6 +551,198 @@ adreno_ringbuffer_issuecmds(struct kgsl_device *device,
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adreno_ringbuffer_addcmds(rb, flags, cmds, sizedwords);
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}
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static bool _parse_ibs(struct kgsl_device_private *dev_priv, uint gpuaddr,
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int sizedwords);
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static bool
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_handle_type3(struct kgsl_device_private *dev_priv, uint *hostaddr)
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{
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unsigned int opcode = cp_type3_opcode(*hostaddr);
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switch (opcode) {
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case CP_INDIRECT_BUFFER_PFD:
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case CP_INDIRECT_BUFFER_PFE:
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case CP_COND_INDIRECT_BUFFER_PFE:
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case CP_COND_INDIRECT_BUFFER_PFD:
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return _parse_ibs(dev_priv, hostaddr[1], hostaddr[2]);
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case CP_NOP:
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case CP_WAIT_FOR_IDLE:
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case CP_WAIT_REG_MEM:
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case CP_WAIT_REG_EQ:
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case CP_WAT_REG_GTE:
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case CP_WAIT_UNTIL_READ:
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case CP_WAIT_IB_PFD_COMPLETE:
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case CP_REG_RMW:
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case CP_REG_TO_MEM:
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case CP_MEM_WRITE:
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case CP_MEM_WRITE_CNTR:
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case CP_COND_EXEC:
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case CP_COND_WRITE:
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case CP_EVENT_WRITE:
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case CP_EVENT_WRITE_SHD:
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case CP_EVENT_WRITE_CFL:
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case CP_EVENT_WRITE_ZPD:
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case CP_DRAW_INDX:
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case CP_DRAW_INDX_2:
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case CP_DRAW_INDX_BIN:
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case CP_DRAW_INDX_2_BIN:
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case CP_VIZ_QUERY:
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case CP_SET_STATE:
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case CP_SET_CONSTANT:
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case CP_IM_LOAD:
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case CP_IM_LOAD_IMMEDIATE:
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case CP_LOAD_CONSTANT_CONTEXT:
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case CP_INVALIDATE_STATE:
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case CP_SET_SHADER_BASES:
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case CP_SET_BIN_MASK:
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case CP_SET_BIN_SELECT:
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case CP_SET_BIN_BASE_OFFSET:
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case CP_SET_BIN_DATA:
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case CP_CONTEXT_UPDATE:
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case CP_INTERRUPT:
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case CP_IM_STORE:
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case CP_LOAD_STATE:
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break;
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/* these shouldn't come from userspace */
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case CP_ME_INIT:
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case CP_SET_PROTECTED_MODE:
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default:
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KGSL_CMD_ERR(dev_priv->device, "bad CP opcode %0x\n", opcode);
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return false;
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break;
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}
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return true;
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}
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static bool
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_handle_type0(struct kgsl_device_private *dev_priv, uint *hostaddr)
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{
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unsigned int reg = type0_pkt_offset(*hostaddr);
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unsigned int cnt = type0_pkt_size(*hostaddr);
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if (reg < 0x0192 || (reg + cnt) >= 0x8000) {
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KGSL_CMD_ERR(dev_priv->device, "bad type0 reg: 0x%0x cnt: %d\n",
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reg, cnt);
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return false;
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}
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return true;
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}
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/*
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* Traverse IBs and dump them to test vector. Detect swap by inspecting
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* register writes, keeping note of the current state, and dump
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* framebuffer config to test vector
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*/
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static bool _parse_ibs(struct kgsl_device_private *dev_priv,
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uint gpuaddr, int sizedwords)
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{
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static uint level; /* recursion level */
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bool ret = false;
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uint *hostaddr, *hoststart;
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int dwords_left = sizedwords; /* dwords left in the current command
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buffer */
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struct kgsl_mem_entry *entry;
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spin_lock(&dev_priv->process_priv->mem_lock);
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entry = kgsl_sharedmem_find_region(dev_priv->process_priv,
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gpuaddr, sizedwords * sizeof(uint));
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spin_unlock(&dev_priv->process_priv->mem_lock);
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if (entry == NULL) {
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KGSL_CMD_ERR(dev_priv->device,
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"no mapping for gpuaddr: 0x%08x\n", gpuaddr);
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return false;
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}
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hostaddr = (uint *)kgsl_gpuaddr_to_vaddr(&entry->memdesc, gpuaddr);
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if (hostaddr == NULL) {
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KGSL_CMD_ERR(dev_priv->device,
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"no mapping for gpuaddr: 0x%08x\n", gpuaddr);
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return false;
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}
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hoststart = hostaddr;
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level++;
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KGSL_CMD_INFO(dev_priv->device, "ib: gpuaddr:0x%08x, wc:%d, hptr:%p\n",
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gpuaddr, sizedwords, hostaddr);
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mb();
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while (dwords_left > 0) {
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bool cur_ret = true;
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int count = 0; /* dword count including packet header */
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switch (*hostaddr >> 30) {
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case 0x0: /* type-0 */
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count = (*hostaddr >> 16)+2;
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cur_ret = _handle_type0(dev_priv, hostaddr);
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break;
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case 0x1: /* type-1 */
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count = 2;
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break;
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case 0x3: /* type-3 */
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count = ((*hostaddr >> 16) & 0x3fff) + 2;
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cur_ret = _handle_type3(dev_priv, hostaddr);
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break;
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default:
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KGSL_CMD_ERR(dev_priv->device, "unexpected type: "
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"type:%d, word:0x%08x @ 0x%p, gpu:0x%08x\n",
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*hostaddr >> 30, *hostaddr, hostaddr,
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gpuaddr+4*(sizedwords-dwords_left));
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cur_ret = false;
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count = dwords_left;
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break;
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}
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if (!cur_ret) {
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KGSL_CMD_ERR(dev_priv->device,
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"bad sub-type: #:%d/%d, v:0x%08x"
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" @ 0x%p[gb:0x%08x], level:%d\n",
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sizedwords-dwords_left, sizedwords, *hostaddr,
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hostaddr, gpuaddr+4*(sizedwords-dwords_left),
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level);
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if (ADRENO_DEVICE(dev_priv->device)->ib_check_level
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>= 2)
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print_hex_dump(KERN_ERR,
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level == 1 ? "IB1:" : "IB2:",
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DUMP_PREFIX_OFFSET, 32, 4, hoststart,
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sizedwords*4, 0);
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goto done;
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}
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/* jump to next packet */
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dwords_left -= count;
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hostaddr += count;
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if (dwords_left < 0) {
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KGSL_CMD_ERR(dev_priv->device,
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"bad count: c:%d, #:%d/%d, "
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"v:0x%08x @ 0x%p[gb:0x%08x], level:%d\n",
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count, sizedwords-(dwords_left+count),
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sizedwords, *(hostaddr-count), hostaddr-count,
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gpuaddr+4*(sizedwords-(dwords_left+count)),
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level);
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if (ADRENO_DEVICE(dev_priv->device)->ib_check_level
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>= 2)
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print_hex_dump(KERN_ERR,
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level == 1 ? "IB1:" : "IB2:",
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DUMP_PREFIX_OFFSET, 32, 4, hoststart,
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sizedwords*4, 0);
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goto done;
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}
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}
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ret = true;
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done:
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if (!ret)
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KGSL_DRV_ERR(dev_priv->device,
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"parsing failed: gpuaddr:0x%08x, "
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"host:0x%p, wc:%d\n", gpuaddr, hoststart, sizedwords);
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level--;
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return ret;
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}
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int
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adreno_ringbuffer_issueibcmds(struct kgsl_device_private *dev_priv,
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struct kgsl_context *context,
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@ -608,9 +801,12 @@ adreno_ringbuffer_issueibcmds(struct kgsl_device_private *dev_priv,
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*cmds++ = ibdesc[0].sizedwords;
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}
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for (i = start_index; i < numibs; i++) {
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(void)kgsl_cffdump_parse_ibs(dev_priv, NULL,
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ibdesc[i].gpuaddr, ibdesc[i].sizedwords, false);
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if (unlikely(adreno_dev->ib_check_level >= 1 &&
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!_parse_ibs(dev_priv, ibdesc[i].gpuaddr,
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ibdesc[i].sizedwords))) {
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kfree(link);
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return -EINVAL;
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}
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*cmds++ = CP_HDR_INDIRECT_BUFFER_PFD;
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*cmds++ = ibdesc[i].gpuaddr;
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*cmds++ = ibdesc[i].sizedwords;
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@ -660,7 +856,6 @@ int adreno_ringbuffer_extract(struct adreno_ringbuffer *rb,
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unsigned int val3;
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unsigned int copy_rb_contents = 0;
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unsigned int cur_context;
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unsigned int j;
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GSL_RB_GET_READPTR(rb, &rb->rptr);
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@ -811,19 +1006,6 @@ int adreno_ringbuffer_extract(struct adreno_ringbuffer *rb,
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}
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*rb_size = temp_idx;
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KGSL_DRV_ERR(device, "Extracted rb contents, size: %x\n", *rb_size);
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for (temp_idx = 0; temp_idx < *rb_size;) {
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char str[80];
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int idx = 0;
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if ((temp_idx + 8) <= *rb_size)
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j = 8;
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else
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j = *rb_size - temp_idx;
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for (; j != 0; j--)
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idx += scnprintf(str + idx, 80 - idx,
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"%8.8X ", temp_rb_buffer[temp_idx++]);
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printk(KERN_ALERT "%s", str);
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}
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return 0;
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}
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@ -909,40 +909,6 @@ static long kgsl_ioctl_device_waittimestamp(struct kgsl_device_private
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return result;
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}
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static bool check_ibdesc(struct kgsl_device_private *dev_priv,
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struct kgsl_ibdesc *ibdesc, unsigned int numibs,
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bool parse)
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{
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bool result = true;
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unsigned int i;
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for (i = 0; i < numibs; i++) {
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struct kgsl_mem_entry *entry;
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spin_lock(&dev_priv->process_priv->mem_lock);
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entry = kgsl_sharedmem_find_region(dev_priv->process_priv,
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ibdesc[i].gpuaddr, ibdesc[i].sizedwords * sizeof(uint));
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spin_unlock(&dev_priv->process_priv->mem_lock);
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if (entry == NULL) {
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KGSL_DRV_ERR(dev_priv->device,
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"invalid cmd buffer gpuaddr %08x " \
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"sizedwords %d\n", ibdesc[i].gpuaddr,
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ibdesc[i].sizedwords);
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result = false;
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break;
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}
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if (parse && !kgsl_cffdump_parse_ibs(dev_priv, &entry->memdesc,
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ibdesc[i].gpuaddr, ibdesc[i].sizedwords, true)) {
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KGSL_DRV_ERR(dev_priv->device,
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"invalid cmd buffer gpuaddr %08x " \
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"sizedwords %d numibs %d/%d\n",
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ibdesc[i].gpuaddr,
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ibdesc[i].sizedwords, i+1, numibs);
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result = false;
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break;
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}
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}
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return result;
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}
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static long kgsl_ioctl_rb_issueibcmds(struct kgsl_device_private *dev_priv,
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unsigned int cmd, void *data)
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@ -1012,12 +978,6 @@ static long kgsl_ioctl_rb_issueibcmds(struct kgsl_device_private *dev_priv,
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param->numibs = 1;
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}
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if (!check_ibdesc(dev_priv, ibdesc, param->numibs, true)) {
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KGSL_DRV_ERR(dev_priv->device, "bad ibdesc");
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result = -EINVAL;
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goto free_ibdesc;
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}
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result = dev_priv->device->ftbl->issueibcmds(dev_priv,
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context,
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ibdesc,
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@ -1025,17 +985,6 @@ static long kgsl_ioctl_rb_issueibcmds(struct kgsl_device_private *dev_priv,
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¶m->timestamp,
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param->flags);
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if (result != 0)
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goto free_ibdesc;
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/* this is a check to try to detect if a command buffer was freed
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* during issueibcmds().
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*/
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if (!check_ibdesc(dev_priv, ibdesc, param->numibs, false)) {
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KGSL_DRV_ERR(dev_priv->device, "bad ibdesc AFTER issue");
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result = -EINVAL;
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goto free_ibdesc;
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}
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free_ibdesc:
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kfree(ibdesc);
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@ -497,195 +497,6 @@ int kgsl_cffdump_waitirq(void)
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}
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EXPORT_SYMBOL(kgsl_cffdump_waitirq);
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#define ADDRESS_STACK_SIZE 256
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#define GET_PM4_TYPE3_OPCODE(x) ((*(x) >> 8) & 0xFF)
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static unsigned int kgsl_cffdump_addr_count;
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static bool kgsl_cffdump_handle_type3(struct kgsl_device_private *dev_priv,
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uint *hostaddr, bool check_only)
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{
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static uint addr_stack[ADDRESS_STACK_SIZE];
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static uint size_stack[ADDRESS_STACK_SIZE];
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switch (GET_PM4_TYPE3_OPCODE(hostaddr)) {
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case CP_INDIRECT_BUFFER_PFD:
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case CP_INDIRECT_BUFFER:
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{
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/* traverse indirect buffers */
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int i;
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uint ibaddr = hostaddr[1];
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uint ibsize = hostaddr[2];
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/* is this address already in encountered? */
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for (i = 0;
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i < kgsl_cffdump_addr_count && addr_stack[i] != ibaddr;
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++i)
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;
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if (kgsl_cffdump_addr_count == i) {
|
||||
addr_stack[kgsl_cffdump_addr_count] = ibaddr;
|
||||
size_stack[kgsl_cffdump_addr_count++] = ibsize;
|
||||
|
||||
if (kgsl_cffdump_addr_count >= ADDRESS_STACK_SIZE) {
|
||||
KGSL_CORE_ERR("stack overflow\n");
|
||||
return false;
|
||||
}
|
||||
|
||||
return kgsl_cffdump_parse_ibs(dev_priv, NULL,
|
||||
ibaddr, ibsize, check_only);
|
||||
} else if (size_stack[i] != ibsize) {
|
||||
KGSL_CORE_ERR("gpuaddr: 0x%08x, "
|
||||
"wc: %u, with size wc: %u already on the "
|
||||
"stack\n", ibaddr, ibsize, size_stack[i]);
|
||||
return false;
|
||||
}
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
/*
|
||||
* Traverse IBs and dump them to test vector. Detect swap by inspecting
|
||||
* register writes, keeping note of the current state, and dump
|
||||
* framebuffer config to test vector
|
||||
*/
|
||||
bool kgsl_cffdump_parse_ibs(struct kgsl_device_private *dev_priv,
|
||||
const struct kgsl_memdesc *memdesc, uint gpuaddr, int sizedwords,
|
||||
bool check_only)
|
||||
{
|
||||
static uint level; /* recursion level */
|
||||
bool ret = true;
|
||||
uint *hostaddr, *hoststart;
|
||||
int dwords_left = sizedwords; /* dwords left in the current command
|
||||
buffer */
|
||||
|
||||
if (level == 0)
|
||||
kgsl_cffdump_addr_count = 0;
|
||||
|
||||
if (memdesc == NULL) {
|
||||
struct kgsl_mem_entry *entry;
|
||||
spin_lock(&dev_priv->process_priv->mem_lock);
|
||||
entry = kgsl_sharedmem_find_region(dev_priv->process_priv,
|
||||
gpuaddr, sizedwords * sizeof(uint));
|
||||
spin_unlock(&dev_priv->process_priv->mem_lock);
|
||||
if (entry == NULL) {
|
||||
KGSL_CORE_ERR("did not find mapping "
|
||||
"for gpuaddr: 0x%08x\n", gpuaddr);
|
||||
return true;
|
||||
}
|
||||
memdesc = &entry->memdesc;
|
||||
}
|
||||
hostaddr = (uint *)kgsl_gpuaddr_to_vaddr(memdesc, gpuaddr);
|
||||
if (hostaddr == NULL) {
|
||||
KGSL_CORE_ERR("no kernel mapping for "
|
||||
"gpuaddr: 0x%08x\n", gpuaddr);
|
||||
return true;
|
||||
}
|
||||
|
||||
hoststart = hostaddr;
|
||||
|
||||
level++;
|
||||
|
||||
if (!memdesc->physaddr) {
|
||||
KGSL_CORE_ERR("no physaddr");
|
||||
} else {
|
||||
mb();
|
||||
kgsl_cache_range_op((struct kgsl_memdesc *)memdesc,
|
||||
KGSL_CACHE_OP_INV);
|
||||
}
|
||||
|
||||
#ifdef DEBUG
|
||||
pr_info("kgsl: cffdump: ib: gpuaddr:0x%08x, wc:%d, hptr:%p\n",
|
||||
gpuaddr, sizedwords, hostaddr);
|
||||
#endif
|
||||
|
||||
while (dwords_left > 0) {
|
||||
int count = 0; /* dword count including packet header */
|
||||
bool cur_ret = true;
|
||||
|
||||
switch (*hostaddr >> 30) {
|
||||
case 0x0: /* type-0 */
|
||||
count = (*hostaddr >> 16)+2;
|
||||
break;
|
||||
case 0x1: /* type-1 */
|
||||
count = 2;
|
||||
break;
|
||||
case 0x3: /* type-3 */
|
||||
count = ((*hostaddr >> 16) & 0x3fff) + 2;
|
||||
cur_ret = kgsl_cffdump_handle_type3(dev_priv,
|
||||
hostaddr, check_only);
|
||||
break;
|
||||
default:
|
||||
pr_warn("kgsl: cffdump: parse-ib: unexpected type: "
|
||||
"type:%d, word:0x%08x @ 0x%p, gpu:0x%08x\n",
|
||||
*hostaddr >> 30, *hostaddr, hostaddr,
|
||||
gpuaddr+4*(sizedwords-dwords_left));
|
||||
cur_ret = false;
|
||||
count = dwords_left;
|
||||
break;
|
||||
}
|
||||
|
||||
#ifdef DEBUG
|
||||
if (!cur_ret) {
|
||||
pr_info("kgsl: cffdump: bad sub-type: #:%d/%d, v:0x%08x"
|
||||
" @ 0x%p[gb:0x%08x], level:%d\n",
|
||||
sizedwords-dwords_left, sizedwords, *hostaddr,
|
||||
hostaddr, gpuaddr+4*(sizedwords-dwords_left),
|
||||
level);
|
||||
|
||||
print_hex_dump(KERN_ERR, level == 1 ? "IB1:" : "IB2:",
|
||||
DUMP_PREFIX_OFFSET, 32, 4, hoststart,
|
||||
sizedwords*4, 0);
|
||||
}
|
||||
#endif
|
||||
ret = ret && cur_ret;
|
||||
|
||||
/* jump to next packet */
|
||||
dwords_left -= count;
|
||||
hostaddr += count;
|
||||
cur_ret = dwords_left >= 0;
|
||||
|
||||
#ifdef DEBUG
|
||||
if (!cur_ret) {
|
||||
pr_info("kgsl: cffdump: bad count: c:%d, #:%d/%d, "
|
||||
"v:0x%08x @ 0x%p[gb:0x%08x], level:%d\n",
|
||||
count, sizedwords-(dwords_left+count),
|
||||
sizedwords, *(hostaddr-count), hostaddr-count,
|
||||
gpuaddr+4*(sizedwords-(dwords_left+count)),
|
||||
level);
|
||||
|
||||
print_hex_dump(KERN_ERR, level == 1 ? "IB1:" : "IB2:",
|
||||
DUMP_PREFIX_OFFSET, 32, 4, hoststart,
|
||||
sizedwords*4, 0);
|
||||
}
|
||||
#endif
|
||||
|
||||
ret = ret && cur_ret;
|
||||
}
|
||||
|
||||
if (!ret)
|
||||
pr_info("kgsl: cffdump: parsing failed: gpuaddr:0x%08x, "
|
||||
"host:0x%p, wc:%d\n", gpuaddr, hoststart, sizedwords);
|
||||
|
||||
if (!check_only) {
|
||||
#ifdef DEBUG
|
||||
uint offset = gpuaddr - memdesc->gpuaddr;
|
||||
pr_info("kgsl: cffdump: ib-dump: hostptr:%p, gpuaddr:%08x, "
|
||||
"physaddr:%08x, offset:%d, size:%d", hoststart,
|
||||
gpuaddr, memdesc->physaddr + offset, offset,
|
||||
sizedwords*4);
|
||||
#endif
|
||||
kgsl_cffdump_syncmem(dev_priv, memdesc, gpuaddr, sizedwords*4,
|
||||
false);
|
||||
}
|
||||
|
||||
level--;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int subbuf_start_handler(struct rchan_buf *buf,
|
||||
void *subbuf, void *prev_subbuf, uint prev_padding)
|
||||
{
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user