mirror of
https://github.com/xcat2/xNBA.git
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349 lines
9.2 KiB
C
349 lines
9.2 KiB
C
#include "stdint.h"
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#include "string.h"
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#include "console.h"
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#include "pci.h"
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/*
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* Ensure that there is sufficient space in the shared dev_bus
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* structure for a struct pci_device.
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*
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*/
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DEV_BUS( struct pci_device, pci_dev );
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static char pci_magic[0]; /* guaranteed unique symbol */
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/*
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* pci_io.c may know how many buses we have, in which case it can
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* overwrite this value.
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*
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*/
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unsigned int pci_max_bus = 0xff;
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/*
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* Fill in parameters (vendor & device ids, class, membase etc.) for a
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* PCI device based on bus & devfn.
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*
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* Returns 1 if a device was found, 0 for no device present.
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*/
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static int fill_pci_device ( struct pci_device *pci ) {
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static struct {
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uint16_t devfn0;
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int is_present;
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} cache = { 0, 1 };
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uint32_t l;
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int reg;
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/* Check bus is within range */
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if ( PCI_BUS ( pci->busdevfn ) > pci_max_bus ) {
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return 0;
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}
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/* Check to see if we've cached the result that this is a
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* non-zero function on a non-existent card. This is done to
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* increase scan speed by a factor of 8.
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*/
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if ( ( PCI_FUNC ( pci->busdevfn ) != 0 ) &&
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( PCI_FN0 ( pci->busdevfn ) == cache.devfn0 ) &&
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( ! cache.is_present ) ) {
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return 0;
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}
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/* Check to see if there's anything physically present.
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*/
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pci_read_config_dword ( pci, PCI_VENDOR_ID, &l );
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/* some broken boards return 0 if a slot is empty: */
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if ( ( l == 0xffffffff ) || ( l == 0x00000000 ) ) {
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if ( PCI_FUNC ( pci->busdevfn ) == 0 ) {
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/* Don't look for subsequent functions if the
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* card itself is not present.
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*/
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cache.devfn0 = pci->busdevfn;
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cache.is_present = 0;
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}
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return 0;
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}
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pci->vendor = l & 0xffff;
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pci->dev_id = ( l >> 16 ) & 0xffff;
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/* Check that we're not a duplicate function on a
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* non-multifunction device.
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*/
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if ( PCI_FUNC ( pci->busdevfn ) != 0 ) {
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uint16_t save_busdevfn = pci->busdevfn;
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uint8_t header_type;
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pci->busdevfn &= PCI_FN0 ( pci->busdevfn );
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pci_read_config_byte ( pci, PCI_HEADER_TYPE, &header_type );
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pci->busdevfn = save_busdevfn;
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if ( ! ( header_type & 0x80 ) ) {
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return 0;
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}
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}
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/* Get device class */
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pci_read_config_word ( pci, PCI_SUBCLASS_CODE, &pci->class );
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/* Get revision */
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pci_read_config_byte ( pci, PCI_REVISION, &pci->revision );
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/* Get the "membase" */
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pci_read_config_dword ( pci, PCI_BASE_ADDRESS_1, &pci->membase );
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/* Get the "ioaddr" */
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pci->ioaddr = 0;
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for ( reg = PCI_BASE_ADDRESS_0; reg <= PCI_BASE_ADDRESS_5; reg += 4 ) {
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pci_read_config_dword ( pci, reg, &pci->ioaddr );
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if ( pci->ioaddr & PCI_BASE_ADDRESS_SPACE_IO ) {
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pci->ioaddr &= PCI_BASE_ADDRESS_IO_MASK;
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if ( pci->ioaddr ) {
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break;
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}
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}
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pci->ioaddr = 0;
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}
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/* Get the irq */
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pci_read_config_byte ( pci, PCI_INTERRUPT_PIN, &pci->irq );
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if ( pci->irq ) {
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pci_read_config_byte ( pci, PCI_INTERRUPT_LINE, &pci->irq );
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}
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DBG ( "PCI found device %hhx:%hhx.%d Class %hx: %hx:%hx (rev %hhx)\n",
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PCI_BUS ( pci->busdevfn ), PCI_DEV ( pci->busdevfn ),
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PCI_FUNC ( pci->busdevfn ), pci->class, pci->vendor, pci->dev_id,
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pci->revision );
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return 1;
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}
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/*
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* Set device to be a busmaster in case BIOS neglected to do so. Also
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* adjust PCI latency timer to a reasonable value, 32.
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*/
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void adjust_pci_device ( struct pci_device *pci ) {
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unsigned short new_command, pci_command;
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unsigned char pci_latency;
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pci_read_config_word ( pci, PCI_COMMAND, &pci_command );
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new_command = pci_command | PCI_COMMAND_MASTER | PCI_COMMAND_IO;
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if ( pci_command != new_command ) {
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DBG ( "PCI BIOS has not enabled device %hhx:%hhx.%d! "
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"Updating PCI command %hX->%hX\n",
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PCI_BUS ( pci->busdevfn ), PCI_DEV ( pci->busdevfn ),
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PCI_FUNC ( pci->busdevfn ), pci_command, new_command );
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pci_write_config_word ( pci, PCI_COMMAND, new_command );
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}
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pci_read_config_byte ( pci, PCI_LATENCY_TIMER, &pci_latency);
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if ( pci_latency < 32 ) {
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DBG ( "PCI device %hhx:%hhx.%d latency timer is "
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"unreasonably low at %d. Setting to 32.\n",
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PCI_BUS ( pci->busdevfn ), PCI_DEV ( pci->busdevfn ),
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PCI_FUNC ( pci->busdevfn ), pci_latency );
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pci_write_config_byte ( pci, PCI_LATENCY_TIMER, 32);
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}
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}
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/*
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* Set PCI device to use.
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*
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* This routine can be called by e.g. the ROM prefix to specify that
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* the first device to be tried should be the device on which the ROM
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* was physically located.
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*
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*/
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void set_pci_device ( uint16_t busdevfn ) {
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pci_dev.magic = pci_magic;
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pci_dev.busdevfn = busdevfn;
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pci_dev.already_tried = 0;
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}
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/*
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* Find a PCI device matching the specified driver
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*
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*/
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int find_pci_device ( struct pci_device *pci,
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struct pci_driver *driver ) {
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int i;
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/* Initialise struct pci if it's the first time it's been used. */
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if ( pci->magic != pci_magic ) {
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memset ( pci, 0, sizeof ( *pci ) );
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pci->magic = pci_magic;
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}
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/* Iterate through all possible PCI bus:dev.fn combinations,
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* starting where we left off.
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*/
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DBG ( "PCI searching for device matching driver %s\n", driver->name );
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do {
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/* If we've already used this device, skip it */
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if ( pci->already_tried ) {
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pci->already_tried = 0;
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continue;
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}
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/* Fill in device parameters, if device present */
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if ( ! fill_pci_device ( pci ) ) {
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continue;
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}
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/* If driver has a class, and class matches, use it */
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if ( driver->class &&
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( driver->class == pci->class ) ) {
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DBG ( "PCI found class %hx matching driver %s\n",
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driver->class, driver->name );
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pci->name = driver->name;
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pci->already_tried = 1;
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return 1;
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}
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/* If any of driver's IDs match, use it */
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for ( i = 0 ; i < driver->id_count; i++ ) {
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struct pci_id *id = &driver->ids[i];
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if ( ( pci->vendor == id->vendor ) &&
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( pci->dev_id == id->dev_id ) ) {
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DBG ( "PCI found ID %hx:%hx (device %s) "
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"matching driver %s\n", id->vendor,
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id->dev_id, id->name, driver->name );
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pci->name = id->name;
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pci->already_tried = 1;
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return 1;
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}
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}
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} while ( ++pci->busdevfn );
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/* No device found */
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DBG ( "PCI found no device matching driver %s\n", driver->name );
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return 0;
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}
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/*
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* Find the next PCI device that can be used to boot using the
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* specified driver.
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*
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*/
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int find_pci_boot_device ( struct dev *dev, struct pci_driver *driver ) {
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struct pci_device *pci = ( struct pci_device * )dev->bus;
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if ( ! find_pci_device ( pci, driver ) )
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return 0;
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dev->name = pci->name;
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dev->devid.bus_type = PCI_BUS_TYPE;
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dev->devid.vendor_id = pci->vendor;
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dev->devid.device_id = pci->dev_id;
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return 1;
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}
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/*
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* Find the start of a pci resource.
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*/
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unsigned long pci_bar_start ( struct pci_device *pci, unsigned int index ) {
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uint32_t lo, hi;
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unsigned long bar;
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pci_read_config_dword ( pci, index, &lo );
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if ( lo & PCI_BASE_ADDRESS_SPACE_IO ) {
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bar = lo & PCI_BASE_ADDRESS_IO_MASK;
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} else {
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bar = 0;
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if ( ( lo & PCI_BASE_ADDRESS_MEM_TYPE_MASK ) ==
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PCI_BASE_ADDRESS_MEM_TYPE_64) {
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pci_read_config_dword ( pci, index + 4, &hi );
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if ( hi ) {
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#if ULONG_MAX > 0xffffffff
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bar = hi;
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bar <<= 32;
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#else
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printf ( "Unhandled 64bit BAR\n" );
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return -1UL;
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#endif
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}
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}
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bar |= lo & PCI_BASE_ADDRESS_MEM_MASK;
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}
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return bar + pci_bus_base ( pci );
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}
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/*
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* Find the size of a pci resource.
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*/
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unsigned long pci_bar_size ( struct pci_device *pci, unsigned int bar ) {
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uint32_t start, size;
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/* Save the original bar */
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pci_read_config_dword ( pci, bar, &start );
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/* Compute which bits can be set */
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pci_write_config_dword ( pci, bar, ~0 );
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pci_read_config_dword ( pci, bar, &size );
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/* Restore the original size */
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pci_write_config_dword ( pci, bar, start );
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/* Find the significant bits */
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if ( start & PCI_BASE_ADDRESS_SPACE_IO ) {
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size &= PCI_BASE_ADDRESS_IO_MASK;
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} else {
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size &= PCI_BASE_ADDRESS_MEM_MASK;
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}
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/* Find the lowest bit set */
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size = size & ~( size - 1 );
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return size;
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}
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/**
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* pci_find_capability - query for devices' capabilities
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* @pci: PCI device to query
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* @cap: capability code
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*
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* Tell if a device supports a given PCI capability.
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* Returns the address of the requested capability structure within the
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* device's PCI configuration space or 0 in case the device does not
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* support it. Possible values for @cap:
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*
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* %PCI_CAP_ID_PM Power Management
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*
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* %PCI_CAP_ID_AGP Accelerated Graphics Port
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*
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* %PCI_CAP_ID_VPD Vital Product Data
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*
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* %PCI_CAP_ID_SLOTID Slot Identification
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*
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* %PCI_CAP_ID_MSI Message Signalled Interrupts
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*
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* %PCI_CAP_ID_CHSWP CompactPCI HotSwap
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*/
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int pci_find_capability ( struct pci_device *pci, int cap ) {
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uint16_t status;
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uint8_t pos, id;
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uint8_t hdr_type;
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int ttl = 48;
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pci_read_config_word ( pci, PCI_STATUS, &status );
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if ( ! ( status & PCI_STATUS_CAP_LIST ) )
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return 0;
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pci_read_config_byte ( pci, PCI_HEADER_TYPE, &hdr_type );
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switch ( hdr_type & 0x7F ) {
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case PCI_HEADER_TYPE_NORMAL:
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case PCI_HEADER_TYPE_BRIDGE:
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default:
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pci_read_config_byte ( pci, PCI_CAPABILITY_LIST, &pos );
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break;
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case PCI_HEADER_TYPE_CARDBUS:
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pci_read_config_byte ( pci, PCI_CB_CAPABILITY_LIST, &pos );
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break;
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}
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while ( ttl-- && pos >= 0x40 ) {
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pos &= ~3;
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pci_read_config_byte ( pci, pos + PCI_CAP_LIST_ID, &id );
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DBG ( "Capability: %d\n", id );
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if ( id == 0xff )
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break;
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if ( id == cap )
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return pos;
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pci_read_config_byte ( pci, pos + PCI_CAP_LIST_NEXT, &pos );
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}
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return 0;
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}
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