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434 lines
18 KiB
C
434 lines
18 KiB
C
/*------------------------------------------------------------------------
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* smc9000.h
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*
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* Copyright (C) 1998 by Daniel Engström
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* Copyright (C) 1996 by Erik Stahlman
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*
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* This software may be used and distributed according to the terms
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* of the GNU Public License, incorporated herein by reference.
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*
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* This file contains register information and access macros for
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* the SMC91xxx chipset.
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*
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* Information contained in this file was obtained from the SMC91C94
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* manual from SMC. To get a copy, if you really want one, you can find
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* information under www.smsc.com in the components division.
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* ( this thanks to advice from Donald Becker ).
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*
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* Authors
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* Daniel Engström <daniel.engstrom@riksnett.no>
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* Erik Stahlman <erik@vt.edu>
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*
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* History
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* 96-01-06 Erik Stahlman moved definitions here from main .c
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* file
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* 96-01-19 Erik Stahlman polished this up some, and added
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* better error handling
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* 98-09-25 Daniel Engström adjusted for Etherboot
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* 98-09-27 Daniel Engström moved some static strings back to the
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* main .c file
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* --------------------------------------------------------------------------*/
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#ifndef _SMC9000_H_
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# define _SMC9000_H_
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/* I want some simple types */
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typedef unsigned char byte;
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typedef unsigned short word;
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typedef unsigned long int dword;
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/*---------------------------------------------------------------
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*
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* A description of the SMC registers is probably in order here,
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* although for details, the SMC datasheet is invaluable.
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*
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* Basically, the chip has 4 banks of registers ( 0 to 3 ), which
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* are accessed by writing a number into the BANK_SELECT register
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* ( I also use a SMC_SELECT_BANK macro for this ).
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*
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* The banks are configured so that for most purposes, bank 2 is all
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* that is needed for simple run time tasks.
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* ----------------------------------------------------------------------*/
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/*
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* Bank Select Register:
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*
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* yyyy yyyy 0000 00xx
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* xx = bank number
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* yyyy yyyy = 0x33, for identification purposes.
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*/
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#define BANK_SELECT 14
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/* BANK 0 */
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#define TCR 0 /* transmit control register */
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#define TCR_ENABLE 0x0001 /* if this is 1, we can transmit */
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#define TCR_FDUPLX 0x0800 /* receive packets sent out */
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#define TCR_STP_SQET 0x1000 /* stop transmitting if Signal quality error */
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#define TCR_MON_CNS 0x0400 /* monitors the carrier status */
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#define TCR_PAD_ENABLE 0x0080 /* pads short packets to 64 bytes */
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#define TCR_CLEAR 0 /* do NOTHING */
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/* the normal settings for the TCR register : */
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#define TCR_NORMAL (TCR_ENABLE | TCR_PAD_ENABLE)
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#define EPH_STATUS 2
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#define ES_LINK_OK 0x4000 /* is the link integrity ok ? */
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#define RCR 4
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#define RCR_SOFTRESET 0x8000 /* resets the chip */
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#define RCR_STRIP_CRC 0x200 /* strips CRC */
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#define RCR_ENABLE 0x100 /* IFF this is set, we can receive packets */
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#define RCR_ALMUL 0x4 /* receive all multicast packets */
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#define RCR_PROMISC 0x2 /* enable promiscuous mode */
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/* the normal settings for the RCR register : */
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#define RCR_NORMAL (RCR_STRIP_CRC | RCR_ENABLE)
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#define RCR_CLEAR 0x0 /* set it to a base state */
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#define COUNTER 6
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#define MIR 8
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#define MCR 10
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/* 12 is reserved */
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// Receive/Phy Control Register
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/* BANK 0 */
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#define RPC_REG 0x000A
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#define RPC_SPEED 0x2000 // When 1 PHY is in 100Mbps mode.
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#define RPC_DPLX 0x1000 // When 1 PHY is in Full-Duplex Mode
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#define RPC_ANEG 0x0800 // When 1 PHY is in Auto-Negotiate Mode
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#define RPC_LSXA_SHFT 5 // Bits to shift LS2A,LS1A,LS0A to lsb
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#define RPC_LSXB_SHFT 2 // Bits to get LS2B,LS1B,LS0B to lsb
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#define RPC_LED_100_10 (0x00) // LED = 100Mbps OR's with 10Mbps link detect
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#define RPC_LED_RES (0x01) // LED = Reserved
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#define RPC_LED_10 (0x02) // LED = 10Mbps link detect
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#define RPC_LED_FD (0x03) // LED = Full Duplex Mode
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#define RPC_LED_TX_RX (0x04) // LED = TX or RX packet occurred
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#define RPC_LED_100 (0x05) // LED = 100Mbps link dectect
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#define RPC_LED_TX (0x06) // LED = TX packet occurred
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#define RPC_LED_RX (0x07) // LED = RX packet occurred
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#define RPC_DEFAULT (RPC_ANEG | (RPC_LED_100 << RPC_LSXA_SHFT) | (RPC_LED_FD << RPC_LSXB_SHFT) | RPC_SPEED | RPC_DPLX)
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// Receive/Phy Control Register
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/* BANK 0 */
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#define RPC_REG 0x000A
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#define RPC_SPEED 0x2000 // When 1 PHY is in 100Mbps mode.
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#define RPC_DPLX 0x1000 // When 1 PHY is in Full-Duplex Mode
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#define RPC_ANEG 0x0800 // When 1 PHY is in Auto-Negotiate Mode
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#define RPC_LSXA_SHFT 5 // Bits to shift LS2A,LS1A,LS0A to lsb
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#define RPC_LSXB_SHFT 2 // Bits to get LS2B,LS1B,LS0B to lsb
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#define RPC_LED_100_10 (0x00) // LED = 100Mbps OR's with 10Mbps link detect
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#define RPC_LED_RES (0x01) // LED = Reserved
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#define RPC_LED_10 (0x02) // LED = 10Mbps link detect
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#define RPC_LED_FD (0x03) // LED = Full Duplex Mode
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#define RPC_LED_TX_RX (0x04) // LED = TX or RX packet occurred
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#define RPC_LED_100 (0x05) // LED = 100Mbps link dectect
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#define RPC_LED_TX (0x06) // LED = TX packet occurred
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#define RPC_LED_RX (0x07) // LED = RX packet occurred
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#define RPC_DEFAULT (RPC_ANEG | (RPC_LED_100 << RPC_LSXA_SHFT) | (RPC_LED_FD << RPC_LSXB_SHFT) | RPC_SPEED | RPC_DPLX)
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/* BANK 1 */
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#define CONFIG 0
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#define CFG_AUI_SELECT 0x100
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#define BASE 2
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#define ADDR0 4
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#define ADDR1 6
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#define ADDR2 8
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#define GENERAL 10
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#define CONTROL 12
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#define CTL_POWERDOWN 0x2000
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#define CTL_LE_ENABLE 0x80
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#define CTL_CR_ENABLE 0x40
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#define CTL_TE_ENABLE 0x0020
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#define CTL_AUTO_RELEASE 0x0800
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#define CTL_EPROM_ACCESS 0x0003 /* high if Eprom is being read */
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/* BANK 2 */
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#define MMU_CMD 0
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#define MC_BUSY 1 /* only readable bit in the register */
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#define MC_NOP 0
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#define MC_ALLOC 0x20 /* or with number of 256 byte packets */
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#define MC_RESET 0x40
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#define MC_REMOVE 0x60 /* remove the current rx packet */
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#define MC_RELEASE 0x80 /* remove and release the current rx packet */
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#define MC_FREEPKT 0xA0 /* Release packet in PNR register */
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#define MC_ENQUEUE 0xC0 /* Enqueue the packet for transmit */
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#define PNR_ARR 2
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#define FIFO_PORTS 4
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#define FP_RXEMPTY 0x8000
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#define FP_TXEMPTY 0x80
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#define POINTER 6
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#define PTR_READ 0x2000
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#define PTR_RCV 0x8000
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#define PTR_AUTOINC 0x4000
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#define PTR_AUTO_INC 0x0040
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#define DATA_1 8
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#define DATA_2 10
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#define INTERRUPT 12
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#define INT_MASK 13
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#define IM_RCV_INT 0x1
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#define IM_TX_INT 0x2
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#define IM_TX_EMPTY_INT 0x4
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#define IM_ALLOC_INT 0x8
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#define IM_RX_OVRN_INT 0x10
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#define IM_EPH_INT 0x20
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#define IM_ERCV_INT 0x40 /* not on SMC9192 */
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/* BANK 3 */
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#define MULTICAST1 0
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#define MULTICAST2 2
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#define MULTICAST3 4
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#define MULTICAST4 6
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#define MGMT 8
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#define REVISION 10 /* ( hi: chip id low: rev # ) */
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// Management Interface Register (MII)
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#define MII_REG 0x0008
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#define MII_MSK_CRS100 0x4000 // Disables CRS100 detection during tx half dup
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#define MII_MDOE 0x0008 // MII Output Enable
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#define MII_MCLK 0x0004 // MII Clock, pin MDCLK
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#define MII_MDI 0x0002 // MII Input, pin MDI
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#define MII_MDO 0x0001 // MII Output, pin MDO
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/* this is NOT on SMC9192 */
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#define ERCV 12
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/* Note that 9194 and 9196 have the smame chip id,
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* the 9196 will have revisions starting at 6 */
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#define CHIP_9190 3
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#define CHIP_9194 4
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#define CHIP_9195 5
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#define CHIP_9196 4
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#define CHIP_91100 7
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#define CHIP_91100FD 8
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#define REV_9196 6
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/*
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* Transmit status bits
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*/
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#define TS_SUCCESS 0x0001
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#define TS_LOSTCAR 0x0400
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#define TS_LATCOL 0x0200
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#define TS_16COL 0x0010
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/*
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* Receive status bits
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*/
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#define RS_ALGNERR 0x8000
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#define RS_BADCRC 0x2000
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#define RS_ODDFRAME 0x1000
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#define RS_TOOLONG 0x0800
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#define RS_TOOSHORT 0x0400
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#define RS_MULTICAST 0x0001
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#define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
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// Management Interface Register (MII)
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#define MII_REG 0x0008
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#define MII_MSK_CRS100 0x4000 // Disables CRS100 detection during tx half dup
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#define MII_MDOE 0x0008 // MII Output Enable
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#define MII_MCLK 0x0004 // MII Clock, pin MDCLK
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#define MII_MDI 0x0002 // MII Input, pin MDI
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#define MII_MDO 0x0001 // MII Output, pin MDO
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// PHY Register Addresses (LAN91C111 Internal PHY)
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// PHY Control Register
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#define PHY_CNTL_REG 0x00
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#define PHY_CNTL_RST 0x8000 // 1=PHY Reset
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#define PHY_CNTL_LPBK 0x4000 // 1=PHY Loopback
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#define PHY_CNTL_SPEED 0x2000 // 1=100Mbps, 0=10Mpbs
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#define PHY_CNTL_ANEG_EN 0x1000 // 1=Enable Auto negotiation
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#define PHY_CNTL_PDN 0x0800 // 1=PHY Power Down mode
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#define PHY_CNTL_MII_DIS 0x0400 // 1=MII 4 bit interface disabled
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#define PHY_CNTL_ANEG_RST 0x0200 // 1=Reset Auto negotiate
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#define PHY_CNTL_DPLX 0x0100 // 1=Full Duplex, 0=Half Duplex
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#define PHY_CNTL_COLTST 0x0080 // 1= MII Colision Test
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// PHY Status Register
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#define PHY_STAT_REG 0x01
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#define PHY_STAT_CAP_T4 0x8000 // 1=100Base-T4 capable
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#define PHY_STAT_CAP_TXF 0x4000 // 1=100Base-X full duplex capable
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#define PHY_STAT_CAP_TXH 0x2000 // 1=100Base-X half duplex capable
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#define PHY_STAT_CAP_TF 0x1000 // 1=10Mbps full duplex capable
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#define PHY_STAT_CAP_TH 0x0800 // 1=10Mbps half duplex capable
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#define PHY_STAT_CAP_SUPR 0x0040 // 1=recv mgmt frames with not preamble
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#define PHY_STAT_ANEG_ACK 0x0020 // 1=ANEG has completed
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#define PHY_STAT_REM_FLT 0x0010 // 1=Remote Fault detected
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#define PHY_STAT_CAP_ANEG 0x0008 // 1=Auto negotiate capable
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#define PHY_STAT_LINK 0x0004 // 1=valid link
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#define PHY_STAT_JAB 0x0002 // 1=10Mbps jabber condition
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#define PHY_STAT_EXREG 0x0001 // 1=extended registers implemented
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// PHY Identifier Registers
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#define PHY_ID1_REG 0x02 // PHY Identifier 1
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#define PHY_ID2_REG 0x03 // PHY Identifier 2
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// PHY Auto-Negotiation Advertisement Register
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#define PHY_AD_REG 0x04
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#define PHY_AD_NP 0x8000 // 1=PHY requests exchange of Next Page
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#define PHY_AD_ACK 0x4000 // 1=got link code word from remote
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#define PHY_AD_RF 0x2000 // 1=advertise remote fault
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#define PHY_AD_T4 0x0200 // 1=PHY is capable of 100Base-T4
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#define PHY_AD_TX_FDX 0x0100 // 1=PHY is capable of 100Base-TX FDPLX
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#define PHY_AD_TX_HDX 0x0080 // 1=PHY is capable of 100Base-TX HDPLX
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#define PHY_AD_10_FDX 0x0040 // 1=PHY is capable of 10Base-T FDPLX
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#define PHY_AD_10_HDX 0x0020 // 1=PHY is capable of 10Base-T HDPLX
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#define PHY_AD_CSMA 0x0001 // 1=PHY is capable of 802.3 CMSA
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// PHY Auto-negotiation Remote End Capability Register
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#define PHY_RMT_REG 0x05
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// Uses same bit definitions as PHY_AD_REG
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// PHY Configuration Register 1
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#define PHY_CFG1_REG 0x10
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#define PHY_CFG1_LNKDIS 0x8000 // 1=Rx Link Detect Function disabled
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#define PHY_CFG1_XMTDIS 0x4000 // 1=TP Transmitter Disabled
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#define PHY_CFG1_XMTPDN 0x2000 // 1=TP Transmitter Powered Down
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#define PHY_CFG1_BYPSCR 0x0400 // 1=Bypass scrambler/descrambler
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#define PHY_CFG1_UNSCDS 0x0200 // 1=Unscramble Idle Reception Disable
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#define PHY_CFG1_EQLZR 0x0100 // 1=Rx Equalizer Disabled
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#define PHY_CFG1_CABLE 0x0080 // 1=STP(150ohm), 0=UTP(100ohm)
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#define PHY_CFG1_RLVL0 0x0040 // 1=Rx Squelch level reduced by 4.5db
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#define PHY_CFG1_TLVL_SHIFT 2 // Transmit Output Level Adjust
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#define PHY_CFG1_TLVL_MASK 0x003C
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#define PHY_CFG1_TRF_MASK 0x0003 // Transmitter Rise/Fall time
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// PHY Configuration Register 2
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#define PHY_CFG2_REG 0x11
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#define PHY_CFG2_APOLDIS 0x0020 // 1=Auto Polarity Correction disabled
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#define PHY_CFG2_JABDIS 0x0010 // 1=Jabber disabled
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#define PHY_CFG2_MREG 0x0008 // 1=Multiple register access (MII mgt)
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#define PHY_CFG2_INTMDIO 0x0004 // 1=Interrupt signaled with MDIO pulseo
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// PHY Status Output (and Interrupt status) Register
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#define PHY_INT_REG 0x12 // Status Output (Interrupt Status)
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#define PHY_INT_INT 0x8000 // 1=bits have changed since last read
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#define PHY_INT_LNKFAIL 0x4000 // 1=Link Not detected
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#define PHY_INT_LOSSSYNC 0x2000 // 1=Descrambler has lost sync
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#define PHY_INT_CWRD 0x1000 // 1=Invalid 4B5B code detected on rx
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#define PHY_INT_SSD 0x0800 // 1=No Start Of Stream detected on rx
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#define PHY_INT_ESD 0x0400 // 1=No End Of Stream detected on rx
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#define PHY_INT_RPOL 0x0200 // 1=Reverse Polarity detected
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#define PHY_INT_JAB 0x0100 // 1=Jabber detected
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#define PHY_INT_SPDDET 0x0080 // 1=100Base-TX mode, 0=10Base-T mode
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#define PHY_INT_DPLXDET 0x0040 // 1=Device in Full Duplex
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// PHY Interrupt/Status Mask Register
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#define PHY_MASK_REG 0x13 // Interrupt Mask
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// Uses the same bit definitions as PHY_INT_REG
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// PHY Register Addresses (LAN91C111 Internal PHY)
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// PHY Control Register
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#define PHY_CNTL_REG 0x00
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#define PHY_CNTL_RST 0x8000 // 1=PHY Reset
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#define PHY_CNTL_LPBK 0x4000 // 1=PHY Loopback
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#define PHY_CNTL_SPEED 0x2000 // 1=100Mbps, 0=10Mpbs
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#define PHY_CNTL_ANEG_EN 0x1000 // 1=Enable Auto negotiation
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#define PHY_CNTL_PDN 0x0800 // 1=PHY Power Down mode
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#define PHY_CNTL_MII_DIS 0x0400 // 1=MII 4 bit interface disabled
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#define PHY_CNTL_ANEG_RST 0x0200 // 1=Reset Auto negotiate
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#define PHY_CNTL_DPLX 0x0100 // 1=Full Duplex, 0=Half Duplex
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#define PHY_CNTL_COLTST 0x0080 // 1= MII Colision Test
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// PHY Status Register
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#define PHY_STAT_REG 0x01
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#define PHY_STAT_CAP_T4 0x8000 // 1=100Base-T4 capable
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#define PHY_STAT_CAP_TXF 0x4000 // 1=100Base-X full duplex capable
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#define PHY_STAT_CAP_TXH 0x2000 // 1=100Base-X half duplex capable
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#define PHY_STAT_CAP_TF 0x1000 // 1=10Mbps full duplex capable
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#define PHY_STAT_CAP_TH 0x0800 // 1=10Mbps half duplex capable
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#define PHY_STAT_CAP_SUPR 0x0040 // 1=recv mgmt frames with not preamble
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#define PHY_STAT_ANEG_ACK 0x0020 // 1=ANEG has completed
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#define PHY_STAT_REM_FLT 0x0010 // 1=Remote Fault detected
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#define PHY_STAT_CAP_ANEG 0x0008 // 1=Auto negotiate capable
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#define PHY_STAT_LINK 0x0004 // 1=valid link
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#define PHY_STAT_JAB 0x0002 // 1=10Mbps jabber condition
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#define PHY_STAT_EXREG 0x0001 // 1=extended registers implemented
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// PHY Identifier Registers
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#define PHY_ID1_REG 0x02 // PHY Identifier 1
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#define PHY_ID2_REG 0x03 // PHY Identifier 2
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// PHY Auto-Negotiation Advertisement Register
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#define PHY_AD_REG 0x04
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#define PHY_AD_NP 0x8000 // 1=PHY requests exchange of Next Page
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#define PHY_AD_ACK 0x4000 // 1=got link code word from remote
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#define PHY_AD_RF 0x2000 // 1=advertise remote fault
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#define PHY_AD_T4 0x0200 // 1=PHY is capable of 100Base-T4
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#define PHY_AD_TX_FDX 0x0100 // 1=PHY is capable of 100Base-TX FDPLX
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#define PHY_AD_TX_HDX 0x0080 // 1=PHY is capable of 100Base-TX HDPLX
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#define PHY_AD_10_FDX 0x0040 // 1=PHY is capable of 10Base-T FDPLX
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#define PHY_AD_10_HDX 0x0020 // 1=PHY is capable of 10Base-T HDPLX
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#define PHY_AD_CSMA 0x0001 // 1=PHY is capable of 802.3 CMSA
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// PHY Auto-negotiation Remote End Capability Register
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#define PHY_RMT_REG 0x05
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// Uses same bit definitions as PHY_AD_REG
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// PHY Configuration Register 1
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#define PHY_CFG1_REG 0x10
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#define PHY_CFG1_LNKDIS 0x8000 // 1=Rx Link Detect Function disabled
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#define PHY_CFG1_XMTDIS 0x4000 // 1=TP Transmitter Disabled
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#define PHY_CFG1_XMTPDN 0x2000 // 1=TP Transmitter Powered Down
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#define PHY_CFG1_BYPSCR 0x0400 // 1=Bypass scrambler/descrambler
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#define PHY_CFG1_UNSCDS 0x0200 // 1=Unscramble Idle Reception Disable
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#define PHY_CFG1_EQLZR 0x0100 // 1=Rx Equalizer Disabled
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#define PHY_CFG1_CABLE 0x0080 // 1=STP(150ohm), 0=UTP(100ohm)
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#define PHY_CFG1_RLVL0 0x0040 // 1=Rx Squelch level reduced by 4.5db
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#define PHY_CFG1_TLVL_SHIFT 2 // Transmit Output Level Adjust
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#define PHY_CFG1_TLVL_MASK 0x003C
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#define PHY_CFG1_TRF_MASK 0x0003 // Transmitter Rise/Fall time
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// PHY Configuration Register 2
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#define PHY_CFG2_REG 0x11
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#define PHY_CFG2_APOLDIS 0x0020 // 1=Auto Polarity Correction disabled
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#define PHY_CFG2_JABDIS 0x0010 // 1=Jabber disabled
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#define PHY_CFG2_MREG 0x0008 // 1=Multiple register access (MII mgt)
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#define PHY_CFG2_INTMDIO 0x0004 // 1=Interrupt signaled with MDIO pulseo
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// PHY Status Output (and Interrupt status) Register
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#define PHY_INT_REG 0x12 // Status Output (Interrupt Status)
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#define PHY_INT_INT 0x8000 // 1=bits have changed since last read
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#define PHY_INT_LNKFAIL 0x4000 // 1=Link Not detected
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#define PHY_INT_LOSSSYNC 0x2000 // 1=Descrambler has lost sync
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#define PHY_INT_CWRD 0x1000 // 1=Invalid 4B5B code detected on rx
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#define PHY_INT_SSD 0x0800 // 1=No Start Of Stream detected on rx
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#define PHY_INT_ESD 0x0400 // 1=No End Of Stream detected on rx
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#define PHY_INT_RPOL 0x0200 // 1=Reverse Polarity detected
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#define PHY_INT_JAB 0x0100 // 1=Jabber detected
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#define PHY_INT_SPDDET 0x0080 // 1=100Base-TX mode, 0=10Base-T mode
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#define PHY_INT_DPLXDET 0x0040 // 1=Device in Full Duplex
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// PHY Interrupt/Status Mask Register
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#define PHY_MASK_REG 0x13 // Interrupt Mask
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// Uses the same bit definitions as PHY_INT_REG
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/*-------------------------------------------------------------------------
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* I define some macros to make it easier to do somewhat common
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* or slightly complicated, repeated tasks.
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--------------------------------------------------------------------------*/
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/* select a register bank, 0 to 3 */
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#define SMC_SELECT_BANK(x, y) { _outw( y, x + BANK_SELECT ); }
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/* define a small delay for the reset */
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#define SMC_DELAY(x) { inw( x + RCR );\
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inw( x + RCR );\
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inw( x + RCR ); }
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#endif /* _SMC_9000_H_ */
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