mirror of
https://github.com/xcat2/xNBA.git
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614c39a8a4
#!/usr/bin/perl -w -pi -0777
use strict;
( my $type ) = /find_(\w+?)_boot_device/ or die "Could not find type\n";
( my $disable ) = /\.disable\s*=\s*(\w+)/ or die "Could not locate disable\n";
s/(${disable}\s*\(\s*struct\s+nic\s+\*nic)(\s*\)\s*\{)(\s*)/${1}, struct ${type}_device \*${type} __unused${2}${3}nic_disable ( nic );${3}/s;
s/(${disable}\s*\(\s*struct\s+nic\s+\*nic)(\s*\)\s*;)/${1}, struct ${type}_device \*${type}${2}/g;
s/^\s*.disable\s*=\s*${disable}\s*,\s*?$//m;
s/(_probe\s*\(\s*)struct\s+dev\s+\*dev/${1}struct nic \*nic/g;
s/^\s*struct\s+nic\s+\*nic\s*=\s*nic_device\s*\(\s*dev\s*\)\s*;\s*?$//m;
s/^(\s*)(nic->(ioaddr|irqno)\s*=\s*${type})/${1}${type}_fill_nic ( nic, ${type} );\n${1}${2}/m;
892 lines
26 KiB
C
892 lines
26 KiB
C
/**************************************************************************
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*
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* sundance.c -- Etherboot device driver for the Sundance ST201 "Alta".
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* Written 2002-2002 by Timothy Legge <tlegge@rogers.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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* Portions of this code based on:
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* sundance.c: A Linux device driver for the Sundance ST201 "Alta"
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* Written 1999-2002 by Donald Becker
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*
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* tulip.c: Tulip and Clone Etherboot Driver
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* By Marty Conner
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* Copyright (C) 2001 Entity Cyber, Inc.
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*
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* Linux Driver Version LK1.09a, 10-Jul-2003 (2.4.25)
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*
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* REVISION HISTORY:
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* ================
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* v1.1 01-01-2003 timlegge Initial implementation
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* v1.7 04-10-2003 timlegge Transfers Linux Kernel (30 sec)
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* v1.8 04-13-2003 timlegge Fix multiple transmission bug
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* v1.9 08-19-2003 timlegge Support Multicast
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* v1.10 01-17-2004 timlegge Initial driver output cleanup
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* v1.11 03-21-2004 timlegge Remove unused variables
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* v1.12 03-21-2004 timlegge Remove excess MII defines
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* v1.13 03-24-2004 timlegge Update to Linux 2.4.25 driver
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*
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****************************************************************************/
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/* to get some global routines like printf */
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#include "etherboot.h"
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/* to get the interface to the body of the program */
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#include "nic.h"
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/* to get the PCI support functions, if this is a PCI NIC */
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#include "pci.h"
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#include "timer.h"
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#include "mii.h"
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#define drv_version "v1.12"
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#define drv_date "2004-03-21"
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typedef unsigned char u8;
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typedef signed char s8;
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typedef unsigned short u16;
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typedef signed short s16;
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typedef unsigned int u32;
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typedef signed int s32;
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#define HZ 100
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/* Condensed operations for readability. */
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#define virt_to_le32desc(addr) cpu_to_le32(virt_to_bus(addr))
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#define le32desc_to_virt(addr) bus_to_virt(le32_to_cpu(addr))
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/* May need to be moved to mii.h */
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struct mii_if_info {
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int phy_id;
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int advertising;
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unsigned int full_duplex:1; /* is full duplex? */
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};
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//#define EDEBUG
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#ifdef EDEBUG
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#define dprintf(x) printf x
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#else
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#define dprintf(x)
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#endif
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/* Set the mtu */
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static int mtu = 1514;
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/* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
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The sundance uses a 64 element hash table based on the Ethernet CRC. */
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// static int multicast_filter_limit = 32;
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/* Set the copy breakpoint for the copy-only-tiny-frames scheme.
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Setting to > 1518 effectively disables this feature.
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This chip can receive into any byte alignment buffers, so word-oriented
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archs do not need a copy-align of the IP header. */
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static int rx_copybreak = 0;
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static int flowctrl = 1;
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/* Allow forcing the media type */
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/* media[] specifies the media type the NIC operates at.
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autosense Autosensing active media.
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10mbps_hd 10Mbps half duplex.
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10mbps_fd 10Mbps full duplex.
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100mbps_hd 100Mbps half duplex.
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100mbps_fd 100Mbps full duplex.
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*/
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static char media[] = "autosense";
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/* Operational parameters that are set at compile time. */
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/* As Etherboot uses a Polling driver we can keep the number of rings
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to the minimum number required. In general that is 1 transmit and 4 receive receive rings. However some cards require that
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there be a minimum of 2 rings */
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#define TX_RING_SIZE 2
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#define TX_QUEUE_LEN 10 /* Limit ring entries actually used. */
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#define RX_RING_SIZE 4
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/* Operational parameters that usually are not changed. */
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/* Time in jiffies before concluding the transmitter is hung. */
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#define TX_TIME_OUT (4*HZ)
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#define PKT_BUF_SZ 1536
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/* Offsets to the device registers.
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Unlike software-only systems, device drivers interact with complex hardware.
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It's not useful to define symbolic names for every register bit in the
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device. The name can only partially document the semantics and make
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the driver longer and more difficult to read.
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In general, only the important configuration values or bits changed
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multiple times should be defined symbolically.
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*/
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enum alta_offsets {
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DMACtrl = 0x00,
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TxListPtr = 0x04,
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TxDMABurstThresh = 0x08,
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TxDMAUrgentThresh = 0x09,
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TxDMAPollPeriod = 0x0a,
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RxDMAStatus = 0x0c,
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RxListPtr = 0x10,
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DebugCtrl0 = 0x1a,
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DebugCtrl1 = 0x1c,
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RxDMABurstThresh = 0x14,
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RxDMAUrgentThresh = 0x15,
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RxDMAPollPeriod = 0x16,
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LEDCtrl = 0x1a,
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ASICCtrl = 0x30,
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EEData = 0x34,
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EECtrl = 0x36,
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TxStartThresh = 0x3c,
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RxEarlyThresh = 0x3e,
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FlashAddr = 0x40,
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FlashData = 0x44,
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TxStatus = 0x46,
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TxFrameId = 0x47,
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DownCounter = 0x18,
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IntrClear = 0x4a,
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IntrEnable = 0x4c,
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IntrStatus = 0x4e,
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MACCtrl0 = 0x50,
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MACCtrl1 = 0x52,
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StationAddr = 0x54,
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MaxFrameSize = 0x5A,
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RxMode = 0x5c,
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MIICtrl = 0x5e,
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MulticastFilter0 = 0x60,
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MulticastFilter1 = 0x64,
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RxOctetsLow = 0x68,
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RxOctetsHigh = 0x6a,
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TxOctetsLow = 0x6c,
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TxOctetsHigh = 0x6e,
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TxFramesOK = 0x70,
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RxFramesOK = 0x72,
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StatsCarrierError = 0x74,
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StatsLateColl = 0x75,
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StatsMultiColl = 0x76,
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StatsOneColl = 0x77,
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StatsTxDefer = 0x78,
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RxMissed = 0x79,
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StatsTxXSDefer = 0x7a,
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StatsTxAbort = 0x7b,
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StatsBcastTx = 0x7c,
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StatsBcastRx = 0x7d,
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StatsMcastTx = 0x7e,
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StatsMcastRx = 0x7f,
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/* Aliased and bogus values! */
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RxStatus = 0x0c,
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};
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enum ASICCtrl_HiWord_bit {
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GlobalReset = 0x0001,
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RxReset = 0x0002,
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TxReset = 0x0004,
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DMAReset = 0x0008,
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FIFOReset = 0x0010,
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NetworkReset = 0x0020,
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HostReset = 0x0040,
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ResetBusy = 0x0400,
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};
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/* Bits in the interrupt status/mask registers. */
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enum intr_status_bits {
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IntrSummary = 0x0001, IntrPCIErr = 0x0002, IntrMACCtrl = 0x0008,
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IntrTxDone = 0x0004, IntrRxDone = 0x0010, IntrRxStart = 0x0020,
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IntrDrvRqst = 0x0040,
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StatsMax = 0x0080, LinkChange = 0x0100,
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IntrTxDMADone = 0x0200, IntrRxDMADone = 0x0400,
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};
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/* Bits in the RxMode register. */
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enum rx_mode_bits {
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AcceptAllIPMulti = 0x20, AcceptMultiHash = 0x10, AcceptAll = 0x08,
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AcceptBroadcast = 0x04, AcceptMulticast = 0x02, AcceptMyPhys =
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0x01,
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};
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/* Bits in MACCtrl. */
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enum mac_ctrl0_bits {
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EnbFullDuplex = 0x20, EnbRcvLargeFrame = 0x40,
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EnbFlowCtrl = 0x100, EnbPassRxCRC = 0x200,
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};
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enum mac_ctrl1_bits {
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StatsEnable = 0x0020, StatsDisable = 0x0040, StatsEnabled = 0x0080,
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TxEnable = 0x0100, TxDisable = 0x0200, TxEnabled = 0x0400,
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RxEnable = 0x0800, RxDisable = 0x1000, RxEnabled = 0x2000,
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};
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/* The Rx and Tx buffer descriptors.
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Using only 32 bit fields simplifies software endian correction.
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This structure must be aligned, and should avoid spanning cache lines.
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*/
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struct netdev_desc {
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u32 next_desc;
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u32 status;
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u32 addr;
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u32 length;
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};
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/* Bits in netdev_desc.status */
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enum desc_status_bits {
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DescOwn = 0x8000,
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DescEndPacket = 0x4000,
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DescEndRing = 0x2000,
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LastFrag = 0x80000000,
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DescIntrOnTx = 0x8000,
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DescIntrOnDMADone = 0x80000000,
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DisableAlign = 0x00000001,
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};
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/**********************************************
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* Descriptor Ring and Buffer defination
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***********************************************/
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/* Define the TX Descriptor */
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static struct netdev_desc tx_ring[TX_RING_SIZE];
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/* Create a static buffer of size PKT_BUF_SZ for each TX Descriptor.
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All descriptors point to a part of this buffer */
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static unsigned char txb[PKT_BUF_SZ * TX_RING_SIZE];
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/* Define the RX Descriptor */
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static struct netdev_desc rx_ring[RX_RING_SIZE];
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/* Create a static buffer of size PKT_BUF_SZ for each RX Descriptor.
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All descriptors point to a part of this buffer */
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static unsigned char rxb[RX_RING_SIZE * PKT_BUF_SZ];
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/* FIXME: Move BASE to the private structure */
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static u32 BASE;
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#define EEPROM_SIZE 128
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enum pci_id_flags_bits {
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PCI_USES_IO = 1, PCI_USES_MEM = 2, PCI_USES_MASTER = 4,
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PCI_ADDR0 = 0 << 4, PCI_ADDR1 = 1 << 4, PCI_ADDR2 =
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2 << 4, PCI_ADDR3 = 3 << 4,
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};
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enum chip_capability_flags { CanHaveMII = 1, KendinPktDropBug = 2, };
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#define PCI_IOTYPE (PCI_USES_MASTER | PCI_USES_IO | PCI_ADDR0)
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#define MII_CNT 4
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struct sundance_private {
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const char *nic_name;
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/* Frequently used values */
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unsigned int cur_rx; /* Producer/consumer ring indicies */
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unsigned int mtu;
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/* These values keep track of the tranceiver/media in use */
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unsigned int flowctrl:1;
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unsigned int an_enable:1;
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unsigned int speed;
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/* MII tranceiver section */
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struct mii_if_info mii_if;
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int mii_preamble_required;
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unsigned char phys[MII_CNT];
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unsigned char pci_rev_id;
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} sdx;
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static struct sundance_private *sdc;
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/* Station Address location within the EEPROM */
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#define EEPROM_SA_OFFSET 0x10
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#define DEFAULT_INTR (IntrRxDMADone | IntrPCIErr | \
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IntrDrvRqst | IntrTxDone | StatsMax | \
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LinkChange)
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static int eeprom_read(long ioaddr, int location);
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static int mdio_read(struct nic *nic, int phy_id, unsigned int location);
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static void mdio_write(struct nic *nic, int phy_id, unsigned int location,
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int value);
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static void set_rx_mode(struct nic *nic);
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static void check_duplex(struct nic *nic)
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{
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int mii_lpa = mdio_read(nic, sdc->phys[0], MII_LPA);
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int negotiated = mii_lpa & sdc->mii_if.advertising;
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int duplex;
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/* Force media */
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if (!sdc->an_enable || mii_lpa == 0xffff) {
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if (sdc->mii_if.full_duplex)
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outw(inw(BASE + MACCtrl0) | EnbFullDuplex,
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BASE + MACCtrl0);
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return;
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}
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/* Autonegotiation */
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duplex = (negotiated & 0x0100) || (negotiated & 0x01C0) == 0x0040;
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if (sdc->mii_if.full_duplex != duplex) {
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sdc->mii_if.full_duplex = duplex;
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dprintf(("%s: Setting %s-duplex based on MII #%d "
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"negotiated capability %4.4x.\n", sdc->nic_name,
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duplex ? "full" : "half", sdc->phys[0],
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negotiated));
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outw(inw(BASE + MACCtrl0) | duplex ? 0x20 : 0,
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BASE + MACCtrl0);
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}
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}
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/**************************************************************************
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* init_ring - setup the tx and rx descriptors
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*************************************************************************/
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static void init_ring(struct nic *nic __unused)
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{
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int i;
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sdc->cur_rx = 0;
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/* Initialize all the Rx descriptors */
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for (i = 0; i < RX_RING_SIZE; i++) {
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rx_ring[i].next_desc = virt_to_le32desc(&rx_ring[i + 1]);
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rx_ring[i].status = 0;
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rx_ring[i].length = 0;
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rx_ring[i].addr = 0;
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}
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/* Mark the last entry as wrapping the ring */
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rx_ring[i - 1].next_desc = virt_to_le32desc(&rx_ring[0]);
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for (i = 0; i < RX_RING_SIZE; i++) {
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rx_ring[i].addr = virt_to_le32desc(&rxb[i * PKT_BUF_SZ]);
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rx_ring[i].length = cpu_to_le32(PKT_BUF_SZ | LastFrag);
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}
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/* We only use one transmit buffer, but two
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* descriptors so transmit engines have somewhere
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* to point should they feel the need */
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tx_ring[0].status = 0x00000000;
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tx_ring[0].addr = virt_to_bus(&txb[0]);
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tx_ring[0].next_desc = 0; /* virt_to_bus(&tx_ring[1]); */
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/* This descriptor is never used */
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tx_ring[1].status = 0x00000000;
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tx_ring[1].addr = 0; /*virt_to_bus(&txb[0]); */
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tx_ring[1].next_desc = 0;
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/* Mark the last entry as wrapping the ring,
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* though this should never happen */
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tx_ring[1].length = cpu_to_le32(LastFrag | PKT_BUF_SZ);
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}
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/**************************************************************************
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* RESET - Reset Adapter
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* ***********************************************************************/
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static void sundance_reset(struct nic *nic)
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{
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int i;
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init_ring(nic);
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outl(virt_to_le32desc(&rx_ring[0]), BASE + RxListPtr);
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/* The Tx List Pointer is written as packets are queued */
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/* Initialize other registers. */
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/* __set_mac_addr(dev); */
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{
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u16 addr16;
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addr16 = (nic->node_addr[0] | (nic->node_addr[1] << 8));
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outw(addr16, BASE + StationAddr);
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addr16 = (nic->node_addr[2] | (nic->node_addr[3] << 8));
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outw(addr16, BASE + StationAddr + 2);
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addr16 = (nic->node_addr[4] | (nic->node_addr[5] << 8));
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outw(addr16, BASE + StationAddr + 4);
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}
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outw(sdc->mtu + 14, BASE + MaxFrameSize);
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if (sdc->mtu > 2047) /* this will never happen with default options */
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outl(inl(BASE + ASICCtrl) | 0x0c, BASE + ASICCtrl);
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set_rx_mode(nic);
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outw(0, BASE + DownCounter);
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/* Set the chip to poll every N*30nsec */
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outb(100, BASE + RxDMAPollPeriod);
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/* Fix DFE-580TX packet drop issue */
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if (sdc->pci_rev_id >= 0x14)
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writeb(0x01, BASE + DebugCtrl1);
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outw(RxEnable | TxEnable, BASE + MACCtrl1);
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/* Construct a perfect filter frame with the mac address as first match
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* and broadcast for all others */
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for (i = 0; i < 192; i++)
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txb[i] = 0xFF;
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txb[0] = nic->node_addr[0];
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txb[1] = nic->node_addr[1];
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txb[2] = nic->node_addr[2];
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txb[3] = nic->node_addr[3];
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txb[4] = nic->node_addr[4];
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txb[5] = nic->node_addr[5];
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dprintf(("%s: Done sundance_reset, status: Rx %hX Tx %hX "
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"MAC Control %hX, %hX %hX\n",
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sdc->nic_name, (int) inl(BASE + RxStatus),
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(int) inw(BASE + TxStatus), (int) inl(BASE + MACCtrl0),
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(int) inw(BASE + MACCtrl1), (int) inw(BASE + MACCtrl0)));
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}
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/**************************************************************************
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IRQ - Wait for a frame
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***************************************************************************/
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void sundance_irq ( struct nic *nic, irq_action_t action ) {
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unsigned int intr_status;
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switch ( action ) {
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case DISABLE :
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case ENABLE :
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intr_status = inw(nic->ioaddr + IntrStatus);
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intr_status = intr_status & ~DEFAULT_INTR;
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if ( action == ENABLE )
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intr_status = intr_status | DEFAULT_INTR;
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outw(intr_status, nic->ioaddr + IntrEnable);
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break;
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case FORCE :
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outw(0x0200, BASE + ASICCtrl);
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break;
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|
}
|
|
}
|
|
/**************************************************************************
|
|
POLL - Wait for a frame
|
|
***************************************************************************/
|
|
static int sundance_poll(struct nic *nic, int retreive)
|
|
{
|
|
/* return true if there's an ethernet packet ready to read */
|
|
/* nic->packet should contain data on return */
|
|
/* nic->packetlen should contain length of data */
|
|
int entry = sdc->cur_rx % RX_RING_SIZE;
|
|
u32 frame_status = le32_to_cpu(rx_ring[entry].status);
|
|
int intr_status;
|
|
int pkt_len = 0;
|
|
|
|
if (!(frame_status & DescOwn))
|
|
return 0;
|
|
|
|
/* There is a packet ready */
|
|
if(!retreive)
|
|
return 1;
|
|
|
|
intr_status = inw(nic->ioaddr + IntrStatus);
|
|
outw(intr_status, nic->ioaddr + IntrStatus);
|
|
|
|
pkt_len = frame_status & 0x1fff;
|
|
|
|
if (frame_status & 0x001f4000) {
|
|
dprintf(("Polling frame_status error\n")); /* Do we really care about this */
|
|
} else {
|
|
if (pkt_len < rx_copybreak) {
|
|
/* FIXME: What should happen Will this ever occur */
|
|
printf("Poll Error: pkt_len < rx_copybreak");
|
|
} else {
|
|
nic->packetlen = pkt_len;
|
|
memcpy(nic->packet, rxb +
|
|
(sdc->cur_rx * PKT_BUF_SZ), nic->packetlen);
|
|
|
|
}
|
|
}
|
|
rx_ring[entry].length = cpu_to_le32(PKT_BUF_SZ | LastFrag);
|
|
rx_ring[entry].status = 0;
|
|
entry++;
|
|
sdc->cur_rx = entry % RX_RING_SIZE;
|
|
outw(DEFAULT_INTR & ~(IntrRxDone|IntrRxDMADone),
|
|
nic->ioaddr + IntrStatus);
|
|
return 1;
|
|
}
|
|
|
|
/**************************************************************************
|
|
TRANSMIT - Transmit a frame
|
|
***************************************************************************/
|
|
static void sundance_transmit(struct nic *nic, const char *d, /* Destination */
|
|
unsigned int t, /* Type */
|
|
unsigned int s, /* size */
|
|
const char *p)
|
|
{ /* Packet */
|
|
u16 nstype;
|
|
u32 to;
|
|
|
|
/* Disable the Tx */
|
|
outw(TxDisable, BASE + MACCtrl1);
|
|
|
|
memcpy(txb, d, ETH_ALEN);
|
|
memcpy(txb + ETH_ALEN, nic->node_addr, ETH_ALEN);
|
|
nstype = htons((u16) t);
|
|
memcpy(txb + 2 * ETH_ALEN, (u8 *) & nstype, 2);
|
|
memcpy(txb + ETH_HLEN, p, s);
|
|
|
|
s += ETH_HLEN;
|
|
s &= 0x0FFF;
|
|
while (s < ETH_ZLEN)
|
|
txb[s++] = '\0';
|
|
|
|
/* Setup the transmit descriptor */
|
|
tx_ring[0].length = cpu_to_le32(s | LastFrag);
|
|
tx_ring[0].status = cpu_to_le32(0x00000001);
|
|
|
|
/* Point to transmit descriptor */
|
|
outl(virt_to_le32desc(&tx_ring[0]), BASE + TxListPtr);
|
|
|
|
/* Enable Tx */
|
|
outw(TxEnable, BASE + MACCtrl1);
|
|
/* Trigger an immediate send */
|
|
outw(0, BASE + TxStatus);
|
|
|
|
to = currticks() + TX_TIME_OUT;
|
|
while (!(tx_ring[0].status & 0x00010000) && (currticks() < to)); /* wait */
|
|
|
|
if (currticks() >= to) {
|
|
printf("TX Time Out");
|
|
}
|
|
/* Disable Tx */
|
|
outw(TxDisable, BASE + MACCtrl1);
|
|
|
|
}
|
|
|
|
/**************************************************************************
|
|
DISABLE - Turn off ethernet interface
|
|
***************************************************************************/
|
|
static void sundance_disable ( struct nic *nic __unused ) {
|
|
/* put the card in its initial state */
|
|
/* This function serves 3 purposes.
|
|
* This disables DMA and interrupts so we don't receive
|
|
* unexpected packets or interrupts from the card after
|
|
* etherboot has finished.
|
|
* This frees resources so etherboot may use
|
|
* this driver on another interface
|
|
* This allows etherboot to reinitialize the interface
|
|
* if something is something goes wrong.
|
|
*/
|
|
outw(0x0000, BASE + IntrEnable);
|
|
/* Stop the Chipchips Tx and Rx Status */
|
|
outw(TxDisable | RxDisable | StatsDisable, BASE + MACCtrl1);
|
|
}
|
|
|
|
static struct nic_operations sundance_operations = {
|
|
.connect = dummy_connect,
|
|
.poll = sundance_poll,
|
|
.transmit = sundance_transmit,
|
|
.irq = sundance_irq,
|
|
|
|
};
|
|
static struct pci_driver sundance_driver;
|
|
|
|
/**************************************************************************
|
|
PROBE - Look for an adapter, this routine's visible to the outside
|
|
***************************************************************************/
|
|
static int sundance_probe ( struct nic *nic, struct pci_device *pci ) {
|
|
|
|
u8 ee_data[EEPROM_SIZE];
|
|
u16 mii_ctl;
|
|
int i;
|
|
int speed;
|
|
|
|
if (pci->ioaddr == 0)
|
|
return 0;
|
|
|
|
/* BASE is used throughout to address the card */
|
|
BASE = pci->ioaddr;
|
|
printf(" sundance.c: Found %s Vendor=0x%hX Device=0x%hX\n",
|
|
dev->name, pci->vendor, pci->dev_id);
|
|
|
|
/* Get the MAC Address by reading the EEPROM */
|
|
for (i = 0; i < 3; i++) {
|
|
((u16 *) ee_data)[i] =
|
|
le16_to_cpu(eeprom_read(BASE, i + EEPROM_SA_OFFSET));
|
|
}
|
|
/* Update the nic structure with the MAC Address */
|
|
for (i = 0; i < ETH_ALEN; i++) {
|
|
nic->node_addr[i] = ee_data[i];
|
|
}
|
|
|
|
/* Set the card as PCI Bus Master */
|
|
adjust_pci_device(pci);
|
|
|
|
// sdc->mii_if.dev = pci;
|
|
// sdc->mii_if.phy_id_mask = 0x1f;
|
|
// sdc->mii_if.reg_num_mask = 0x1f;
|
|
|
|
/* point to private storage */
|
|
sdc = &sdx;
|
|
|
|
sdc->nic_name = dev->name;
|
|
sdc->mtu = mtu;
|
|
|
|
pci_read_config_byte(pci, PCI_REVISION_ID, &sdc->pci_rev_id);
|
|
dprintf(("Device revision id: %hx\n", sdc->pci_rev_id));
|
|
/* Print out some hardware info */
|
|
printf("%s: %! at ioaddr %hX, ", dev->name, nic->node_addr, BASE);
|
|
sdc->mii_preamble_required = 0;
|
|
if (1) {
|
|
int phy, phy_idx = 0;
|
|
sdc->phys[0] = 1; /* Default Setting */
|
|
sdc->mii_preamble_required++;
|
|
for (phy = 1; phy < 32 && phy_idx < MII_CNT; phy++) {
|
|
int mii_status = mdio_read(nic, phy, MII_BMSR);
|
|
if (mii_status != 0xffff && mii_status != 0x0000) {
|
|
sdc->phys[phy_idx++] = phy;
|
|
sdc->mii_if.advertising =
|
|
mdio_read(nic, phy, MII_ADVERTISE);
|
|
if ((mii_status & 0x0040) == 0)
|
|
sdc->mii_preamble_required++;
|
|
dprintf
|
|
(("%s: MII PHY found at address %d, status " "%hX advertising %hX\n", sdc->nic_name, phy, mii_status, sdc->mii_if.advertising));
|
|
}
|
|
}
|
|
sdc->mii_preamble_required--;
|
|
if (phy_idx == 0)
|
|
printf("%s: No MII transceiver found!\n",
|
|
sdc->nic_name);
|
|
sdc->mii_if.phy_id = sdc->phys[0];
|
|
}
|
|
|
|
/* Parse override configuration */
|
|
sdc->an_enable = 1;
|
|
if (strcasecmp(media, "autosense") != 0) {
|
|
sdc->an_enable = 0;
|
|
if (strcasecmp(media, "100mbps_fd") == 0 ||
|
|
strcasecmp(media, "4") == 0) {
|
|
sdc->speed = 100;
|
|
sdc->mii_if.full_duplex = 1;
|
|
} else if (strcasecmp(media, "100mbps_hd") == 0
|
|
|| strcasecmp(media, "3") == 0) {
|
|
sdc->speed = 100;
|
|
sdc->mii_if.full_duplex = 0;
|
|
} else if (strcasecmp(media, "10mbps_fd") == 0 ||
|
|
strcasecmp(media, "2") == 0) {
|
|
sdc->speed = 10;
|
|
sdc->mii_if.full_duplex = 1;
|
|
} else if (strcasecmp(media, "10mbps_hd") == 0 ||
|
|
strcasecmp(media, "1") == 0) {
|
|
sdc->speed = 10;
|
|
sdc->mii_if.full_duplex = 0;
|
|
} else {
|
|
sdc->an_enable = 1;
|
|
}
|
|
}
|
|
if (flowctrl == 1)
|
|
sdc->flowctrl = 1;
|
|
|
|
/* Fibre PHY? */
|
|
if (inl(BASE + ASICCtrl) & 0x80) {
|
|
/* Default 100Mbps Full */
|
|
if (sdc->an_enable) {
|
|
sdc->speed = 100;
|
|
sdc->mii_if.full_duplex = 1;
|
|
sdc->an_enable = 0;
|
|
}
|
|
}
|
|
|
|
/* The Linux driver uses flow control and resets the link here. This means the
|
|
mii section from above would need to be re done I believe. Since it serves
|
|
no real purpose leave it out. */
|
|
|
|
/* Force media type */
|
|
if (!sdc->an_enable) {
|
|
mii_ctl = 0;
|
|
mii_ctl |= (sdc->speed == 100) ? BMCR_SPEED100 : 0;
|
|
mii_ctl |= (sdc->mii_if.full_duplex) ? BMCR_FULLDPLX : 0;
|
|
mdio_write(nic, sdc->phys[0], MII_BMCR, mii_ctl);
|
|
printf("Override speed=%d, %s duplex\n",
|
|
sdc->speed,
|
|
sdc->mii_if.full_duplex ? "Full" : "Half");
|
|
}
|
|
|
|
/* Reset the chip to erase previous misconfiguration */
|
|
dprintf(("ASIC Control is %x.\n", inl(BASE + ASICCtrl)));
|
|
outw(0x007f, BASE + ASICCtrl + 2);
|
|
dprintf(("ASIC Control is now %x.\n", inl(BASE + ASICCtrl)));
|
|
|
|
sundance_reset(nic);
|
|
if (sdc->an_enable) {
|
|
u16 mii_advertise, mii_lpa;
|
|
mii_advertise =
|
|
mdio_read(nic, sdc->phys[0], MII_ADVERTISE);
|
|
mii_lpa = mdio_read(nic, sdc->phys[0], MII_LPA);
|
|
mii_advertise &= mii_lpa;
|
|
if (mii_advertise & ADVERTISE_100FULL)
|
|
sdc->speed = 100;
|
|
else if (mii_advertise & ADVERTISE_100HALF)
|
|
sdc->speed = 100;
|
|
else if (mii_advertise & ADVERTISE_10FULL)
|
|
sdc->speed = 10;
|
|
else if (mii_advertise & ADVERTISE_10HALF)
|
|
sdc->speed = 10;
|
|
} else {
|
|
mii_ctl = mdio_read(nic, sdc->phys[0], MII_BMCR);
|
|
speed = (mii_ctl & BMCR_SPEED100) ? 100 : 10;
|
|
sdc->speed = speed;
|
|
printf("%s: Link changed: %dMbps ,", sdc->nic_name, speed);
|
|
printf("%s duplex.\n", (mii_ctl & BMCR_FULLDPLX) ?
|
|
"full" : "half");
|
|
}
|
|
check_duplex(nic);
|
|
if (sdc->flowctrl && sdc->mii_if.full_duplex) {
|
|
outw(inw(BASE + MulticastFilter1 + 2) | 0x0200,
|
|
BASE + MulticastFilter1 + 2);
|
|
outw(inw(BASE + MACCtrl0) | EnbFlowCtrl, BASE + MACCtrl0);
|
|
}
|
|
printf("%dMbps, %s-Duplex\n", sdc->speed,
|
|
sdc->mii_if.full_duplex ? "Full" : "Half");
|
|
|
|
/* point to NIC specific routines */
|
|
nic->nic_op = &sundance_operations;
|
|
pci_fill_nic ( nic, pci );
|
|
nic->irqno = pci->irq;
|
|
nic->ioaddr = BASE;
|
|
|
|
return 1;
|
|
}
|
|
|
|
|
|
/* Read the EEPROM and MII Management Data I/O (MDIO) interfaces. */
|
|
static int eeprom_read(long ioaddr, int location)
|
|
{
|
|
int boguscnt = 10000; /* Typical 1900 ticks */
|
|
outw(0x0200 | (location & 0xff), ioaddr + EECtrl);
|
|
do {
|
|
if (!(inw(ioaddr + EECtrl) & 0x8000)) {
|
|
return inw(ioaddr + EEData);
|
|
}
|
|
}
|
|
while (--boguscnt > 0);
|
|
return 0;
|
|
}
|
|
|
|
/* MII transceiver control section.
|
|
Read and write the MII registers using software-generated serial
|
|
MDIO protocol. See the MII specifications or DP83840A data sheet
|
|
for details.
|
|
|
|
The maximum data clock rate is 2.5 Mhz.
|
|
The timing is decoupled from the processor clock by flushing the write
|
|
from the CPU write buffer with a following read, and using PCI
|
|
transaction time. */
|
|
|
|
#define mdio_in(mdio_addr) inb(mdio_addr)
|
|
#define mdio_out(value, mdio_addr) outb(value, mdio_addr)
|
|
#define mdio_delay(mdio_addr) inb(mdio_addr)
|
|
|
|
enum mii_reg_bits {
|
|
MDIO_ShiftClk = 0x0001, MDIO_Data = 0x0002, MDIO_EnbOutput =
|
|
0x0004,
|
|
};
|
|
#define MDIO_EnbIn (0)
|
|
#define MDIO_WRITE0 (MDIO_EnbOutput)
|
|
#define MDIO_WRITE1 (MDIO_Data | MDIO_EnbOutput)
|
|
|
|
/* Generate the preamble required for initial synchronization and
|
|
a few older transceivers. */
|
|
static void mdio_sync(long mdio_addr)
|
|
{
|
|
int bits = 32;
|
|
|
|
/* Establish sync by sending at least 32 logic ones. */
|
|
while (--bits >= 0) {
|
|
mdio_out(MDIO_WRITE1, mdio_addr);
|
|
mdio_delay(mdio_addr);
|
|
mdio_out(MDIO_WRITE1 | MDIO_ShiftClk, mdio_addr);
|
|
mdio_delay(mdio_addr);
|
|
}
|
|
}
|
|
|
|
static int
|
|
mdio_read(struct nic *nic __unused, int phy_id, unsigned int location)
|
|
{
|
|
long mdio_addr = BASE + MIICtrl;
|
|
int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location;
|
|
int i, retval = 0;
|
|
|
|
if (sdc->mii_preamble_required)
|
|
mdio_sync(mdio_addr);
|
|
|
|
/* Shift the read command bits out. */
|
|
for (i = 15; i >= 0; i--) {
|
|
int dataval =
|
|
(mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
|
|
|
|
mdio_out(dataval, mdio_addr);
|
|
mdio_delay(mdio_addr);
|
|
mdio_out(dataval | MDIO_ShiftClk, mdio_addr);
|
|
mdio_delay(mdio_addr);
|
|
}
|
|
/* Read the two transition, 16 data, and wire-idle bits. */
|
|
for (i = 19; i > 0; i--) {
|
|
mdio_out(MDIO_EnbIn, mdio_addr);
|
|
mdio_delay(mdio_addr);
|
|
retval = (retval << 1) | ((mdio_in(mdio_addr) & MDIO_Data)
|
|
? 1 : 0);
|
|
mdio_out(MDIO_EnbIn | MDIO_ShiftClk, mdio_addr);
|
|
mdio_delay(mdio_addr);
|
|
}
|
|
return (retval >> 1) & 0xffff;
|
|
}
|
|
|
|
static void
|
|
mdio_write(struct nic *nic __unused, int phy_id,
|
|
unsigned int location, int value)
|
|
{
|
|
long mdio_addr = BASE + MIICtrl;
|
|
int mii_cmd =
|
|
(0x5002 << 16) | (phy_id << 23) | (location << 18) | value;
|
|
int i;
|
|
|
|
if (sdc->mii_preamble_required)
|
|
mdio_sync(mdio_addr);
|
|
|
|
/* Shift the command bits out. */
|
|
for (i = 31; i >= 0; i--) {
|
|
int dataval =
|
|
(mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
|
|
mdio_out(dataval, mdio_addr);
|
|
mdio_delay(mdio_addr);
|
|
mdio_out(dataval | MDIO_ShiftClk, mdio_addr);
|
|
mdio_delay(mdio_addr);
|
|
}
|
|
/* Clear out extra bits. */
|
|
for (i = 2; i > 0; i--) {
|
|
mdio_out(MDIO_EnbIn, mdio_addr);
|
|
mdio_delay(mdio_addr);
|
|
mdio_out(MDIO_EnbIn | MDIO_ShiftClk, mdio_addr);
|
|
mdio_delay(mdio_addr);
|
|
}
|
|
return;
|
|
}
|
|
|
|
static void set_rx_mode(struct nic *nic __unused)
|
|
{
|
|
int i;
|
|
u16 mc_filter[4]; /* Multicast hash filter */
|
|
u32 rx_mode;
|
|
|
|
memset(mc_filter, 0xff, sizeof(mc_filter));
|
|
rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
|
|
|
|
if (sdc->mii_if.full_duplex && sdc->flowctrl)
|
|
mc_filter[3] |= 0x0200;
|
|
for (i = 0; i < 4; i++)
|
|
outw(mc_filter[i], BASE + MulticastFilter0 + i * 2);
|
|
outb(rx_mode, BASE + RxMode);
|
|
return;
|
|
}
|
|
|
|
static struct pci_id sundance_nics[] = {
|
|
PCI_ROM(0x13f0, 0x0201, "sundance", "ST201 Sundance 'Alta' based Adaptor"),
|
|
PCI_ROM(0x1186, 0x1002, "dfe530txs", "D-Link DFE530TXS (Sundance ST201 Alta)"),
|
|
};
|
|
|
|
static struct pci_driver sundance_driver =
|
|
PCI_DRIVER ( sundance_nics, PCI_NO_CLASS );
|
|
|
|
DRIVER ( "SUNDANCE/PCI", nic_driver, pci_driver, sundance_driver,
|
|
sundance_probe, sundance_disable );
|