xCAT/xNBA
2
0
Fork 0
mirror of https://github.com/xcat2/xNBA.git synced 2024-12-15 07:41:45 +00:00
Code Issues Projects Releases Wiki Activity

Set up %ds *before* testing a value in our data segment (d'oh!).

Browse Source 
Always send EOI; do not chain to BIOS's default interrupt handler.
They are just too unpredictable; at least VMware's seems to kill the
machine if you go anywhere near it.

Disable interrupts after return from PXENV_UNDI_ISR, just in case some
dumb PXE stack enables them.
This commit is contained in:
Michael Brown 2007-07-10 17:08:32 +01:00
parent f6f9a3098d
commit efd322091d
1 changed files with 11 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
src/arch/i386/drivers/net/undiisr.S
View File

@ -23,14 +23,17 @@ undiisr:
pushw %es
pusha
/* Set up our segment registers */
movw %cs:rm_ds, %ax
movw %ax, %ds
/* Check that we have an UNDI entry point */
cmpw $0, undinet_entry_point
je chain
/* Issue UNDI API call */
movw %cs:rm_ds, %ax
movw %ax, %ds
movw %ax, %es
pushw %ds
popw %es
movw $undinet_params, %di
movw $PXENV_UNDI_ISR, %bx
movw $PXENV_UNDI_ISR_IN_START, funcflag
@ -38,13 +41,15 @@ undiisr:
pushw %di
pushw %bx
lcall *undinet_entry_point
cli /* Just in case */
addw $6, %sp
cmpw $PXENV_UNDI_ISR_OUT_OURS, funcflag
jne chain
jne eoi
ack: /* Record interrupt occurence */
trig: /* Record interrupt occurence */
incb undiisr_trigger_count
/* Send EOI */
eoi: /* Send EOI */
movb $ICR_EOI_NON_SPECIFIC, %al
cmpb $IRQ_PIC_CUTOFF, undiisr_irq
jb 1f