mirror of
https://github.com/xcat2/xNBA.git
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Shrink cpu.c and render it useful for our purposes.
This commit is contained in:
Michael Brown
parent
25fd42ca87
commit
adf192f566
@ -1,88 +1,73 @@
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#ifdef CONFIG_X86_64
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#include "stdint.h"
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#include "string.h"
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#include "bits/cpu.h"
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#include <gpxe/init.h>
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#include <stdint.h>
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#include <string.h>
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#include <cpu.h>
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/** @file
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*
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* CPU identification
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*
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*/
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/* Standard macro to see if a specific flag is changeable */
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static inline int flag_is_changeable_p(uint32_t flag)
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{
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/**
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* Test to see if CPU flag is changeable
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*
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* @v flag Flag to test
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* @ret can_change Flag is changeable
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*/
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static inline int flag_is_changeable ( unsigned int flag ) {
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uint32_t f1, f2;
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asm("pushfl\n\t"
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"pushfl\n\t"
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"popl %0\n\t"
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"movl %0,%1\n\t"
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"xorl %2,%0\n\t"
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"pushl %0\n\t"
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"popfl\n\t"
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"pushfl\n\t"
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"popl %0\n\t"
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"popfl\n\t"
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: "=&r" (f1), "=&r" (f2)
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: "ir" (flag));
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__asm__ ( "pushfl\n\t"
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"pushfl\n\t"
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"popl %0\n\t"
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"movl %0,%1\n\t"
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"xorl %2,%0\n\t"
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"pushl %0\n\t"
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"popfl\n\t"
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"pushfl\n\t"
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"popl %0\n\t"
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"popfl\n\t"
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: "=&r" ( f1 ), "=&r" ( f2 )
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: "ir" ( flag ) );
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return ((f1^f2) & flag) != 0;
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return ( ( ( f1 ^ f2 ) & flag ) != 0 );
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}
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/**
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* Get CPU information
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*
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* @v cpu CPU information structure to fill in
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*/
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void get_cpuinfo ( struct cpuinfo_x86 *cpu ) {
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unsigned int cpuid_level;
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unsigned int cpuid_extlevel;
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unsigned int discard_1, discard_2, discard_3;
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/* Probe for the CPUID instruction */
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static inline int have_cpuid_p(void)
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{
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return flag_is_changeable_p(X86_EFLAGS_ID);
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}
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memset ( cpu, 0, sizeof ( *cpu ) );
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static void identify_cpu(struct cpuinfo_x86 *c)
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{
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unsigned xlvl;
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c->cpuid_level = -1; /* CPUID not detected */
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c->x86_model = c->x86_mask = 0; /* So far unknown... */
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c->x86_vendor_id[0] = '\0'; /* Unset */
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memset(&c->x86_capability, 0, sizeof c->x86_capability);
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if (!have_cpuid_p()) {
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/* CPU doesn'thave CPUID */
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/* If there are any capabilities, they'r vendor-specific */
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/* enable_cpuid() would have set c->x86 for us. */
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/* Check for CPUID instruction */
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if ( ! flag_is_changeable ( X86_EFLAGS_ID ) ) {
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DBG ( "CPUID not supported\n" );
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return;
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}
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else {
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/* CPU does have CPUID */
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/* Get vendor name */
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cpuid(0x00000000, &c->cpuid_level,
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(int *)&c->x86_vendor_id[0],
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(int *)&c->x86_vendor_id[8],
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(int *)&c->x86_vendor_id[4]);
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/* Initialize the standard set of capabilities */
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/* Note that the vendor-specific code below might override */
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/* Get features, if present */
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cpuid ( 0x00000000, &cpuid_level, &discard_1,
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&discard_2, &discard_3 );
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if ( cpuid_level >= 0x00000001 ) {
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cpuid ( 0x00000001, &discard_1, &discard_2,
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&discard_3, &cpu->features );
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} else {
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DBG ( "CPUID cannot return capabilities\n" );
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}
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/* Intel-defined flags: level 0x00000001 */
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if ( c->cpuid_level >= 0x00000001 ) {
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unsigned tfms, junk;
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cpuid(0x00000001, &tfms, &junk, &junk,
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&c->x86_capability[0]);
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c->x86 = (tfms >> 8) & 15;
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c->x86_model = (tfms >> 4) & 15;
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c->x86_mask = tfms & 15;
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}
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/* AMD-defined flags: level 0x80000001 */
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xlvl = cpuid_eax(0x80000000);
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if ( (xlvl & 0xffff0000) == 0x80000000 ) {
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if ( xlvl >= 0x80000001 )
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c->x86_capability[1] = cpuid_edx(0x80000001);
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/* Get 64-bit features, if present */
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cpuid ( 0x80000000, &cpuid_extlevel, &discard_1,
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&discard_2, &discard_3 );
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if ( ( cpuid_extlevel & 0xffff0000 ) == 0x80000000 ) {
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if ( cpuid_extlevel >= 0x80000001 ) {
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cpuid ( 0x80000001, &discard_1, &discard_2,
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&discard_3, &cpu->amd_features );
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}
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}
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}
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struct cpuinfo_x86 cpu_info;
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void cpu_setup(void)
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{
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identify_cpu(&cpu_info);
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}
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#endif /* CONFIG_X86_64 */
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@ -1,88 +1,54 @@
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#ifndef I386_BITS_CPU_H
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#define I386_BITS_CPU_H
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/* Sample usage: CPU_FEATURE_P(cpu.x86_capability, FPU) */
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#define CPU_FEATURE_P(CAP, FEATURE) \
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(!!(CAP[(X86_FEATURE_##FEATURE)/32] & ((X86_FEATURE_##FEATURE) & 0x1f)))
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#define NCAPINTS 4 /* Currently we have 4 32-bit words worth of info */
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/* Intel-defined CPU features, CPUID level 0x00000001, word 0 */
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#define X86_FEATURE_FPU (0*32+ 0) /* Onboard FPU */
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#define X86_FEATURE_VME (0*32+ 1) /* Virtual Mode Extensions */
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#define X86_FEATURE_DE (0*32+ 2) /* Debugging Extensions */
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#define X86_FEATURE_PSE (0*32+ 3) /* Page Size Extensions */
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#define X86_FEATURE_TSC (0*32+ 4) /* Time Stamp Counter */
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#define X86_FEATURE_MSR (0*32+ 5) /* Model-Specific Registers, RDMSR, WRMSR */
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#define X86_FEATURE_PAE (0*32+ 6) /* Physical Address Extensions */
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#define X86_FEATURE_MCE (0*32+ 7) /* Machine Check Architecture */
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#define X86_FEATURE_CX8 (0*32+ 8) /* CMPXCHG8 instruction */
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#define X86_FEATURE_APIC (0*32+ 9) /* Onboard APIC */
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#define X86_FEATURE_SEP (0*32+11) /* SYSENTER/SYSEXIT */
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#define X86_FEATURE_MTRR (0*32+12) /* Memory Type Range Registers */
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#define X86_FEATURE_PGE (0*32+13) /* Page Global Enable */
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#define X86_FEATURE_MCA (0*32+14) /* Machine Check Architecture */
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#define X86_FEATURE_CMOV (0*32+15) /* CMOV instruction (FCMOVCC and FCOMI too if FPU present) */
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#define X86_FEATURE_PAT (0*32+16) /* Page Attribute Table */
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#define X86_FEATURE_PSE36 (0*32+17) /* 36-bit PSEs */
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#define X86_FEATURE_PN (0*32+18) /* Processor serial number */
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#define X86_FEATURE_CLFLSH (0*32+19) /* Supports the CLFLUSH instruction */
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#define X86_FEATURE_DTES (0*32+21) /* Debug Trace Store */
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#define X86_FEATURE_ACPI (0*32+22) /* ACPI via MSR */
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#define X86_FEATURE_MMX (0*32+23) /* Multimedia Extensions */
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#define X86_FEATURE_FXSR (0*32+24) /* FXSAVE and FXRSTOR instructions (fast save and restore */
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#define X86_FEATURE_FPU 0 /* Onboard FPU */
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#define X86_FEATURE_VME 1 /* Virtual Mode Extensions */
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#define X86_FEATURE_DE 2 /* Debugging Extensions */
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#define X86_FEATURE_PSE 3 /* Page Size Extensions */
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#define X86_FEATURE_TSC 4 /* Time Stamp Counter */
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#define X86_FEATURE_MSR 5 /* Model-Specific Registers, RDMSR, WRMSR */
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#define X86_FEATURE_PAE 6 /* Physical Address Extensions */
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#define X86_FEATURE_MCE 7 /* Machine Check Architecture */
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#define X86_FEATURE_CX8 8 /* CMPXCHG8 instruction */
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#define X86_FEATURE_APIC 9 /* Onboard APIC */
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#define X86_FEATURE_SEP 11 /* SYSENTER/SYSEXIT */
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#define X86_FEATURE_MTRR 12 /* Memory Type Range Registers */
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#define X86_FEATURE_PGE 13 /* Page Global Enable */
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#define X86_FEATURE_MCA 14 /* Machine Check Architecture */
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#define X86_FEATURE_CMOV 15 /* CMOV instruction (FCMOVCC and FCOMI too if FPU present) */
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#define X86_FEATURE_PAT 16 /* Page Attribute Table */
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#define X86_FEATURE_PSE36 17 /* 36-bit PSEs */
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#define X86_FEATURE_PN 18 /* Processor serial number */
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#define X86_FEATURE_CLFLSH 19 /* Supports the CLFLUSH instruction */
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#define X86_FEATURE_DTES 21 /* Debug Trace Store */
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#define X86_FEATURE_ACPI 22 /* ACPI via MSR */
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#define X86_FEATURE_MMX 23 /* Multimedia Extensions */
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#define X86_FEATURE_FXSR 24 /* FXSAVE and FXRSTOR instructions (fast save and restore */
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/* of FPU context), and CR4.OSFXSR available */
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#define X86_FEATURE_XMM (0*32+25) /* Streaming SIMD Extensions */
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#define X86_FEATURE_XMM2 (0*32+26) /* Streaming SIMD Extensions-2 */
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#define X86_FEATURE_SELFSNOOP (0*32+27) /* CPU self snoop */
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#define X86_FEATURE_HT (0*32+28) /* Hyper-Threading */
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#define X86_FEATURE_ACC (0*32+29) /* Automatic clock control */
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#define X86_FEATURE_IA64 (0*32+30) /* IA-64 processor */
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#define X86_FEATURE_XMM 25 /* Streaming SIMD Extensions */
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#define X86_FEATURE_XMM2 26 /* Streaming SIMD Extensions-2 */
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#define X86_FEATURE_SELFSNOOP 27 /* CPU self snoop */
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#define X86_FEATURE_HT 28 /* Hyper-Threading */
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#define X86_FEATURE_ACC 29 /* Automatic clock control */
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#define X86_FEATURE_IA64 30 /* IA-64 processor */
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/* AMD-defined CPU features, CPUID level 0x80000001, word 1 */
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/* Don't duplicate feature flags which are redundant with Intel! */
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#define X86_FEATURE_SYSCALL (1*32+11) /* SYSCALL/SYSRET */
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#define X86_FEATURE_MMXEXT (1*32+22) /* AMD MMX extensions */
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#define X86_FEATURE_LM (1*32+29) /* Long Mode (x86-64) */
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#define X86_FEATURE_3DNOWEXT (1*32+30) /* AMD 3DNow! extensions */
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#define X86_FEATURE_3DNOW (1*32+31) /* 3DNow! */
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#define X86_FEATURE_SYSCALL 11 /* SYSCALL/SYSRET */
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#define X86_FEATURE_MMXEXT 22 /* AMD MMX extensions */
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#define X86_FEATURE_LM 29 /* Long Mode (x86-64) */
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#define X86_FEATURE_3DNOWEXT 30 /* AMD 3DNow! extensions */
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#define X86_FEATURE_3DNOW 31 /* 3DNow! */
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/* Transmeta-defined CPU features, CPUID level 0x80860001, word 2 */
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#define X86_FEATURE_RECOVERY (2*32+ 0) /* CPU in recovery mode */
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#define X86_FEATURE_LONGRUN (2*32+ 1) /* Longrun power control */
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#define X86_FEATURE_LRTI (2*32+ 3) /* LongRun table interface */
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/* Other features, Linux-defined mapping, word 3 */
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/* This range is used for feature bits which conflict or are synthesized */
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#define X86_FEATURE_CXMMX (3*32+ 0) /* Cyrix MMX extensions */
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#define X86_FEATURE_K6_MTRR (3*32+ 1) /* AMD K6 nonstandard MTRRs */
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#define X86_FEATURE_CYRIX_ARR (3*32+ 2) /* Cyrix ARRs (= MTRRs) */
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#define X86_FEATURE_CENTAUR_MCR (3*32+ 3) /* Centaur MCRs (= MTRRs) */
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#define MAX_X86_VENDOR_ID 16
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/** x86 CPU information */
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struct cpuinfo_x86 {
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uint8_t x86; /* CPU family */
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uint8_t x86_model;
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uint8_t x86_mask;
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int cpuid_level; /* Maximum supported CPUID level, -1=no CPUID */
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unsigned x86_capability[NCAPINTS];
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char x86_vendor_id[MAX_X86_VENDOR_ID];
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/** CPU features */
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unsigned int features;
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/** 64-bit CPU features */
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unsigned int amd_features;
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};
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#define X86_VENDOR_INTEL 0
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#define X86_VENDOR_CYRIX 1
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#define X86_VENDOR_AMD 2
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#define X86_VENDOR_UMC 3
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#define X86_VENDOR_NEXGEN 4
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#define X86_VENDOR_CENTAUR 5
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#define X86_VENDOR_RISE 6
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#define X86_VENDOR_TRANSMETA 7
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#define X86_VENDOR_NSC 8
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#define X86_VENDOR_UNKNOWN 0xff
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/*
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* EFLAGS bits
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*/
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@ -107,137 +73,14 @@ struct cpuinfo_x86 {
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/*
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* Generic CPUID function
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*/
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static inline void cpuid(int op,
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unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx)
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{
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__asm__("cpuid"
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: "=a" (*eax),
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"=b" (*ebx),
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"=c" (*ecx),
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"=d" (*edx)
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: "0" (op));
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static inline __attribute__ (( always_inline )) void
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cpuid ( int op, unsigned int *eax, unsigned int *ebx,
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unsigned int *ecx, unsigned int *edx ) {
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__asm__ ( "cpuid" :
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"=a" ( *eax ), "=b" ( *ebx ), "=c" ( *ecx ), "=d" ( *edx )
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: "0" ( op ) );
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}
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/*
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* CPUID functions returning a single datum
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*/
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static inline unsigned int cpuid_eax(unsigned int op)
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{
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unsigned int eax;
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__asm__("cpuid"
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: "=a" (eax)
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: "0" (op)
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: "bx", "cx", "dx");
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return eax;
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}
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static inline unsigned int cpuid_ebx(unsigned int op)
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{
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unsigned int eax, ebx;
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__asm__("cpuid"
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: "=a" (eax), "=b" (ebx)
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: "0" (op)
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: "cx", "dx" );
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return ebx;
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}
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static inline unsigned int cpuid_ecx(unsigned int op)
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{
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unsigned int eax, ecx;
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__asm__("cpuid"
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: "=a" (eax), "=c" (ecx)
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: "0" (op)
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: "bx", "dx" );
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return ecx;
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}
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static inline unsigned int cpuid_edx(unsigned int op)
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{
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unsigned int eax, edx;
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__asm__("cpuid"
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: "=a" (eax), "=d" (edx)
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: "0" (op)
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: "bx", "cx");
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return edx;
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}
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/*
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* Intel CPU features in CR4
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*/
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#define X86_CR4_VME 0x0001 /* enable vm86 extensions */
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#define X86_CR4_PVI 0x0002 /* virtual interrupts flag enable */
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#define X86_CR4_TSD 0x0004 /* disable time stamp at ipl 3 */
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#define X86_CR4_DE 0x0008 /* enable debugging extensions */
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#define X86_CR4_PSE 0x0010 /* enable page size extensions */
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#define X86_CR4_PAE 0x0020 /* enable physical address extensions */
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#define X86_CR4_MCE 0x0040 /* Machine check enable */
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#define X86_CR4_PGE 0x0080 /* enable global pages */
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#define X86_CR4_PCE 0x0100 /* enable performance counters at ipl 3 */
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#define X86_CR4_OSFXSR 0x0200 /* enable fast FPU save and restore */
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#define X86_CR4_OSXMMEXCPT 0x0400 /* enable unmasked SSE exceptions */
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#define MSR_K6_EFER 0xC0000080
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/* EFER bits: */
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#define _EFER_SCE 0 /* SYSCALL/SYSRET */
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#define _EFER_LME 8 /* Long mode enable */
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#define _EFER_LMA 10 /* Long mode active (read-only) */
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#define _EFER_NX 11 /* No execute enable */
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#define EFER_SCE (1<<_EFER_SCE)
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#define EFER_LME (1<<EFER_LME)
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#define EFER_LMA (1<<EFER_LMA)
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#define EFER_NX (1<<_EFER_NX)
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#define rdmsr(msr,val1,val2) \
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__asm__ __volatile__("rdmsr" \
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: "=a" (val1), "=d" (val2) \
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: "c" (msr))
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#define wrmsr(msr,val1,val2) \
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__asm__ __volatile__("wrmsr" \
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: /* no outputs */ \
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: "c" (msr), "a" (val1), "d" (val2))
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#define read_cr0() ({ \
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unsigned int __dummy; \
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__asm__( \
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"movl %%cr0, %0\n\t" \
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:"=r" (__dummy)); \
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__dummy; \
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})
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#define write_cr0(x) \
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__asm__("movl %0,%%cr0": :"r" (x));
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#define read_cr3() ({ \
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unsigned int __dummy; \
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__asm__( \
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"movl %%cr3, %0\n\t" \
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:"=r" (__dummy)); \
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__dummy; \
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})
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#define write_cr3x(x) \
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__asm__("movl %0,%%cr3": :"r" (x));
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#define read_cr4() ({ \
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unsigned int __dummy; \
|
||||
__asm__( \
|
||||
"movl %%cr4, %0\n\t" \
|
||||
:"=r" (__dummy)); \
|
||||
__dummy; \
|
||||
})
|
||||
#define write_cr4x(x) \
|
||||
__asm__("movl %0,%%cr4": :"r" (x));
|
||||
|
||||
|
||||
extern struct cpuinfo_x86 cpu_info;
|
||||
#ifdef CONFIG_X86_64
|
||||
extern void cpu_setup(void);
|
||||
#else
|
||||
#define cpu_setup() do {} while(0)
|
||||
#endif
|
||||
extern void get_cpuinfo ( struct cpuinfo_x86 *cpu );
|
||||
|
||||
#endif /* I386_BITS_CPU_H */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user