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[rhine] Rewrite VIA Rhine driver
Replace the old via-rhine driver with a new version using the iPXE API. Includes fixes by Thomas Miletich for: - MMIO access - Link detection - RX completion in RX overflow case - Reset and EEPROM reloading - CRC stripping - Missing cpu_to_le32() calls - Missing memory barriers Signed-off-by: Adrian Jamróz <adrian.jamroz@gmail.com> Modified-by: Thomas Miletich <thomas.miletich@gmail.com> Tested-by: Thomas Miletich <thomas.miletich@gmail.com> Tested-by: Robin Smidsrød <robin@smidsrod.no> Modified-by: Michael Brown <mcb30@ipxe.org> Tested-by: Michael Brown <mcb30@ipxe.org> Signed-off-by: Michael Brown <mcb30@ipxe.org>
This commit is contained in:
Adrian Jamróz
Michael Brown
parent
c0d2aebdcf
commit
ad4f58d410
787
src/drivers/net/rhine.c
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787
src/drivers/net/rhine.c
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@ -0,0 +1,787 @@
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/*
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* Copyright (C) 2012 Adrian Jamroz <adrian.jamroz@gmail.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
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* 02110-1301, USA.
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*/
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FILE_LICENCE ( GPL2_OR_LATER );
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#include <stdint.h>
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#include <string.h>
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#include <unistd.h>
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#include <errno.h>
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#include <byteswap.h>
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#include <ipxe/netdevice.h>
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#include <ipxe/ethernet.h>
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#include <ipxe/if_ether.h>
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#include <ipxe/iobuf.h>
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#include <ipxe/malloc.h>
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#include <ipxe/pci.h>
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#include <ipxe/mii.h>
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#include "rhine.h"
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/** @file
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*
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* VIA Rhine network driver
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*
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*/
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/******************************************************************************
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*
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* MII interface
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*
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******************************************************************************
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*/
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/**
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* Read from MII register
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*
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* @v mii MII interface
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* @v reg Register address
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* @ret value Data read, or negative error
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*/
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static int rhine_mii_read ( struct mii_interface *mii, unsigned int reg ) {
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struct rhine_nic *rhn = container_of ( mii, struct rhine_nic, mii );
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unsigned int timeout = RHINE_TIMEOUT_US;
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uint8_t cr;
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DBGC2 ( rhn, "RHINE %p MII read reg %d\n", rhn, reg );
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/* Initiate read */
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writeb ( reg, rhn->regs + RHINE_MII_ADDR );
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cr = readb ( rhn->regs + RHINE_MII_CR );
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writeb ( ( cr | RHINE_MII_CR_RDEN ), rhn->regs + RHINE_MII_CR );
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/* Wait for read to complete */
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while ( timeout-- ) {
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udelay ( 1 );
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cr = readb ( rhn->regs + RHINE_MII_CR );
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if ( ! ( cr & RHINE_MII_CR_RDEN ) )
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return readw ( rhn->regs + RHINE_MII_RDWR );
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}
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DBGC ( rhn, "RHINE %p MII read timeout\n", rhn );
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return -ETIMEDOUT;
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}
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/**
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* Write to MII register
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*
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* @v mii MII interface
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* @v reg Register address
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* @v data Data to write
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* @ret rc Return status code
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*/
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static int rhine_mii_write ( struct mii_interface *mii, unsigned int reg,
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unsigned int data ) {
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struct rhine_nic *rhn = container_of ( mii, struct rhine_nic, mii );
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unsigned int timeout = RHINE_TIMEOUT_US;
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uint8_t cr;
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DBGC2 ( rhn, "RHINE %p MII write reg %d data 0x%04x\n",
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rhn, reg, data );
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/* Initiate write */
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writeb ( reg, rhn->regs + RHINE_MII_ADDR );
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writew ( data, rhn->regs + RHINE_MII_RDWR );
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cr = readb ( rhn->regs + RHINE_MII_CR );
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writeb ( ( cr | RHINE_MII_CR_WREN ), rhn->regs + RHINE_MII_CR );
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/* Wait for write to complete */
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while ( timeout-- ) {
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udelay ( 1 );
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cr = readb ( rhn->regs + RHINE_MII_CR );
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if ( ! ( cr & RHINE_MII_CR_WREN ) )
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return 0;
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}
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DBGC ( rhn, "RHINE %p MII write timeout\n", rhn );
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return -ETIMEDOUT;
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}
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/** Rhine MII operations */
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static struct mii_operations rhine_mii_operations = {
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.read = rhine_mii_read,
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.write = rhine_mii_write,
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};
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/**
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* Enable auto-polling
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*
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* @v rhn Rhine device
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* @ret rc Return status code
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*
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* This is voodoo. There seems to be no documentation on exactly what
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* we are waiting for, or why we have to do anything other than simply
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* turn the feature on.
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*/
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static int rhine_mii_autopoll ( struct rhine_nic *rhn ) {
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unsigned int timeout = RHINE_TIMEOUT_US;
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uint8_t addr;
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/* Initiate auto-polling */
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writeb ( MII_BMSR, rhn->regs + RHINE_MII_ADDR );
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writeb ( RHINE_MII_CR_AUTOPOLL, rhn->regs + RHINE_MII_CR );
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/* Wait for auto-polling to complete */
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while ( timeout-- ) {
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udelay ( 1 );
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addr = readb ( rhn->regs + RHINE_MII_ADDR );
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if ( ! ( addr & RHINE_MII_ADDR_MDONE ) ) {
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writeb ( ( MII_BMSR | RHINE_MII_ADDR_MSRCEN ),
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rhn->regs + RHINE_MII_ADDR );
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return 0;
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}
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}
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DBGC ( rhn, "RHINE %p MII auto-poll timeout\n", rhn );
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return -ETIMEDOUT;
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}
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/******************************************************************************
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*
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* Device reset
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*
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******************************************************************************
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*/
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/**
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* Reset hardware
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*
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* @v rhn Rhine device
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* @ret rc Return status code
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*
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* We're using PIO because this might reset the MMIO enable bit.
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*/
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static int rhine_reset ( struct rhine_nic *rhn ) {
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unsigned int timeout = RHINE_TIMEOUT_US;
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uint8_t cr1;
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DBGC ( rhn, "RHINE %p reset\n", rhn );
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/* Initiate reset */
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outb ( RHINE_CR1_RESET, rhn->ioaddr + RHINE_CR1 );
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/* Wait for reset to complete */
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while ( timeout-- ) {
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udelay ( 1 );
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cr1 = inb ( rhn->ioaddr + RHINE_CR1 );
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if ( ! ( cr1 & RHINE_CR1_RESET ) )
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return 0;
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}
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DBGC ( rhn, "RHINE %p reset timeout\n", rhn );
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return -ETIMEDOUT;
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}
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/**
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* Enable MMIO register access
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*
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* @v rhn Rhine device
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* @v revision Card revision
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*/
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static void rhine_enable_mmio ( struct rhine_nic *rhn, int revision ) {
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uint8_t conf;
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if ( revision < RHINE_REVISION_OLD ) {
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conf = inb ( rhn->ioaddr + RHINE_CHIPCFG_A );
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outb ( ( conf | RHINE_CHIPCFG_A_MMIO ),
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rhn->ioaddr + RHINE_CHIPCFG_A );
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} else {
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conf = inb ( rhn->ioaddr + RHINE_CHIPCFG_D );
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outb ( ( conf | RHINE_CHIPCFG_D_MMIO ),
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rhn->ioaddr + RHINE_CHIPCFG_D );
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}
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}
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/**
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* Reload EEPROM contents
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*
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* @v rhn Rhine device
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* @ret rc Return status code
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*
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* We're using PIO because this might reset the MMIO enable bit.
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*/
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static int rhine_reload_eeprom ( struct rhine_nic *rhn ) {
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unsigned int timeout = RHINE_TIMEOUT_US;
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uint8_t eeprom;
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/* Initiate reload */
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eeprom = inb ( rhn->ioaddr + RHINE_EEPROM_CTRL );
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outb ( ( eeprom | RHINE_EEPROM_CTRL_RELOAD ),
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rhn->ioaddr + RHINE_EEPROM_CTRL );
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/* Wait for reload to complete */
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while ( timeout-- ) {
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udelay ( 1 );
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eeprom = inb ( rhn->ioaddr + RHINE_EEPROM_CTRL );
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if ( ! ( eeprom & RHINE_EEPROM_CTRL_RELOAD ) )
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return 0;
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}
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DBGC ( rhn, "RHINE %p EEPROM reload timeout\n", rhn );
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return -ETIMEDOUT;
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}
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/******************************************************************************
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*
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* Link state
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*
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******************************************************************************
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*/
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/**
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* Check link state
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*
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* @v netdev Network device
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*/
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static void rhine_check_link ( struct net_device *netdev ) {
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struct rhine_nic *rhn = netdev->priv;
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uint8_t mii_sr;
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/* Read MII status register */
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mii_sr = readb ( rhn->regs + RHINE_MII_SR );
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DBGC ( rhn, "RHINE %p link status %02x\n", rhn, mii_sr );
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/* Report link state */
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if ( ! ( mii_sr & RHINE_MII_SR_LINKPOLL ) ) {
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netdev_link_up ( netdev );
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} else if ( mii_sr & RHINE_MII_SR_PHYERR ) {
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netdev_link_err ( netdev, -EIO );
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} else {
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netdev_link_down ( netdev );
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}
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}
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/******************************************************************************
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*
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* Network device interface
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*
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******************************************************************************
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*/
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/**
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* Create descriptor ring
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*
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* @v rhn Rhine device
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* @v ring Descriptor ring
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* @ret rc Return status code
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*/
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static int rhine_create_ring ( struct rhine_nic *rhn,
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struct rhine_ring *ring ) {
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size_t len = ( ring->count * sizeof ( ring->desc[0] ) );
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struct rhine_descriptor *next;
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physaddr_t address;
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unsigned int i;
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/* Allocate descriptors */
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ring->desc = malloc_dma ( len, RHINE_RING_ALIGN );
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if ( ! ring->desc )
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return -ENOMEM;
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/* Initialise descriptor ring */
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memset ( ring->desc, 0, len );
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for ( i = 0 ; i < ring->count ; i++ ) {
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next = &ring->desc[ ( i + 1 ) % ring->count ];
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ring->desc[i].next = cpu_to_le32 ( virt_to_bus ( next ) );
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}
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/* Program ring address */
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address = virt_to_bus ( ring->desc );
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writel ( address, rhn->regs + ring->reg );
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DBGC ( rhn, "RHINE %p ring %02x is at [%08llx,%08llx)\n",
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rhn, ring->reg, ( ( unsigned long long ) address ),
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( ( unsigned long long ) address + len ) );
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return 0;
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}
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/**
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* Destroy descriptor ring
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*
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* @v rhn Rhine device
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* @v ring Descriptor ring
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*/
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static void rhine_destroy_ring ( struct rhine_nic *rhn,
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struct rhine_ring *ring ) {
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size_t len = ( ring->count * sizeof ( ring->desc[0] ) );
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/* Clear ring address */
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writel ( 0, rhn->regs + ring->reg );
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/* Free descriptor ring */
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free_dma ( ring->desc, len );
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ring->desc = NULL;
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ring->prod = 0;
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ring->cons = 0;
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}
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/**
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* Refill RX descriptor ring
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*
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* @v rhn Rhine device
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*/
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static void rhine_refill_rx ( struct rhine_nic *rhn ) {
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struct rhine_descriptor *desc;
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struct io_buffer *iobuf;
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unsigned int rx_idx;
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physaddr_t address;
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while ( ( rhn->rx.prod - rhn->rx.cons ) < RHINE_RXDESC_NUM ) {
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/* Allocate I/O buffer */
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iobuf = alloc_iob ( RHINE_RX_MAX_LEN );
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if ( ! iobuf ) {
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/* Wait for next refill */
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return;
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}
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/* Populate next receive descriptor */
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rx_idx = ( rhn->rx.prod++ % RHINE_RXDESC_NUM );
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desc = &rhn->rx.desc[rx_idx];
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address = virt_to_bus ( iobuf->data );
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desc->buffer = cpu_to_le32 ( address );
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desc->des1 =
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cpu_to_le32 ( RHINE_DES1_SIZE ( RHINE_RX_MAX_LEN - 1) |
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RHINE_DES1_CHAIN | RHINE_DES1_IC );
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wmb();
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desc->des0 = cpu_to_le32 ( RHINE_DES0_OWN );
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/* Record I/O buffer */
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rhn->rx_iobuf[rx_idx] = iobuf;
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DBGC2 ( rhn, "RHINE %p RX %d is [%llx,%llx)\n", rhn, rx_idx,
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( ( unsigned long long ) address ),
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( ( unsigned long long ) address + RHINE_RX_MAX_LEN ) );
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}
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}
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/**
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* Open network device
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*
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* @v netdev Network device
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* @ret rc Return status code
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*/
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static int rhine_open ( struct net_device *netdev ) {
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struct rhine_nic *rhn = netdev->priv;
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int rc;
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/* Create transmit ring */
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if ( ( rc = rhine_create_ring ( rhn, &rhn->tx ) ) != 0 )
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goto err_create_tx;
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/* Create receive ring */
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if ( ( rc = rhine_create_ring ( rhn, &rhn->rx ) ) != 0 )
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goto err_create_rx;
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/* Set receive configuration */
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writeb ( ( RHINE_RCR_PHYS_ACCEPT | RHINE_RCR_BCAST_ACCEPT |
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RHINE_RCR_RUNT_ACCEPT ), rhn->regs + RHINE_RCR );
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/* Enable link status monitoring */
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if ( ( rc = rhine_mii_autopoll ( rhn ) ) != 0 )
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goto err_mii_autopoll;
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/* Some cards need an extra delay(observed with VT6102) */
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mdelay ( 10 );
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/* Enable RX/TX of packets */
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writeb ( ( RHINE_CR0_STARTNIC | RHINE_CR0_RXEN | RHINE_CR0_TXEN ),
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rhn->regs + RHINE_CR0 );
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/* Enable auto polling and full duplex operation */
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rhn->cr1 = RHINE_CR1_FDX;
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writeb ( rhn->cr1, rhn->regs + RHINE_CR1 );
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/* Refill RX ring */
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rhine_refill_rx ( rhn );
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/* Update link state */
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rhine_check_link ( netdev );
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return 0;
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err_mii_autopoll:
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rhine_destroy_ring ( rhn, &rhn->rx );
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err_create_rx:
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rhine_destroy_ring ( rhn, &rhn->tx );
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err_create_tx:
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return rc;
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}
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/**
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* Close network device
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*
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* @v netdev Network device
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*/
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static void rhine_close ( struct net_device *netdev ) {
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struct rhine_nic *rhn = netdev->priv;
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unsigned int i;
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/* Disable interrupts */
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writeb ( 0, RHINE_IMR0 );
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writeb ( 0, RHINE_IMR1 );
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/* Stop card, clear RXON and TXON bits */
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writeb ( RHINE_CR0_STOPNIC, rhn->regs + RHINE_CR0 );
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/* Destroy receive ring */
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rhine_destroy_ring ( rhn, &rhn->rx );
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/* Discard any unused receive buffers */
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for ( i = 0 ; i < RHINE_RXDESC_NUM ; i++ ) {
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if ( rhn->rx_iobuf[i] )
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free_iob ( rhn->rx_iobuf[i] );
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rhn->rx_iobuf[i] = NULL;
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}
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/* Destroy transmit ring */
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rhine_destroy_ring ( rhn, &rhn->tx );
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}
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/**
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* Transmit packet
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*
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* @v netdev Network device
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* @v iobuf I/O buffer
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* @ret rc Return status code
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*/
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static int rhine_transmit ( struct net_device *netdev,
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struct io_buffer *iobuf ) {
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struct rhine_nic *rhn = netdev->priv;
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struct rhine_descriptor *desc;
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physaddr_t address;
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unsigned int tx_idx;
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/* Get next transmit descriptor */
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if ( ( rhn->tx.prod - rhn->tx.cons ) >= RHINE_TXDESC_NUM )
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return -ENOBUFS;
|
||||
tx_idx = ( rhn->tx.prod++ % RHINE_TXDESC_NUM );
|
||||
desc = &rhn->tx.desc[tx_idx];
|
||||
|
||||
/* Pad and align packet */
|
||||
iob_pad ( iobuf, ETH_ZLEN );
|
||||
address = virt_to_bus ( iobuf->data );
|
||||
|
||||
/* Populate transmit descriptor */
|
||||
desc->buffer = cpu_to_le32 ( address );
|
||||
desc->des1 = cpu_to_le32 ( RHINE_DES1_IC | RHINE_TDES1_STP |
|
||||
RHINE_TDES1_EDP | RHINE_DES1_CHAIN |
|
||||
RHINE_DES1_SIZE ( iob_len ( iobuf ) ) );
|
||||
wmb();
|
||||
desc->des0 = cpu_to_le32 ( RHINE_DES0_OWN );
|
||||
wmb();
|
||||
|
||||
/* Notify card that there are packets ready to transmit */
|
||||
writeb ( ( rhn->cr1 | RHINE_CR1_TXPOLL ), rhn->regs + RHINE_CR1 );
|
||||
|
||||
DBGC2 ( rhn, "RHINE %p TX %d is [%llx,%llx)\n", rhn, tx_idx,
|
||||
( ( unsigned long long ) address ),
|
||||
( ( unsigned long long ) address + iob_len ( iobuf ) ) );
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* Poll for completed packets
|
||||
*
|
||||
* @v netdev Network device
|
||||
*/
|
||||
static void rhine_poll_tx ( struct net_device *netdev ) {
|
||||
struct rhine_nic *rhn = netdev->priv;
|
||||
struct rhine_descriptor *desc;
|
||||
unsigned int tx_idx;
|
||||
uint32_t des0;
|
||||
|
||||
/* Check for completed packets */
|
||||
while ( rhn->tx.cons != rhn->tx.prod ) {
|
||||
|
||||
/* Get next transmit descriptor */
|
||||
tx_idx = ( rhn->tx.cons % RHINE_TXDESC_NUM );
|
||||
desc = &rhn->tx.desc[tx_idx];
|
||||
|
||||
/* Stop if descriptor is still in use */
|
||||
if ( desc->des0 & cpu_to_le32 ( RHINE_DES0_OWN ) )
|
||||
return;
|
||||
|
||||
/* Complete TX descriptor */
|
||||
des0 = le32_to_cpu ( desc->des0 );
|
||||
if ( des0 & RHINE_TDES0_TERR ) {
|
||||
DBGC ( rhn, "RHINE %p TX %d error (DES0 %08x)\n",
|
||||
rhn, tx_idx, des0 );
|
||||
netdev_tx_complete_next_err ( netdev, -EIO );
|
||||
} else {
|
||||
DBGC2 ( rhn, "RHINE %p TX %d complete\n", rhn, tx_idx );
|
||||
netdev_tx_complete_next ( netdev );
|
||||
}
|
||||
rhn->tx.cons++;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Poll for received packets
|
||||
*
|
||||
* @v netdev Network device
|
||||
*/
|
||||
static void rhine_poll_rx ( struct net_device *netdev ) {
|
||||
struct rhine_nic *rhn = netdev->priv;
|
||||
struct rhine_descriptor *desc;
|
||||
struct io_buffer *iobuf;
|
||||
unsigned int rx_idx;
|
||||
uint32_t des0;
|
||||
size_t len;
|
||||
|
||||
/* Check for received packets */
|
||||
while ( rhn->rx.cons != rhn->rx.prod ) {
|
||||
|
||||
/* Get next receive descriptor */
|
||||
rx_idx = ( rhn->rx.cons % RHINE_RXDESC_NUM );
|
||||
desc = &rhn->rx.desc[rx_idx];
|
||||
|
||||
/* Stop if descriptor is still in use */
|
||||
if ( desc->des0 & cpu_to_le32 ( RHINE_DES0_OWN ) )
|
||||
return;
|
||||
|
||||
/* Populate I/O buffer */
|
||||
iobuf = rhn->rx_iobuf[rx_idx];
|
||||
rhn->rx_iobuf[rx_idx] = NULL;
|
||||
des0 = le32_to_cpu ( desc->des0 );
|
||||
len = ( RHINE_DES0_GETSIZE ( des0 ) - 4 /* strip CRC */ );
|
||||
iob_put ( iobuf, len );
|
||||
|
||||
/* Hand off to network stack */
|
||||
if ( des0 & RHINE_RDES0_RXOK ) {
|
||||
DBGC2 ( rhn, "RHINE %p RX %d complete (length %zd)\n",
|
||||
rhn, rx_idx, len );
|
||||
netdev_rx ( netdev, iobuf );
|
||||
} else {
|
||||
DBGC ( rhn, "RHINE %p RX %d error (length %zd, DES0 "
|
||||
"%08x)\n", rhn, rx_idx, len, des0 );
|
||||
netdev_rx_err ( netdev, iobuf, -EIO );
|
||||
}
|
||||
rhn->rx.cons++;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Poll for completed and received packets
|
||||
*
|
||||
* @v netdev Network device
|
||||
*/
|
||||
static void rhine_poll ( struct net_device *netdev ) {
|
||||
struct rhine_nic *rhn = netdev->priv;
|
||||
uint8_t isr0;
|
||||
uint8_t isr1;
|
||||
|
||||
/* Read and acknowledge interrupts */
|
||||
isr0 = readb ( rhn->regs + RHINE_ISR0 );
|
||||
isr1 = readb ( rhn->regs + RHINE_ISR1 );
|
||||
if ( isr0 )
|
||||
writeb ( isr0, rhn->regs + RHINE_ISR0 );
|
||||
if ( isr1 )
|
||||
writeb ( isr1, rhn->regs + RHINE_ISR1 );
|
||||
|
||||
/* Report unexpected errors */
|
||||
if ( ( isr0 & ( RHINE_ISR0_MIBOVFL | RHINE_ISR0_PCIERR |
|
||||
RHINE_ISR0_RXRINGERR | RHINE_ISR0_TXRINGERR ) ) ||
|
||||
( isr1 & ( RHINE_ISR1_GPI | RHINE_ISR1_TXABORT |
|
||||
RHINE_ISR1_RXFIFOOVFL | RHINE_ISR1_RXFIFOUNFL |
|
||||
RHINE_ISR1_TXFIFOUNFL ) ) ) {
|
||||
DBGC ( rhn, "RHINE %p unexpected ISR0 %02x ISR1 %02x\n",
|
||||
rhn, isr0, isr1 );
|
||||
/* Report as a TX error */
|
||||
netdev_tx_err ( netdev, NULL, -EIO );
|
||||
}
|
||||
|
||||
/* Poll for TX completions, if applicable */
|
||||
if ( isr0 & ( RHINE_ISR0_TXDONE | RHINE_ISR0_TXERR ) )
|
||||
rhine_poll_tx ( netdev );
|
||||
|
||||
/* Poll for RX completions, if applicable */
|
||||
if ( isr0 & ( RHINE_ISR0_RXDONE | RHINE_ISR0_RXERR ) )
|
||||
rhine_poll_rx ( netdev );
|
||||
|
||||
/* Handle RX buffer exhaustion */
|
||||
if ( isr1 & RHINE_ISR1_RXNOBUF ) {
|
||||
rhine_poll_rx ( netdev );
|
||||
netdev_rx_err ( netdev, NULL, -ENOBUFS );
|
||||
}
|
||||
|
||||
/* Check link state, if applicable */
|
||||
if ( isr1 & RHINE_ISR1_PORTSTATE )
|
||||
rhine_check_link ( netdev );
|
||||
|
||||
/* Refill RX ring */
|
||||
rhine_refill_rx ( rhn );
|
||||
}
|
||||
|
||||
/**
|
||||
* Enable or disable interrupts
|
||||
*
|
||||
* @v netdev Network device
|
||||
* @v enable Interrupts should be enabled
|
||||
*/
|
||||
static void rhine_irq ( struct net_device *netdev, int enable ) {
|
||||
struct rhine_nic *nic = netdev->priv;
|
||||
|
||||
if ( enable ) {
|
||||
/* Enable interrupts */
|
||||
writeb ( 0xff, nic->regs + RHINE_IMR0 );
|
||||
writeb ( 0xff, nic->regs + RHINE_IMR1 );
|
||||
} else {
|
||||
/* Disable interrupts */
|
||||
writeb ( 0, nic->regs + RHINE_IMR0 );
|
||||
writeb ( 0, nic->regs + RHINE_IMR1 );
|
||||
}
|
||||
}
|
||||
|
||||
/** Rhine network device operations */
|
||||
static struct net_device_operations rhine_operations = {
|
||||
.open = rhine_open,
|
||||
.close = rhine_close,
|
||||
.transmit = rhine_transmit,
|
||||
.poll = rhine_poll,
|
||||
.irq = rhine_irq,
|
||||
};
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* PCI interface
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/**
|
||||
* Probe PCI device
|
||||
*
|
||||
* @v pci PCI device
|
||||
* @ret rc Return status code
|
||||
*/
|
||||
static int rhine_probe ( struct pci_device *pci ) {
|
||||
struct net_device *netdev;
|
||||
struct rhine_nic *rhn;
|
||||
uint8_t revision;
|
||||
unsigned int i;
|
||||
int rc;
|
||||
|
||||
/* Allocate and initialise net device */
|
||||
netdev = alloc_etherdev ( sizeof ( *rhn ) );
|
||||
if ( ! netdev ) {
|
||||
rc = -ENOMEM;
|
||||
goto err_alloc;
|
||||
}
|
||||
netdev_init ( netdev, &rhine_operations );
|
||||
rhn = netdev->priv;
|
||||
pci_set_drvdata ( pci, netdev );
|
||||
netdev->dev = &pci->dev;
|
||||
memset ( rhn, 0, sizeof ( *rhn ) );
|
||||
rhine_init_ring ( &rhn->tx, RHINE_TXDESC_NUM, RHINE_TXQUEUE_BASE );
|
||||
rhine_init_ring ( &rhn->rx, RHINE_RXDESC_NUM, RHINE_RXQUEUE_BASE );
|
||||
|
||||
/* Fix up PCI device */
|
||||
adjust_pci_device ( pci );
|
||||
|
||||
/* Map registers */
|
||||
rhn->regs = ioremap ( pci->membase, RHINE_BAR_SIZE );
|
||||
rhn->ioaddr = pci->ioaddr;
|
||||
DBGC ( rhn, "RHINE %p regs at %08lx, I/O at %04lx\n", rhn,
|
||||
pci->membase, pci->ioaddr );
|
||||
|
||||
/* Reset the NIC */
|
||||
if ( ( rc = rhine_reset ( rhn ) ) != 0 )
|
||||
goto err_reset;
|
||||
|
||||
/* Reload EEPROM */
|
||||
if ( ( rc = rhine_reload_eeprom ( rhn ) ) != 0 )
|
||||
goto err_reload_eeprom;
|
||||
|
||||
/* Read card revision and enable MMIO */
|
||||
pci_read_config_byte ( pci, PCI_REVISION, &revision );
|
||||
DBGC ( rhn, "RHINE %p revision %#02x detected\n", rhn, revision );
|
||||
rhine_enable_mmio ( rhn, revision );
|
||||
|
||||
/* Read MAC address */
|
||||
for ( i = 0 ; i < ETH_ALEN ; i++ )
|
||||
netdev->hw_addr[i] = readb ( rhn->regs + RHINE_MAC + i );
|
||||
|
||||
/* Initialise and reset MII interface */
|
||||
mii_init ( &rhn->mii, &rhine_mii_operations );
|
||||
if ( ( rc = mii_reset ( &rhn->mii ) ) != 0 ) {
|
||||
DBGC ( rhn, "RHINE %p could not reset MII: %s\n",
|
||||
rhn, strerror ( rc ) );
|
||||
goto err_mii_reset;
|
||||
}
|
||||
DBGC ( rhn, "RHINE PHY vendor %04x device %04x\n",
|
||||
rhine_mii_read ( &rhn->mii, 0x02 ),
|
||||
rhine_mii_read ( &rhn->mii, 0x03 ) );
|
||||
|
||||
/* Register network device */
|
||||
if ( ( rc = register_netdev ( netdev ) ) != 0 )
|
||||
goto err_register_netdev;
|
||||
|
||||
/* Set initial link state */
|
||||
rhine_check_link ( netdev );
|
||||
|
||||
return 0;
|
||||
|
||||
err_register_netdev:
|
||||
err_mii_reset:
|
||||
err_reload_eeprom:
|
||||
rhine_reset ( rhn );
|
||||
err_reset:
|
||||
netdev_nullify ( netdev );
|
||||
netdev_put ( netdev );
|
||||
err_alloc:
|
||||
return rc;
|
||||
}
|
||||
|
||||
/**
|
||||
* Remove PCI device
|
||||
*
|
||||
* @v pci PCI device
|
||||
*/
|
||||
static void rhine_remove ( struct pci_device *pci ) {
|
||||
struct net_device *netdev = pci_get_drvdata ( pci );
|
||||
struct rhine_nic *nic = netdev->priv;
|
||||
|
||||
/* Unregister network device */
|
||||
unregister_netdev ( netdev );
|
||||
|
||||
/* Reset card */
|
||||
rhine_reset ( nic );
|
||||
|
||||
/* Free network device */
|
||||
netdev_nullify ( netdev );
|
||||
netdev_put ( netdev );
|
||||
}
|
||||
|
||||
/** Rhine PCI device IDs */
|
||||
static struct pci_device_id rhine_nics[] = {
|
||||
PCI_ROM ( 0x1106, 0x3065, "dlink-530tx", "VIA VT6102", 0 ),
|
||||
PCI_ROM ( 0x1106, 0x3106, "vt6105", "VIA VT6105", 0 ),
|
||||
PCI_ROM ( 0x1106, 0x3043, "dlink-530tx-old", "VIA VT3043", 0 ),
|
||||
PCI_ROM ( 0x1106, 0x3053, "vt6105m", "VIA VT6105M", 0 ),
|
||||
PCI_ROM ( 0x1106, 0x6100, "via-rhine-old", "VIA 86C100A", 0 )
|
||||
};
|
||||
|
||||
/** Rhine PCI driver */
|
||||
struct pci_driver rhine_driver __pci_driver = {
|
||||
.ids = rhine_nics,
|
||||
.id_count = ( sizeof ( rhine_nics ) / sizeof ( rhine_nics[0] ) ),
|
||||
.probe = rhine_probe,
|
||||
.remove = rhine_remove,
|
||||
};
|
||||
250
src/drivers/net/rhine.h
Normal file
250
src/drivers/net/rhine.h
Normal file
@ -0,0 +1,250 @@
|
||||
#ifndef _RHINE_H
|
||||
#define _RHINE_H
|
||||
|
||||
/** @file
|
||||
*
|
||||
* VIA Rhine network driver
|
||||
*
|
||||
*/
|
||||
|
||||
FILE_LICENCE ( GPL2_OR_LATER );
|
||||
|
||||
/** Rhine BAR size */
|
||||
#define RHINE_BAR_SIZE 256
|
||||
|
||||
/** Default timeout */
|
||||
#define RHINE_TIMEOUT_US 10000
|
||||
|
||||
/** Rhine descriptor format */
|
||||
struct rhine_descriptor {
|
||||
uint32_t des0;
|
||||
uint32_t des1;
|
||||
uint32_t buffer;
|
||||
uint32_t next;
|
||||
} __attribute__ (( packed ));
|
||||
|
||||
#define RHINE_DES0_OWN (1 << 31) /*< Owned descriptor */
|
||||
#define RHINE_DES1_IC (1 << 23) /*< Generate interrupt */
|
||||
#define RHINE_TDES1_EDP (1 << 22) /*< End of packet */
|
||||
#define RHINE_TDES1_STP (1 << 21) /*< Start of packet */
|
||||
#define RHINE_TDES1_TCPCK (1 << 20) /*< HW TCP checksum */
|
||||
#define RHINE_TDES1_UDPCK (1 << 19) /*< HW UDP checksum */
|
||||
#define RHINE_TDES1_IPCK (1 << 18) /*< HW IP checksum */
|
||||
#define RHINE_TDES1_TAG (1 << 17) /*< Tagged frame */
|
||||
#define RHINE_TDES1_CRC (1 << 16) /*< No CRC */
|
||||
#define RHINE_DES1_CHAIN (1 << 15) /*< Chained descriptor */
|
||||
#define RHINE_DES1_SIZE(_x) ((_x) & 0x7ff) /*< Frame size */
|
||||
#define RHINE_DES0_GETSIZE(_x) (((_x) >> 16) & 0x7ff)
|
||||
|
||||
#define RHINE_RDES0_RXOK (1 << 15)
|
||||
#define RHINE_RDES0_VIDHIT (1 << 14)
|
||||
#define RHINE_RDES0_MAR (1 << 13)
|
||||
#define RHINE_RDES0_BAR (1 << 12)
|
||||
#define RHINE_RDES0_PHY (1 << 11)
|
||||
#define RHINE_RDES0_CHN (1 << 10)
|
||||
#define RHINE_RDES0_STP (1 << 9)
|
||||
#define RHINE_RDES0_EDP (1 << 8)
|
||||
#define RHINE_RDES0_BUFF (1 << 7)
|
||||
#define RHINE_RDES0_FRAG (1 << 6)
|
||||
#define RHINE_RDES0_RUNT (1 << 5)
|
||||
#define RHINE_RDES0_LONG (1 << 4)
|
||||
#define RHINE_RDES0_FOV (1 << 3)
|
||||
#define RHINE_RDES0_FAE (1 << 2)
|
||||
#define RHINE_RDES0_CRCE (1 << 1)
|
||||
#define RHINE_RDES0_RERR (1 << 0)
|
||||
|
||||
#define RHINE_TDES0_TERR (1 << 15)
|
||||
#define RHINE_TDES0_UDF (1 << 11)
|
||||
#define RHINE_TDES0_CRS (1 << 10)
|
||||
#define RHINE_TDES0_OWC (1 << 9)
|
||||
#define RHINE_TDES0_ABT (1 << 8)
|
||||
#define RHINE_TDES0_CDH (1 << 7)
|
||||
#define RHINE_TDES0_COLS (1 << 4)
|
||||
#define RHINE_TDES0_NCR(_x) ((_x) & 0xf)
|
||||
|
||||
#define RHINE_RING_ALIGN 4
|
||||
|
||||
/** Rhine descriptor rings sizes */
|
||||
#define RHINE_RXDESC_NUM 4
|
||||
#define RHINE_TXDESC_NUM 8
|
||||
#define RHINE_RX_MAX_LEN 1536
|
||||
|
||||
/** Rhine MAC address registers */
|
||||
#define RHINE_MAC 0x00
|
||||
|
||||
/** Receive control register */
|
||||
#define RHINE_RCR 0x06
|
||||
#define RHINE_RCR_FIFO_TRSH(_x) (((_x) & 0x7) << 5) /*< RX FIFO threshold */
|
||||
#define RHINE_RCR_PHYS_ACCEPT (1 << 4) /*< Accept matching PA */
|
||||
#define RHINE_RCR_BCAST_ACCEPT (1 << 3) /*< Accept broadcast */
|
||||
#define RHINE_RCR_MCAST_ACCEPT (1 << 2) /*< Accept multicast */
|
||||
#define RHINE_RCR_RUNT_ACCEPT (1 << 1) /*< Accept runt frames */
|
||||
#define RHINE_RCR_ERR_ACCEPT (1 << 0) /*< Accept erroneous frames */
|
||||
|
||||
/** Transmit control register */
|
||||
#define RHINE_TCR 0x07
|
||||
#define RHINE_TCR_LOOPBACK(_x) (((_x) & 0x3) << 1) /*< Transmit loop mode */
|
||||
#define RHINE_TCR_TAGGING (1 << 0) /*< 802.1P/Q packet tagging */
|
||||
|
||||
/** Command 0 register */
|
||||
#define RHINE_CR0 0x08
|
||||
#define RHINE_CR0_RXSTART (1 << 6)
|
||||
#define RHINE_CR0_TXSTART (1 << 5)
|
||||
#define RHINE_CR0_TXEN (1 << 4) /*< Transmit enable */
|
||||
#define RHINE_CR0_RXEN (1 << 3) /*< Receive enable */
|
||||
#define RHINE_CR0_STOPNIC (1 << 2) /*< Stop NIC */
|
||||
#define RHINE_CR0_STARTNIC (1 << 1) /*< Start NIC */
|
||||
|
||||
/** Command 1 register */
|
||||
#define RHINE_CR1 0x09
|
||||
#define RHINE_CR1_RESET (1 << 7) /*< Software reset */
|
||||
#define RHINE_CR1_RXPOLL (1 << 6) /*< Receive poll demand */
|
||||
#define RHINE_CR1_TXPOLL (1 << 5) /*< Xmit poll demand */
|
||||
#define RHINE_CR1_AUTOPOLL (1 << 3) /*< Disable autopoll */
|
||||
#define RHINE_CR1_FDX (1 << 2) /*< Full duplex */
|
||||
#define RIHNE_CR1_ACCUNI (1 << 1) /*< Disable accept unicast */
|
||||
|
||||
/** Transmit queue wake register */
|
||||
#define RHINE_TXQUEUE_WAKE 0x0a
|
||||
|
||||
/** Interrupt service 0 */
|
||||
#define RHINE_ISR0 0x0c
|
||||
#define RHINE_ISR0_MIBOVFL (1 << 7)
|
||||
#define RHINE_ISR0_PCIERR (1 << 6)
|
||||
#define RHINE_ISR0_RXRINGERR (1 << 5)
|
||||
#define RHINE_ISR0_TXRINGERR (1 << 4)
|
||||
#define RHINE_ISR0_TXERR (1 << 3)
|
||||
#define RHINE_ISR0_RXERR (1 << 2)
|
||||
#define RHINE_ISR0_TXDONE (1 << 1)
|
||||
#define RHINE_ISR0_RXDONE (1 << 0)
|
||||
|
||||
/** Interrupt service 1 */
|
||||
#define RHINE_ISR1 0x0d
|
||||
#define RHINE_ISR1_GPI (1 << 7)
|
||||
#define RHINE_ISR1_PORTSTATE (1 << 6)
|
||||
#define RHINE_ISR1_TXABORT (1 << 5)
|
||||
#define RHINE_ISR1_RXNOBUF (1 << 4)
|
||||
#define RHINE_ISR1_RXFIFOOVFL (1 << 3)
|
||||
#define RHINE_ISR1_RXFIFOUNFL (1 << 2)
|
||||
#define RHINE_ISR1_TXFIFOUNFL (1 << 1)
|
||||
#define RHINE_ISR1_EARLYRX (1 << 0)
|
||||
|
||||
/** Interrupt enable mask register 0 */
|
||||
#define RHINE_IMR0 0x0e
|
||||
|
||||
/** Interrupt enable mask register 1 */
|
||||
#define RHINE_IMR1 0x0f
|
||||
|
||||
/** RX queue descriptor base address */
|
||||
#define RHINE_RXQUEUE_BASE 0x18
|
||||
|
||||
/** TX queue 0 descriptor base address */
|
||||
#define RHINE_TXQUEUE_BASE 0x1c
|
||||
|
||||
/** MII configuration */
|
||||
#define RHINE_MII_CFG 0x6c
|
||||
|
||||
/** MII status register */
|
||||
#define RHINE_MII_SR 0x6d
|
||||
#define RHINE_MII_SR_PHYRST (1 << 7) /*< PHY reset */
|
||||
#define RHINE_MII_SR_LINKNWAY (1 << 4) /*< Link status after N-Way */
|
||||
#define RHINE_MII_SR_PHYERR (1 << 3) /*< PHY device error */
|
||||
#define RHINE_MII_SR_DUPLEX (1 << 2) /*< Duplex mode after N-Way */
|
||||
#define RHINE_MII_SR_LINKPOLL (1 << 1) /*< Link status after poll */
|
||||
#define RHINE_MII_SR_LINKSPD (1 << 0) /*< Link speed after N-Way */
|
||||
|
||||
/** MII bus control 0 register */
|
||||
#define RHINE_MII_BCR0 0x6e
|
||||
|
||||
/** MII bus control 1 register */
|
||||
#define RHINE_MII_BCR1 0x6f
|
||||
|
||||
/** MII control register */
|
||||
#define RHINE_MII_CR 0x70
|
||||
#define RHINE_MII_CR_AUTOPOLL (1 << 7) /*< MII auto polling */
|
||||
#define RHINE_MII_CR_RDEN (1 << 6) /*< PHY read enable */
|
||||
#define RHINE_MII_CR_WREN (1 << 5) /*< PHY write enable */
|
||||
#define RHINE_MII_CR_DIRECT (1 << 4) /*< Direct programming mode */
|
||||
#define RHINE_MII_CR_MDIOOUT (1 << 3) /*< MDIO output enable */
|
||||
|
||||
/** MII port address */
|
||||
#define RHINE_MII_ADDR 0x71
|
||||
#define RHINE_MII_ADDR_MSRCEN (1 << 6)
|
||||
#define RHINE_MII_ADDR_MDONE (1 << 5)
|
||||
|
||||
/** MII read/write data */
|
||||
#define RHINE_MII_RDWR 0x72
|
||||
|
||||
/** EERPOM control/status register */
|
||||
#define RHINE_EEPROM_CTRL 0x74
|
||||
#define RHINE_EEPROM_CTRL_STATUS (1 << 7) /*< EEPROM status */
|
||||
#define RHINE_EEPROM_CTRL_RELOAD (1 << 5) /*< EEPROM reload */
|
||||
|
||||
/** Chip configuration A */
|
||||
#define RHINE_CHIPCFG_A 0x78
|
||||
/* MMIO enable. Only valid for Rhine I. Reserved on later boards */
|
||||
#define RHINE_CHIPCFG_A_MMIO (1 << 5)
|
||||
|
||||
/** Chip configuration B */
|
||||
#define RHINE_CHIPCFG_B 0x79
|
||||
|
||||
/** Chip configuation C */
|
||||
#define RHINE_CHIPCFG_C 0x7a
|
||||
|
||||
/** Chip configuration D */
|
||||
#define RHINE_CHIPCFG_D 0x7b
|
||||
/* MMIO enable. Only valid on Rhine II and later. GPIOEN on Rhine I */
|
||||
#define RHINE_CHIPCFG_D_MMIO (1 << 7)
|
||||
|
||||
#define RHINE_REVISION_OLD 0x20
|
||||
|
||||
/** A VIA Rhine descriptor ring */
|
||||
struct rhine_ring {
|
||||
/** Descriptors */
|
||||
struct rhine_descriptor *desc;
|
||||
/** Producer index */
|
||||
unsigned int prod;
|
||||
/** Consumer index */
|
||||
unsigned int cons;
|
||||
|
||||
/** Number of descriptors */
|
||||
unsigned int count;
|
||||
/** Register address */
|
||||
unsigned int reg;
|
||||
};
|
||||
|
||||
/**
|
||||
* Initialise descriptor ring
|
||||
*
|
||||
* @v ring Descriptor ring
|
||||
* @v count Number of descriptors (must be a power of 2)
|
||||
* @v reg Register address
|
||||
*/
|
||||
static inline __attribute__ (( always_inline)) void
|
||||
rhine_init_ring ( struct rhine_ring *ring, unsigned int count,
|
||||
unsigned int reg ) {
|
||||
ring->count = count;
|
||||
ring->reg = reg;
|
||||
}
|
||||
|
||||
/** A VIA Rhine network card */
|
||||
struct rhine_nic {
|
||||
/** I/O address (some PIO access is always required) */
|
||||
unsigned long ioaddr;
|
||||
/** Registers */
|
||||
void *regs;
|
||||
/** Cached value of CR1 (to avoid read-modify-write on fast path) */
|
||||
uint8_t cr1;
|
||||
|
||||
/** MII interface */
|
||||
struct mii_interface mii;
|
||||
|
||||
/** Transmit descriptor ring */
|
||||
struct rhine_ring tx;
|
||||
/** Receive descriptor ring */
|
||||
struct rhine_ring rx;
|
||||
/** Receive I/O buffers */
|
||||
struct io_buffer *rx_iobuf[RHINE_RXDESC_NUM];
|
||||
};
|
||||
|
||||
#endif /* _RHINE_H */
|
||||
File diff suppressed because it is too large
Load Diff
@ -113,7 +113,7 @@ FILE_LICENCE ( GPL2_OR_LATER );
|
||||
#define ERRFILE_sundance ( ERRFILE_DRIVER | 0x00410000 )
|
||||
#define ERRFILE_tlan ( ERRFILE_DRIVER | 0x00420000 )
|
||||
#define ERRFILE_tulip ( ERRFILE_DRIVER | 0x00430000 )
|
||||
#define ERRFILE_via_rhine ( ERRFILE_DRIVER | 0x00440000 )
|
||||
#define ERRFILE_rhine ( ERRFILE_DRIVER | 0x00440000 )
|
||||
#define ERRFILE_via_velocity ( ERRFILE_DRIVER | 0x00450000 )
|
||||
#define ERRFILE_w89c840 ( ERRFILE_DRIVER | 0x00460000 )
|
||||
#define ERRFILE_ipoib ( ERRFILE_DRIVER | 0x00470000 )
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user