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Forward-port start-of-day fixes from 5.4 tree
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@ -771,16 +771,28 @@ static int mentormac_mdio_read ( struct efab_nic *efab, int phy_id,
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#define EF1_EVT3_REG 0x38
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/** EEPROM access */
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#define EF1_EEPROM_REG 0x0040
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#define EF1_EEPROM_REG 0x40
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#define EF1_EEPROM_SDA_LBN 31
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#define EF1_EEPROM_SDA_WIDTH 1
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#define EF1_EEPROM_SCL_LBN 30
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#define EF1_EEPROM_SCL_WIDTH 1
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#define EF1_JTAG_DISCONNECT_LBN 17
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#define EF1_JTAG_DISCONNECT_WIDTH 1
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#define EF1_EEPROM_LBN 0
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#define EF1_EEPROM_WIDTH 32
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/** Control register 2 */
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#define EF1_CTL2_REG 0x4c
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#define EF1_PLL_TRAP_LBN 31
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#define EF1_PLL_TRAP_WIDTH 1
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#define EF1_MEM_MAP_4MB_LBN 11
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#define EF1_MEM_MAP_4MB_WIDTH 1
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#define EF1_EV_INTR_CLR_WRITE_LBN 6
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#define EF1_EV_INTR_CLR_WRITE_WIDTH 1
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#define EF1_BURST_MERGE_LBN 5
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#define EF1_BURST_MERGE_WIDTH 1
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#define EF1_CLEAR_NULL_PAD_LBN 4
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#define EF1_CLEAR_NULL_PAD_WIDTH 1
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#define EF1_SW_RESET_LBN 2
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#define EF1_SW_RESET_WIDTH 1
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#define EF1_INTR_AFTER_EVENT_LBN 1
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@ -1083,15 +1095,20 @@ static int ef1002_init_nic ( struct efab_nic *efab ) {
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/* General control register 0 */
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ef1002_readl ( efab, ®, EF1_CTR_GEN_STATUS0_REG );
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EFAB_SET_DWORD_FIELD ( reg, EF1_MASTER_EVENTS, 0 );
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EFAB_SET_DWORD_FIELD ( reg, EF1_TX_ENGINE_EN, 0 );
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EFAB_SET_DWORD_FIELD ( reg, EF1_RX_ENGINE_EN, 0 );
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EFAB_SET_DWORD_FIELD ( reg, EF1_CAM_ENABLE, 1 );
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ef1002_writel ( efab, ®, EF1_CTR_GEN_STATUS0_REG );
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udelay ( 1000 );
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/* General control register 2 */
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ef1002_readl ( efab, ®, EF1_CTL2_REG );
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EFAB_SET_DWORD_FIELD ( reg, EF1_INTR_AFTER_EVENT, 1 );
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EFAB_SET_DWORD_FIELD ( reg, EF1_EV_INTR_CLR_WRITE, 0 );
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EFAB_SET_DWORD_FIELD ( reg, EF1_PLL_TRAP, 1 );
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EFAB_SET_DWORD_FIELD ( reg, EF1_MEM_MAP_4MB, 0 );
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EFAB_SET_DWORD_FIELD ( reg, EF1_EV_INTR_CLR_WRITE, 0 );
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EFAB_SET_DWORD_FIELD ( reg, EF1_BURST_MERGE, 0 );
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EFAB_SET_DWORD_FIELD ( reg, EF1_CLEAR_NULL_PAD, 1 );
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EFAB_SET_DWORD_FIELD ( reg, EF1_INTR_AFTER_EVENT, 1 );
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ef1002_writel ( efab, ®, EF1_CTL2_REG );
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udelay ( 1000 );
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@ -1111,6 +1128,17 @@ static int ef1002_init_nic ( struct efab_nic *efab ) {
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ef1002_writel ( efab, ®, EF1_DMA_TX_CSR_REG );
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udelay ( 1000 );
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/* Disconnect the JTAG chain. Read-modify-write is impossible
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* on the I2C control bits, since reading gives the state of
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* the line inputs rather than the last written state.
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*/
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ef1002_readl ( efab, ®, EF1_EEPROM_REG );
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EFAB_SET_DWORD_FIELD ( reg, EF1_EEPROM_SDA, 1 );
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EFAB_SET_DWORD_FIELD ( reg, EF1_EEPROM_SCL, 1 );
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EFAB_SET_DWORD_FIELD ( reg, EF1_JTAG_DISCONNECT, 1 );
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ef1002_writel ( efab, ®, EF1_EEPROM_REG );
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udelay ( 10 );
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/* Flush descriptor queues */
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EFAB_ZERO_DWORD ( reg );
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ef1002_writel ( efab, ®, EF1_RX_DESC_FIFO_FLUSH );
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