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https://github.com/xcat2/xNBA.git
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Natsemi commented and almost done
This commit is contained in:
Udayan Kumar
parent
4f2fab2e14
commit
83dd194330
@ -50,13 +50,13 @@
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/*
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02 JUL 2007 Udayan Kumar 1.2 ported the driver from etherboot to gPXE API
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Added a circular buffer for transmit and receive.
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transmit routine will not wait for transmission to finish
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poll routine deals with it.
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Added a circular buffer for transmit and receive.
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transmit routine will not wait for transmission to finish.
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poll routine deals with it.
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13 Dec 2003 timlegge 1.1 Enabled Multicast Support
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29 May 2001 mdc 1.0
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Initial Release. Tested with Netgear FA311 and FA312 boards
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13 Dec 2003 timlegge 1.1 Enabled Multicast Support
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29 May 2001 mdc 1.0
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Initial Release. Tested with Netgear FA311 and FA312 boards
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*/
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@ -119,7 +119,6 @@ struct natsemi_nic {
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struct nvo_block nvo;
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};
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/* NATSEMI: Offsets to the device registers.
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* Unlike software-only systems, device drivers interact with complex hardware.
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* It's not useful to define symbolic names for every register bit in the
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@ -154,8 +153,8 @@ enum register_offsets {
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PhyStatus = 0xC0,
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MIntrCtrl = 0xC4,
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MIntrStatus = 0xC8,
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/* These are from the spec, around page 78... on a separate table. */
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/* These are from the spec, around page 78... on a separate table.
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*/
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PGSEL = 0xCC,
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PMDCSR = 0xE4,
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TSTDAT = 0xFC,
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@ -166,10 +165,8 @@ enum register_offsets {
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};
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/* Bit in ChipCmd. */
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/* Bit in ChipCmd.
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*/
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enum ChipCmdBits {
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ChipReset = 0x100,
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RxReset = 0x20,
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@ -180,8 +177,8 @@ enum ChipCmdBits {
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TxOn = 0x01
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};
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/* Bits in the RxMode register. */
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/* Bits in the RxMode register.
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*/
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enum rx_mode_bits {
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AcceptErr = 0x20,
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AcceptRunt = 0x10,
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@ -193,7 +190,8 @@ enum rx_mode_bits {
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RxFilterEnable = 0x80000000
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};
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/* Bits in network_desc.status */
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/* Bits in network_desc.status
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*/
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enum desc_status_bits {
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DescOwn = 0x80000000,
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DescMore = 0x40000000,
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@ -203,8 +201,8 @@ enum desc_status_bits {
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RxTooLong = 0x00400000
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};
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/*Bits in Interrupt Mask register */
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/*Bits in Interrupt Mask register
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*/
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enum Intr_mask_register_bits {
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RxOk = 0x001,
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RxErr = 0x004,
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@ -212,19 +210,19 @@ enum Intr_mask_register_bits {
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TxErr = 0x100
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};
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/* EEPROM access , values are devices specific*/
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/* EEPROM access , values are devices specific
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*/
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#define EE_CS 0x08 /* EEPROM chip select */
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#define EE_SK 0x04 /* EEPROM shift clock */
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#define EE_DI 0x01 /* Data in */
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#define EE_DO 0x02 /* Data out */
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/* Offsets within EEPROM (these are word offsets) */
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/* Offsets within EEPROM (these are word offsets)
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*/
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#define EE_MAC 7
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#define EE_REG EECtrl
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static uint32_t SavedClkRun;
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static const uint8_t nat_ee_bits[] = {
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[SPI_BIT_SCLK] = EE_SK,
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[SPI_BIT_MOSI] = EE_DI,
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@ -277,13 +275,15 @@ static struct nvo_fragment nat_nvo_fragments[] = {
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*/
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void nat_init_eeprom ( struct natsemi_nic *nat ) {
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/* Initialise three-wire bus */
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/* Initialise three-wire bus
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*/
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nat->spibit.basher.op = &nat_basher_ops;
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nat->spibit.bus.mode = SPI_MODE_THREEWIRE;
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nat->spibit.endianness = SPI_BIT_LITTLE_ENDIAN;
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init_spi_bit_basher ( &nat->spibit );
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/*natsemi DP 83815 only supports at93c46 */
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/*natsemi DP 83815 only supports at93c46
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*/
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init_at93c46 ( &nat->eeprom, 16 );
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nat->eeprom.bus = &nat->spibit.bus;
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@ -301,7 +301,8 @@ static struct nvo_fragment nat_nvo_fragments[] = {
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static void nat_reset ( struct natsemi_nic *nat ) {
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int i;
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/* Reset chip */
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/* Reset chip
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*/
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outl ( ChipReset, nat->ioaddr + ChipCmd );
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mdelay ( 10 );
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nat->tx_dirty=0;
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@ -317,7 +318,8 @@ static void nat_reset ( struct natsemi_nic *nat ) {
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outl(TxOff|RxOff, nat->ioaddr + ChipCmd);
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/* Restore PME enable bit */
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/* Restore PME enable bit
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*/
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outl(SavedClkRun, nat->ioaddr + ClkRun);
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}
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@ -342,13 +344,16 @@ static int nat_open ( struct net_device *netdev ) {
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SavedClkRun = inl(nat->ioaddr + ClkRun);
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outl(SavedClkRun & ~0x100, nat->ioaddr + ClkRun);
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/* Setting up Mac address in the NIC */
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/* Setting up Mac address in the NIC
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*/
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for ( i = 0 ; i < ETH_ALEN ; i+=2 ) {
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outl(i,nat->ioaddr+RxFilterAddr);
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outw ( netdev->ll_addr[i] + (netdev->ll_addr[i+1]<<8), nat->ioaddr +RxFilterData);
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outw ( netdev->ll_addr[i] + (netdev->ll_addr[i+1]<<8),
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nat->ioaddr +RxFilterData);
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}
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/*Set up the Tx Ring */
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/*Set up the Tx Ring
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*/
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nat->tx_cur=0;
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nat->tx_dirty=0;
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for (i=0;i<TX_RING_SIZE;i++) {
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@ -357,7 +362,8 @@ static int nat_open ( struct net_device *netdev ) {
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nat->tx[i].bufptr = 0;
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}
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/* Set up RX ring */
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/* Set up RX ring
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*/
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nat->rx_cur=0;
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for (i=0;i<NUM_RX_DESC;i++) {
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@ -369,16 +375,22 @@ static int nat_open ( struct net_device *netdev ) {
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nat->rx[i].bufptr = virt_to_bus(nat->iobuf[i]->data);
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}
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/* load Receive Descriptor Register */
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/* load Receive Descriptor Register
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*/
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outl(virt_to_bus(&nat->rx[0]), nat->ioaddr + RxRingPtr);
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DBG("Natsemi Rx descriptor loaded with: %X\n",(unsigned int)inl(nat->ioaddr+RxRingPtr));
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DBG("Natsemi Rx descriptor loaded with: %X\n",
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(unsigned int)inl(nat->ioaddr+RxRingPtr));
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/* setup Tx ring */
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/* setup Tx ring
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*/
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outl(virt_to_bus(&nat->tx[0]),nat->ioaddr+TxRingPtr);
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DBG("Natsemi Tx descriptor loaded with: %X\n",(unsigned int)inl(nat->ioaddr+TxRingPtr));
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DBG("Natsemi Tx descriptor loaded with: %X\n",
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(unsigned int)inl(nat->ioaddr+TxRingPtr));
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/* Enables RX */
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outl(RxFilterEnable|AcceptBroadcast|AcceptAllMulticast|AcceptMyPhys, nat->ioaddr+RxFilterAddr);
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/* Enables RX
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*/
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outl(RxFilterEnable|AcceptBroadcast|AcceptAllMulticast|AcceptMyPhys,
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nat->ioaddr+RxFilterAddr);
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/* Initialize other registers.
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* Configure the PCI bus bursts and FIFO thresholds.
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@ -394,10 +406,12 @@ static int nat_open ( struct net_device *netdev ) {
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outl(tx_config, nat->ioaddr + TxConfig);
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outl(rx_config, nat->ioaddr + RxConfig);
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/*start the receiver */
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/*start the receiver
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*/
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outl(RxOn, nat->ioaddr + ChipCmd);
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/*enable interrupts*/
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/*enable interrupts
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*/
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outl((RxOk|RxErr|TxOk|TxErr),nat->ioaddr + IntrMask);
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//outl(1,nat->ioaddr +IntrEnable);
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@ -414,15 +428,18 @@ static void nat_close ( struct net_device *netdev ) {
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int i;
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/* Reset the hardware to disable everything in one go */
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/* Reset the hardware to disable everything in one go
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*/
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nat_reset ( nat );
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/* Free RX ring */
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/* Free RX ring
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*/
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for (i=0;i<NUM_RX_DESC;i++) {
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free_iob( nat->iobuf[i] );
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}
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/* disable interrupts */
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/* disable interrupts
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*/
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//outl(0,nat->ioaddr + IntrMask) ;
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}
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@ -436,28 +453,34 @@ static void nat_close ( struct net_device *netdev ) {
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static int nat_transmit ( struct net_device *netdev, struct io_buffer *iobuf ) {
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struct natsemi_nic *nat = netdev->priv;
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/* check for space in TX ring */
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/* check for space in TX ring
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*/
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if (nat->tx[nat->tx_cur].cmdsts !=0) {
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DBG( "TX overflow\n" );
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return -ENOBUFS;
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}
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/* to be used in netdev_tx_complete*/
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/* to be used in netdev_tx_complete
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*/
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nat->tx_iobuf[nat->tx_cur]=iobuf;
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/* Pad and align packet */
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iob_pad ( iobuf, ETH_ZLEN );
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/* Pad and align packet has been ignored because its not required here
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* iob_pad ( iobuf, ETH_ZLEN ); can be used to achieve it
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*/
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/* Add to TX ring */
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/* Add to TX ring
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*/
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DBG ( "TX id %d at %lx+%x\n", nat->tx_cur,
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virt_to_bus ( &iobuf->data ), iob_len ( iobuf ) );
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nat->tx[nat->tx_cur].bufptr = virt_to_bus(iobuf->data);
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nat->tx[nat->tx_cur].cmdsts= iob_len(iobuf)|OWN;
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/* increment the circular buffer pointer to the next buffer location */
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/* increment the circular buffer pointer to the next buffer location
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*/
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nat->tx_cur=(nat->tx_cur+1) % TX_RING_SIZE;
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/*start the transmitter */
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/*start the transmitter
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*/
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outl(TxOn, nat->ioaddr + ChipCmd);
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return 0;
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@ -479,12 +502,14 @@ static void nat_poll ( struct net_device *netdev, unsigned int rx_quota ) {
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int i;
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//outl(1,nat->ioaddr +IntrEnable);
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/* read the interrupt register */
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/* read the interrupt register
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*/
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intr_status=inl(nat->ioaddr+IntrStatus);
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if(!intr_status)
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goto end;
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/* check the status of packets given to card for transmission */
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/* check the status of packets given to card for transmission
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*/
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DBG("Intr status %X\n",intr_status);
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i=nat->tx_dirty;
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@ -493,10 +518,12 @@ static void nat_poll ( struct net_device *netdev, unsigned int rx_quota ) {
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DBG("value of tx_dirty = %d tx_cur=%d status=%X\n",
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nat->tx_dirty,nat->tx_cur,status);
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/* check if current packet has been transmitted or not */
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/* check if current packet has been transmitted or not
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*/
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if(status & OWN)
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break;
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/* Check if any errors in transmission */
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/* Check if any errors in transmission
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*/
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if (! (status & DescPktOK)) {
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DBG("Error in sending Packet status:%X\n",
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(unsigned int)status);
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@ -505,17 +532,20 @@ static void nat_poll ( struct net_device *netdev, unsigned int rx_quota ) {
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DBG("Success in transmitting Packet\n");
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netdev_tx_complete(netdev,nat->tx_iobuf[nat->tx_dirty]);
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}
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/* setting cmdsts zero, indicating that it can be reused */
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/* setting cmdsts zero, indicating that it can be reused
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*/
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nat->tx[nat->tx_dirty].cmdsts=0;
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nat->tx_dirty=(nat->tx_dirty +1) % TX_RING_SIZE;
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i=(i+1) % TX_RING_SIZE;
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}
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/* Handle received packets */
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/* Handle received packets
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*/
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rx_status=(unsigned int)nat->rx[nat->rx_cur].cmdsts;
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while (rx_quota && (rx_status & OWN)) {
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rx_len= (rx_status & DSIZE) - CRC_SIZE;
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/*check for the corrupt packet */
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/*check for the corrupt packet
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*/
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if((rx_status & (DescMore|DescPktOK|RxTooLong)) != DescPktOK) {
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DBG("natsemi_poll: Corrupted packet received, "
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"buffer status = %X ^ %X \n",rx_status,
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@ -524,12 +554,14 @@ static void nat_poll ( struct net_device *netdev, unsigned int rx_quota ) {
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} else {
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rx_iob = alloc_iob(rx_len);
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if(!rx_iob)
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/* leave packet for next call to poll*/
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/* leave packet for next call to poll
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*/
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goto end;
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memcpy(iob_put(rx_iob,rx_len),
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nat->iobuf[nat->rx_cur]->data,rx_len);
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DBG("received packet\n");
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/* add to the receive queue. */
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/* add to the receive queue.
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*/
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netdev_rx(netdev,rx_iob);
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rx_quota--;
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}
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@ -540,7 +572,8 @@ static void nat_poll ( struct net_device *netdev, unsigned int rx_quota ) {
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end:
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/* re-enable the potentially idle receive state machine */
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/* re-enable the potentially idle receive state machine
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*/
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outl(RxOn, nat->ioaddr + ChipCmd);
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// outl(1,nat->ioaddr +IntrEnable);
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}
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@ -570,7 +603,8 @@ static int nat_probe ( struct pci_device *pci,
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uint8_t last=0;
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uint8_t last1=0;
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/* Allocate net device */
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/* Allocate net device
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*/
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netdev = alloc_etherdev ( sizeof ( *nat ) );
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if ( ! netdev )
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return -ENOMEM;
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@ -581,10 +615,12 @@ static int nat_probe ( struct pci_device *pci,
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memset ( nat, 0, sizeof ( *nat ) );
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nat->ioaddr = pci->ioaddr;
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/* Fix up PCI device */
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/* Fix up PCI device
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*/
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adjust_pci_device ( pci );
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/* Reset the NIC, set up EEPROM access and read MAC address */
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/* Reset the NIC, set up EEPROM access and read MAC address
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*/
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nat_reset ( nat );
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nat_init_eeprom ( nat );
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nvs_read ( &nat->eeprom.nvs, EE_MAC, ll_addr_encoded, ETH_ALEN );
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@ -598,24 +634,14 @@ static int nat_probe ( struct pci_device *pci,
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last=(ll_addr_encoded[i+1]>>7);
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netdev->ll_addr[i+1]=(ll_addr_encoded[i+1]<<1)+last1;
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}
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/* TODO remove the block below */
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DBG("Contents of the EEPROM\n");
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uint8_t eetest[108];
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nvs_read(&nat->eeprom.nvs,0,eetest,108);
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DBG_HD(&eetest,108);
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/* Point to NIC specific routines */
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/*
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netdev->open = nat_open;
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netdev->close = nat_close;
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netdev->transmit = nat_transmit;
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netdev->poll = nat_poll;
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*/
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/* Register network device */
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/* Register network device
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*/
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if ( ( rc = register_netdev ( netdev ) ) != 0 )
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goto err_register_netdev;
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/* Register non-volatile storage */
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/* Register non-volatile storage
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*/
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if ( nat->nvo.nvs ) {
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if ( ( rc = nvo_register ( &nat->nvo ) ) != 0 )
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goto err_register_nvo;
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@ -627,9 +653,11 @@ static int nat_probe ( struct pci_device *pci,
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err_register_nvo:
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unregister_netdev ( netdev );
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err_register_netdev:
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/* Disable NIC */
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/* Disable NIC
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*/
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nat_reset ( nat );
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/* Free net device */
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/* Free net device
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*/
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netdev_put ( netdev );
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return rc;
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}
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