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https://github.com/xcat2/xNBA.git
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[tg3] Added support for tg3-5754.
In tg3_chip_reset(), the PCI_EXPRESS change is taken from the Linux tg3 driver. I am not sure what exactly it does (it is not documented in the Linux driver), but it is necessary for the NIC to work correctly.
This commit is contained in:
Andrew Schran
Michael Brown
parent
c302eeda5a
commit
6b58992318
@ -1431,7 +1431,8 @@ static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, uint32_t enable_bit
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unsigned int i;
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uint32_t val;
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) {
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switch(ofs) {
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case RCVLSC_MODE:
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case DMAC_MODE:
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@ -1439,7 +1440,7 @@ static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, uint32_t enable_bit
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case BUFMGR_MODE:
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case MEMARB_MODE:
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/* We can't enable/disable these bits of the
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* 5705, just say success.
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* 5705 or 5787, just say success.
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*/
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return 0;
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default:
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@ -1470,6 +1471,7 @@ static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, uint32_t enable_bit
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static int tg3_abort_hw(struct tg3 *tp)
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{
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int i, err;
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uint32_t val;
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tg3_disable_ints(tp);
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@ -1513,8 +1515,14 @@ static int tg3_abort_hw(struct tg3 *tp)
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err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE);
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err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE);
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tw32(FTQ_RESET, 0xffffffff);
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tw32(FTQ_RESET, 0x00000000);
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val = tr32(FTQ_RESET);
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val |= FTQ_RESET_DMA_READ_QUEUE | FTQ_RESET_DMA_HIGH_PRI_READ |
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FTQ_RESET_SEND_BD_COMPLETION | FTQ_RESET_DMA_WRITE |
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FTQ_RESET_DMA_HIGH_PRI_WRITE | FTQ_RESET_SEND_DATA_COMPLETION |
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FTQ_RESET_HOST_COALESCING | FTQ_RESET_MAC_TX |
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FTQ_RESET_RX_BD_COMPLETE | FTQ_RESET_RX_LIST_PLCMT |
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FTQ_RESET_RX_DATA_COMPLETION;
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tw32(FTQ_RESET, val);
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err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE);
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err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE);
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@ -1554,8 +1562,19 @@ static void tg3_chip_reset(struct tg3 *tp)
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// Alf: here patched
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/* do the reset */
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val = GRC_MISC_CFG_CORECLK_RESET;
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if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
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if (tr32(0x7e2c) == 0x60) {
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tw32(0x7e2c, 0x20);
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}
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if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
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tw32(GRC_MISC_CFG, (1 << 29));
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val |= (1 << 29);
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}
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}
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if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
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|| (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
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|| (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
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|| (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)) {
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val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
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}
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@ -1644,7 +1663,8 @@ static int tg3_restart_fw(struct tg3 *tp, uint32_t state)
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udelay(10);
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}
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if (i >= 100000 &&
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!(tp->tg3_flags2 & TG3_FLG2_SUN_5704)) {
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!(tp->tg3_flags2 & TG3_FLG2_SUN_5704) &&
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!(GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)) {
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printf ( "Firmware will not restart magic=%#lx\n",
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val );
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return -ENODEV;
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@ -1879,7 +1899,9 @@ static int tg3_setup_hw(struct tg3 *tp)
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(65 << GRC_MISC_CFG_PRESCALAR_SHIFT));
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/* Initialize MBUF/DESC pool. */
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if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) &&
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) {
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/* Do nothing. */
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} else if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) &&
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(tp->pci_chip_rev_id != CHIPREV_ID_5721)) {
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tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
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@ -1976,7 +1998,8 @@ static int tg3_setup_hw(struct tg3 *tp)
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TG3_WRITE_SETTINGS(table_all);
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tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
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virt_to_bus(tp->rx_std));
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) {
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tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
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RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
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} else {
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@ -1985,10 +2008,11 @@ static int tg3_setup_hw(struct tg3 *tp)
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}
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/* There is only one send ring on 5705, no need to explicitly
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/* There is only one send ring on 5705 and 5787, no need to explicitly
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* disable the others.
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*/
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if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
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if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
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GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787) {
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/* Clear out send RCB ring in SRAM. */
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for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
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tg3_write_mem(i + TG3_BDINFO_MAXLEN_FLAGS, BDINFO_FLAGS_DISABLED);
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@ -2004,10 +2028,11 @@ static int tg3_setup_hw(struct tg3 *tp)
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(TG3_TX_RING_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT),
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NIC_SRAM_TX_BUFFER_DESC);
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/* There is only one receive return ring on 5705, no need to explicitly
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* disable the others.
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/* There is only one receive return ring on 5705 and 5787, no need to
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* explicitly disable the others.
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*/
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if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
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if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
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GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787) {
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for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK; i += TG3_BDINFO_SIZE) {
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tg3_write_mem(i + TG3_BDINFO_MAXLEN_FLAGS,
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BDINFO_FLAGS_DISABLED);
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@ -2086,6 +2111,11 @@ static int tg3_setup_hw(struct tg3 *tp)
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!(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
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val |= WDMAC_MODE_RX_ACCEL;
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}
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/* Host coalescing bug fix */
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
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val |= (1 << 29);
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tw32_carefully(WDMAC_MODE, val);
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if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
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@ -2182,7 +2212,8 @@ static int tg3_setup_hw(struct tg3 *tp)
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virt_to_bus(tp->hw_stats));
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tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
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virt_to_bus(tp->hw_status));
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if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
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if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
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GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787) {
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TG3_WRITE_SETTINGS(table_not_5705);
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}
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}
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@ -2762,15 +2793,9 @@ static int tg3_get_invariants(struct tg3 *tp)
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/* determine if it is PCIE system */
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// Alf : I have no idea what this is about...
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// But it's definitely usefull
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
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val = tr32(TG3PCI_MSI_CAP_ID) ;
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if (((val >> 8) & 0xff) == T3_PCIE_CAPABILITY_ID_REG) {
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val = tr32(T3_PCIE_CAPABILITY_ID_REG) ;
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if ((val & 0xff) == T3_PCIE_CAPABILITY_ID) {
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tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS ;
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}
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}
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}
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val = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
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if (val)
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tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
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/* Force the chip into D0. */
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tg3_set_power_state_0(tp);
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@ -3010,6 +3035,7 @@ static const char * tg3_phy_string(struct tg3 *tp)
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case PHY_ID_BCM5705: return "5705";
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case PHY_ID_BCM5750: return "5750";
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case PHY_ID_BCM5751: return "5751";
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case PHY_ID_BCM5787: return "5787";
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case PHY_ID_BCM8002: return "8002/serdes";
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case PHY_ID_SERDES: return "serdes";
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default: return "unknown";
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@ -3370,6 +3396,7 @@ PCI_ROM(0x14e4, 0x1659, "tg3-5721", "Broadcom Tigon 3 5721"),
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PCI_ROM(0x14e4, 0x165d, "tg3-5705M", "Broadcom Tigon 3 5705M"),
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PCI_ROM(0x14e4, 0x165e, "tg3-5705M_2", "Broadcom Tigon 3 5705M_2"),
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PCI_ROM(0x14e4, 0x1677, "tg3-5751", "Broadcom Tigon 3 5751"),
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PCI_ROM(0x14e4, 0x167a, "tg3-5754", "Broadcom Tigon 3 5754"),
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PCI_ROM(0x14e4, 0x1696, "tg3-5782", "Broadcom Tigon 3 5782"),
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PCI_ROM(0x14e4, 0x169c, "tg3-5788", "Broadcom Tigon 3 5788"),
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PCI_ROM(0x14e4, 0x169d, "tg3-5789", "Broadcom Tigon 3 5789"),
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@ -294,6 +294,7 @@ typedef unsigned long dma_addr_t;
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#define ASIC_REV_5704 0x02
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#define ASIC_REV_5705 0x03
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#define ASIC_REV_5750 0x04
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#define ASIC_REV_5787 0x0b
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#define GET_CHIP_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 8)
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#define CHIPREV_5700_AX 0x70
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#define CHIPREV_5700_BX 0x71
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@ -1273,6 +1274,17 @@ typedef unsigned long dma_addr_t;
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/* Flow Through queues */
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#define FTQ_RESET 0x00005c00
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#define FTQ_RESET_DMA_READ_QUEUE (1 << 1)
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#define FTQ_RESET_DMA_HIGH_PRI_READ (1 << 2)
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#define FTQ_RESET_SEND_BD_COMPLETION (1 << 4)
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#define FTQ_RESET_DMA_WRITE (1 << 6)
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#define FTQ_RESET_DMA_HIGH_PRI_WRITE (1 << 7)
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#define FTQ_RESET_SEND_DATA_COMPLETION (1 << 9)
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#define FTQ_RESET_HOST_COALESCING (1 << 10)
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#define FTQ_RESET_MAC_TX (1 << 11)
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#define FTQ_RESET_RX_BD_COMPLETE (1 << 13)
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#define FTQ_RESET_RX_LIST_PLCMT (1 << 14)
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#define FTQ_RESET_RX_DATA_COMPLETION (1 << 16)
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/* 0x5c04 --> 0x5c10 unused */
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#define FTQ_DMA_NORM_READ_CTL 0x00005c10
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#define FTQ_DMA_NORM_READ_FULL_CNT 0x00005c14
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@ -2130,7 +2142,8 @@ struct tg3 {
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#define PHY_ID_BCM5703 0x60008160
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#define PHY_ID_BCM5704 0x60008190
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#define PHY_ID_BCM5705 0x600081a0
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#define PHY_ID_BCM5750 0x60008180
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#define PHY_ID_BCM5750 0x60008180
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#define PHY_ID_BCM5787 0xbc050ce0
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#define PHY_ID_BCM8002 0x60010140
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#define PHY_ID_BCM5751 0x00206180
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#define PHY_ID_SERDES 0xfeedbee0
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@ -2157,7 +2170,8 @@ struct tg3 {
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((X) == PHY_ID_BCM5400 || (X) == PHY_ID_BCM5401 || \
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(X) == PHY_ID_BCM5411 || (X) == PHY_ID_BCM5701 || \
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(X) == PHY_ID_BCM5703 || (X) == PHY_ID_BCM5704 || \
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(X) == PHY_ID_BCM5705 || (X) == PHY_ID_BCM5750 || (X) == PHY_ID_BCM5751 || \
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(X) == PHY_ID_BCM5705 || (X) == PHY_ID_BCM5750 || \
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(X) == PHY_ID_BCM5751 || (X) == PHY_ID_BCM5787 || \
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(X) == PHY_ID_BCM8002 || (X) == PHY_ID_SERDES)
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unsigned long regs;
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@ -156,6 +156,7 @@
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#define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
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#define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
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#define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
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#define PCI_CAP_ID_EXP 0x10 /* PCI Express */
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#define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
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#define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */
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#define PCI_CAP_SIZEOF 4
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