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[ioapi] Generalise i386 raw I/O API to x86
Signed-off-by: Michael Brown <mcb30@ipxe.org>
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@ -35,7 +35,7 @@ FILE_LICENCE ( GPL2_OR_LATER );
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*
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* This routine uses MMX instructions.
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*/
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static uint64_t x86_readq ( volatile uint64_t *io_addr ) {
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static __unused uint64_t i386_readq ( volatile uint64_t *io_addr ) {
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uint64_t data;
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__asm__ __volatile__ ( "pushl %%edx\n\t"
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"pushl %%eax\n\t"
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@ -56,7 +56,7 @@ static uint64_t x86_readq ( volatile uint64_t *io_addr ) {
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*
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* This routine uses MMX instructions.
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*/
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static void x86_writeq ( uint64_t data, volatile uint64_t *io_addr ) {
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static __unused void i386_writeq ( uint64_t data, volatile uint64_t *io_addr ) {
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__asm__ __volatile__ ( "pushl %%edx\n\t"
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"pushl %%eax\n\t"
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"movq (%%esp), %%mm0\n\t"
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@ -75,11 +75,9 @@ PROVIDE_IOAPI_INLINE ( x86, io_to_bus );
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PROVIDE_IOAPI_INLINE ( x86, readb );
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PROVIDE_IOAPI_INLINE ( x86, readw );
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PROVIDE_IOAPI_INLINE ( x86, readl );
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PROVIDE_IOAPI ( x86, readq, x86_readq );
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PROVIDE_IOAPI_INLINE ( x86, writeb );
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PROVIDE_IOAPI_INLINE ( x86, writew );
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PROVIDE_IOAPI_INLINE ( x86, writel );
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PROVIDE_IOAPI ( x86, writeq, x86_writeq );
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PROVIDE_IOAPI_INLINE ( x86, inb );
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PROVIDE_IOAPI_INLINE ( x86, inw );
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PROVIDE_IOAPI_INLINE ( x86, inl );
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@ -94,3 +92,10 @@ PROVIDE_IOAPI_INLINE ( x86, outsw );
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PROVIDE_IOAPI_INLINE ( x86, outsl );
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PROVIDE_IOAPI_INLINE ( x86, iodelay );
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PROVIDE_IOAPI_INLINE ( x86, mb );
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#ifdef __x86_64__
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PROVIDE_IOAPI_INLINE ( x86, readq );
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PROVIDE_IOAPI_INLINE ( x86, writeq );
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#else
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PROVIDE_IOAPI ( x86, readq, i386_readq );
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PROVIDE_IOAPI ( x86, writeq, i386_writeq );
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#endif
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@ -3,7 +3,7 @@
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/** @file
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*
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* i386-specific I/O API implementations
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* x86-specific I/O API implementations
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*
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*/
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@ -5,14 +5,14 @@
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*
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* iPXE I/O API for x86
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*
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* i386 uses direct pointer dereferences for accesses to memory-mapped
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* x86 uses direct pointer dereferences for accesses to memory-mapped
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* I/O space, and the inX/outX instructions for accesses to
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* port-mapped I/O space.
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*
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* 64-bit atomic accesses (readq() and writeq()) use MMX instructions,
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* and will crash original Pentium and earlier CPUs. Fortunately, no
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* hardware that requires atomic 64-bit accesses will physically fit
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* into a machine with such an old CPU anyway.
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* 64-bit atomic accesses (readq() and writeq()) use MMX instructions
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* under i386, and will crash original Pentium and earlier CPUs.
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* Fortunately, no hardware that requires atomic 64-bit accesses will
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* physically fit into a machine with such an old CPU anyway.
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*/
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FILE_LICENCE ( GPL2_OR_LATER );
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@ -59,7 +59,7 @@ IOAPI_INLINE ( x86, io_to_bus ) ( volatile const void *io_addr ) {
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}
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/*
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* MMIO reads and writes up to 32 bits
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* MMIO reads and writes up to native word size
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*
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*/
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@ -71,6 +71,9 @@ IOAPI_INLINE ( x86, _api_func ) ( volatile _type *io_addr ) { \
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X86_READX ( readb, uint8_t );
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X86_READX ( readw, uint16_t );
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X86_READX ( readl, uint32_t );
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#ifdef __x86_64__
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X86_READX ( readq, uint64_t );
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#endif
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#define X86_WRITEX( _api_func, _type ) \
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static inline __always_inline void \
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@ -81,6 +84,9 @@ IOAPI_INLINE ( x86, _api_func ) ( _type data, \
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X86_WRITEX ( writeb, uint8_t );
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X86_WRITEX ( writew, uint16_t );
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X86_WRITEX ( writel, uint32_t );
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#ifdef __x86_64__
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X86_WRITEX ( writeq, uint64_t );
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#endif
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/*
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* PIO reads and writes up to 32 bits
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@ -1,10 +0,0 @@
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#ifndef _BITS_IO_H
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#define _BITS_IO_H
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/** @file
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*
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* x86_64-specific I/O API implementations
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*
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*/
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#endif /* _BITS_IO_H */
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