mirror of
https://github.com/xcat2/xNBA.git
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[natsemi] Replace driver for National Semicondutor NICs
Signed-off-by: Michael Brown <mcb30@ipxe.org>
This commit is contained in:
Michael Brown
parent
bd16deaa87
commit
2c1e8d2cb1
File diff suppressed because it is too large
Load Diff
@ -1,232 +1,329 @@
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FILE_LICENCE ( GPL_ANY );
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#ifndef _NATSEMI_H
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#define _NATSEMI_H
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#define NATSEMI_HW_TIMEOUT 400
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/** @file
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*
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* National Semiconductor "MacPhyter" network card driver
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*
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*/
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#define TX_RING_SIZE 4
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#define NUM_RX_DESC 4
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#define RX_BUF_SIZE 1536
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#define OWN 0x80000000
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#define DSIZE 0x00000FFF
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#define CRC_SIZE 4
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FILE_LICENCE ( GPL2_OR_LATER );
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struct natsemi_tx {
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#include <stdint.h>
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#include <ipxe/spi.h>
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#include <ipxe/spi_bit.h>
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/** BAR size */
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#define NATSEMI_BAR_SIZE 0x100
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/** A 32-bit packet descriptor */
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struct natsemi_descriptor_32 {
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/** Link to next descriptor */
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uint32_t link;
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/** Command / status */
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uint32_t cmdsts;
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/** Buffer pointer */
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uint32_t bufptr;
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} __attribute__ (( packed ));
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/** A 64-bit packet descriptor */
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struct natsemi_descriptor_64 {
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/** Link to next descriptor */
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uint64_t link;
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/** Buffer pointer */
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uint64_t bufptr;
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/** Command / status */
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uint32_t cmdsts;
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/** Extended status */
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uint32_t extsts;
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} __attribute__ (( packed ));
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/** A packet descriptor
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*
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* The 32-bit and 64-bit variants are overlaid such that "cmdsts" can
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* be accessed as a common field, and the overall size is a power of
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* two (to allow the descriptor ring length to be used as an
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* alignment).
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*/
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union natsemi_descriptor {
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/** Common fields */
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struct {
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/** Reserved */
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uint8_t reserved_a[16];
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/** Command / status */
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uint32_t cmdsts;
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/** Reserved */
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uint8_t reserved_b[12];
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} __attribute__ (( packed )) common;
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/** 64-bit descriptor */
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struct natsemi_descriptor_64 d64;
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/** 32-bit descriptor */
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struct {
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/** Reserved */
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uint8_t reserved[12];
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/** Descriptor */
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struct natsemi_descriptor_32 d32;
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} __attribute__ (( packed )) d32pad;
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};
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struct natsemi_rx {
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uint32_t link;
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uint32_t cmdsts;
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uint32_t bufptr;
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/** Descriptor buffer size mask */
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#define NATSEMI_DESC_SIZE_MASK 0xfff
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/** Packet descriptor flags */
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enum natsemi_descriptor_flags {
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/** Descriptor is owned by NIC */
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NATSEMI_DESC_OWN = 0x80000000UL,
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/** Request descriptor interrupt */
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NATSEMI_DESC_INTR = 0x20000000UL,
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/** Packet OK */
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NATSEMI_DESC_OK = 0x08000000UL,
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};
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struct natsemi_private {
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unsigned short ioaddr;
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unsigned short tx_cur;
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unsigned short tx_dirty;
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unsigned short rx_cur;
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struct natsemi_tx tx[TX_RING_SIZE];
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struct natsemi_rx rx[NUM_RX_DESC];
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/** Command Register */
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#define NATSEMI_CR 0x0000
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#define NATSEMI_CR_RST 0x00000100UL /**< Reset */
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#define NATSEMI_CR_RXR 0x00000020UL /**< Receiver reset */
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#define NATSEMI_CR_TXR 0x00000010UL /**< Transmit reset */
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#define NATSEMI_CR_RXE 0x00000004UL /**< Receiver enable */
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#define NATSEMI_CR_TXE 0x00000001UL /**< Transmit enable */
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/* need to add iobuf as we cannot free iobuf->data in close without this
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* alternatively substracting sizeof(head) and sizeof(list_head) can also
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* give the same.
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*/
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struct io_buffer *iobuf[NUM_RX_DESC];
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/** Maximum time to wait for a reset, in milliseconds */
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#define NATSEMI_RESET_MAX_WAIT_MS 100
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/* netdev_tx_complete needs pointer to the iobuf of the data so as to free
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* it from the memory.
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*/
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struct io_buffer *tx_iobuf[TX_RING_SIZE];
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/** Configuration and Media Status Register */
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#define NATSEMI_CFG 0x0004
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#define NATSEMI_CFG_LNKSTS 0x80000000UL /**< Link status */
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#define NATSEMI_CFG_SPDSTS1 0x40000000UL /**< Speed status bit 1 */
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#define NATSEMI_CFG_MODE_1000 0x00400000UL /**< 1000 Mb/s mode control */
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#define NATSEMI_CFG_PCI64_DET 0x00002000UL /**< PCI 64-bit bus detected */
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#define NATSEMI_CFG_DATA64_EN 0x00001000UL /**< 64-bit data enable */
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#define NATSEMI_CFG_M64ADDR 0x00000800UL /**< 64-bit address enable */
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#define NATSEMI_CFG_EXTSTS_EN 0x00000100UL /**< Extended status enable */
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/** EEPROM Access Register */
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#define NATSEMI_MEAR 0x0008
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#define NATSEMI_MEAR_EESEL 0x00000008UL /**< EEPROM chip select */
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#define NATSEMI_MEAR_EECLK 0x00000004UL /**< EEPROM serial clock */
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#define NATSEMI_MEAR_EEDO 0x00000002UL /**< EEPROM data out */
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#define NATSEMI_MEAR_EEDI 0x00000001UL /**< EEPROM data in */
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/** Size of EEPROM (in bytes) */
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#define NATSEMI_EEPROM_SIZE 32
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/** Word offset of MAC address within sane EEPROM layout */
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#define NATSEMI_EEPROM_MAC_SANE 0x0a
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/** Word offset of MAC address within insane EEPROM layout */
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#define NATSEMI_EEPROM_MAC_INSANE 0x06
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/** PCI Test Control Register */
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#define NATSEMI_PTSCR 0x000c
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#define NATSEMI_PTSCR_EELOAD_EN 0x00000004UL /**< Enable EEPROM load */
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/** Maximum time to wait for a configuration reload, in milliseconds */
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#define NATSEMI_EELOAD_MAX_WAIT_MS 100
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/** Interrupt Status Register */
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#define NATSEMI_ISR 0x0010
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#define NATSEMI_IRQ_TXDESC 0x00000080UL /**< TX descriptor */
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#define NATSEMI_IRQ_RXDESC 0x00000002UL /**< RX descriptor */
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/** Interrupt Mask Register */
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#define NATSEMI_IMR 0x0014
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/** Interrupt Enable Register */
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#define NATSEMI_IER 0x0018
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#define NATSEMI_IER_IE 0x00000001UL /**< Interrupt enable */
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/** Transmit Descriptor Pointer */
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#define NATSEMI_TXDP 0x0020
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/** Transmit Descriptor Pointer High Dword (64-bit) */
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#define NATSEMI_TXDP_HI_64 0x0024
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/** Number of transmit descriptors */
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#define NATSEMI_NUM_TX_DESC 4
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/** Transmit configuration register (32-bit) */
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#define NATSEMI_TXCFG_32 0x24
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/** Transmit configuration register (64-bit) */
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#define NATSEMI_TXCFG_64 0x28
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#define NATSEMI_TXCFG_CSI 0x80000000UL /**< Carrier sense ignore */
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#define NATSEMI_TXCFG_HBI 0x40000000UL /**< Heartbeat ignore */
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#define NATSEMI_TXCFG_ATP 0x10000000UL /**< Automatic padding */
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#define NATSEMI_TXCFG_ECRETRY 0x00800000UL /**< Excess collision retry */
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#define NATSEMI_TXCFG_MXDMA(x) ( (x) << 20 ) /**< Max DMA burst size */
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#define NATSEMI_TXCFG_FLTH(x) ( (x) << 8 ) /**< Fill threshold */
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#define NATSEMI_TXCFG_DRTH(x) ( (x) << 0 ) /**< Drain threshold */
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/** Max DMA burst size (encoded value)
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*
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* This represents 256-byte bursts on 83815 controllers and 512-byte
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* bursts on 83820 controllers.
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*/
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#define NATSEMI_TXCFG_MXDMA_DEFAULT NATSEMI_TXCFG_MXDMA ( 0x7 )
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/** Fill threshold (in units of 32 bytes)
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*
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* Must be at least as large as the max DMA burst size, so use a value
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* of 512 bytes.
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*/
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#define NATSEMI_TXCFG_FLTH_DEFAULT NATSEMI_TXCFG_FLTH ( 512 / 32 )
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/** Drain threshold (in units of 32 bytes)
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*
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* Start transmission once we receive a conservative 1024 bytes, to
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* avoid FIFO underrun errors. (83815 does not allow us to specify a
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* value of 0 for "wait until whole packet is present".)
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*
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* Fill threshold plus drain threshold must be less than the transmit
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* FIFO size, which is 2kB on 83815 and 8kB on 83820.
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*/
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#define NATSEMI_TXCFG_DRTH_DEFAULT NATSEMI_TXCFG_DRTH ( 1024 / 32 )
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/** Receive Descriptor Pointer */
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#define NATSEMI_RXDP 0x0030
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/** Receive Descriptor Pointer High Dword (64-bit) */
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#define NATSEMI_RXDP_HI_64 0x0034
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/** Number of receive descriptors */
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#define NATSEMI_NUM_RX_DESC 4
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/** Receive buffer length */
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#define NATSEMI_RX_MAX_LEN ( ETH_FRAME_LEN + 4 /* VLAN */ + 4 /* CRC */ )
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/** Receive configuration register (32-bit) */
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#define NATSEMI_RXCFG_32 0x34
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/** Receive configuration register (64-bit) */
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#define NATSEMI_RXCFG_64 0x38
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#define NATSEMI_RXCFG_ARP 0x40000000UL /**< Accept runt packets */
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#define NATSEMI_RXCFG_ATX 0x10000000UL /**< Accept transmit packets */
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#define NATSEMI_RXCFG_ALP 0x08000000UL /**< Accept long packets */
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#define NATSEMI_RXCFG_MXDMA(x) ( (x) << 20 ) /**< Max DMA burst size */
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#define NATSEMI_RXCFG_DRTH(x) ( (x) << 1 ) /**< Drain threshold */
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/** Max DMA burst size (encoded value)
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*
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* This represents 256-byte bursts on 83815 controllers and 512-byte
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* bursts on 83820 controllers.
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*/
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#define NATSEMI_RXCFG_MXDMA_DEFAULT NATSEMI_RXCFG_MXDMA ( 0x7 )
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/** Drain threshold (in units of 8 bytes)
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*
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* Start draining after 64 bytes.
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*
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* Must be large enough to allow packet's accept/reject status to be
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* determined before draining begins.
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*/
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#define NATSEMI_RXCFG_DRTH_DEFAULT NATSEMI_RXCFG_DRTH ( 64 / 8 )
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/** Receive Filter/Match Control Register */
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#define NATSEMI_RFCR 0x0048
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#define NATSEMI_RFCR_RFEN 0x80000000UL /**< RX filter enable */
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#define NATSEMI_RFCR_AAB 0x40000000UL /**< Accept all broadcast */
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#define NATSEMI_RFCR_AAM 0x20000000UL /**< Accept all multicast */
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#define NATSEMI_RFCR_AAU 0x10000000UL /**< Accept all unicast */
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#define NATSEMI_RFCR_RFADDR( addr ) ( (addr) << 0 ) /**< Extended address */
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#define NATSEMI_RFCR_RFADDR_MASK NATSEMI_RFCR_RFADDR ( 0x3ff )
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/** Perfect match filter address base */
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#define NATSEMI_RFADDR_PMATCH_BASE 0x000
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/** Receive Filter/Match Data Register */
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#define NATSEMI_RFDR 0x004c
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#define NATSEMI_RFDR_BMASK 0x00030000UL /**< Byte mask */
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#define NATSEMI_RFDR_DATA( value ) ( (value) & 0xffff ) /**< Filter data */
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/** National Semiconductor network card flags */
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enum natsemi_nic_flags {
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/** EEPROM is little-endian */
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NATSEMI_EEPROM_LITTLE_ENDIAN = 0x0001,
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/** EEPROM layout is insane */
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NATSEMI_EEPROM_INSANE = 0x0002,
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/** Card supports 64-bit operation */
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NATSEMI_64BIT = 0x0004,
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/** Card supports 1000Mbps link */
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NATSEMI_1000 = 0x0008,
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};
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/** A National Semiconductor descriptor ring */
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struct natsemi_ring {
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/** Descriptors */
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union natsemi_descriptor *desc;
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/** Producer index */
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unsigned int prod;
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/** Consumer index */
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unsigned int cons;
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/** Number of descriptors */
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unsigned int count;
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/** Descriptor start address register */
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unsigned int reg;
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};
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/**
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* Initialise descriptor ring
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*
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* @v ring Descriptor ring
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* @v count Number of descriptors
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* @v reg Descriptor start address register
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*/
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static inline __attribute__ (( always_inline)) void
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natsemi_init_ring ( struct natsemi_ring *ring, unsigned int count,
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unsigned int reg ) {
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ring->count = count;
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ring->reg = reg;
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}
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/** A National Semiconductor network card */
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struct natsemi_nic {
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/** Flags */
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unsigned int flags;
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/** Registers */
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void *regs;
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/** SPI bit-bashing interface */
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struct spi_bit_basher spibit;
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/** EEPROM */
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struct spi_device eeprom;
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struct nvo_block nvo;
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/** Transmit descriptor ring */
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struct natsemi_ring tx;
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/** Receive descriptor ring */
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struct natsemi_ring rx;
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/** Receive I/O buffers */
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struct io_buffer *rx_iobuf[NATSEMI_NUM_RX_DESC];
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/** Link status (cache) */
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uint32_t cfg;
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};
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/*
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* Support for fibre connections on Am79C874:
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* This phy needs a special setup when connected to a fibre cable.
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* http://www.amd.com/files/connectivitysolutions/networking/archivednetworking/22235.pdf
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/**
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* Check if card can access physical address
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*
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* @v natsemi National Semiconductor device
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* @v address Physical address
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* @v address_ok Card can access physical address
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*/
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#define PHYID_AM79C874 0x0022561b
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static inline __attribute__ (( always_inline )) int
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natsemi_address_ok ( struct natsemi_nic *natsemi, physaddr_t address ) {
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enum {
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MII_MCTRL = 0x15, /* mode control register */
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MII_FX_SEL = 0x0001, /* 100BASE-FX (fiber) */
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MII_EN_SCRM = 0x0004, /* enable scrambler (tp) */
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};
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/* In a 32-bit build, all addresses can be accessed */
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if ( sizeof ( physaddr_t ) <= sizeof ( uint32_t ) )
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return 1;
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/* A 64-bit card can access all addresses */
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if ( natsemi->flags & NATSEMI_64BIT )
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return 1;
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/* A 32-bit card can access all address below 4GB */
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if ( ( address & 0xffffffffUL ) == 0 )
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return 1;
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/* values we might find in the silicon revision register */
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#define SRR_DP83815_C 0x0302
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#define SRR_DP83815_D 0x0403
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#define SRR_DP83816_A4 0x0504
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#define SRR_DP83816_A5 0x0505
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/* NATSEMI: Offsets to the device registers.
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* Unlike software-only systems, device drivers interact with complex hardware.
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* It's not useful to define symbolic names for every register bit in the
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* device.
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*/
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enum register_offsets {
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ChipCmd = 0x00,
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ChipConfig = 0x04,
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EECtrl = 0x08,
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PCIBusCfg = 0x0C,
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IntrStatus = 0x10,
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IntrMask = 0x14,
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IntrEnable = 0x18,
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TxRingPtr = 0x20,
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TxConfig = 0x24,
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RxRingPtr = 0x30,
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RxConfig = 0x34,
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ClkRun = 0x3C,
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WOLCmd = 0x40,
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PauseCmd = 0x44,
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RxFilterAddr = 0x48,
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RxFilterData = 0x4C,
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BootRomAddr = 0x50,
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BootRomData = 0x54,
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SiliconRev = 0x58,
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StatsCtrl = 0x5C,
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StatsData = 0x60,
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RxPktErrs = 0x60,
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RxMissed = 0x68,
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RxCRCErrs = 0x64,
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PCIPM = 0x44,
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PhyStatus = 0xC0,
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MIntrCtrl = 0xC4,
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MIntrStatus = 0xC8,
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/* These are from the spec, around page 78... on a separate table.
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*/
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PGSEL = 0xCC,
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PMDCSR = 0xE4,
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TSTDAT = 0xFC,
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DSPCFG = 0xF4,
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SDCFG = 0x8C,
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BasicControl = 0x80,
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BasicStatus = 0x84
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};
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/* the values for the 'magic' registers above (PGSEL=1) */
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#define PMDCSR_VAL 0x189c /* enable preferred adaptation circuitry */
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#define TSTDAT_VAL 0x0
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#define DSPCFG_VAL 0x5040
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#define SDCFG_VAL 0x008c /* set voltage thresholds for Signal Detect */
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#define DSPCFG_LOCK 0x20 /* coefficient lock bit in DSPCFG */
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#define DSPCFG_COEF 0x1000 /* see coefficient (in TSTDAT) bit in DSPCFG */
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#define TSTDAT_FIXED 0xe8 /* magic number for bad coefficients */
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/* Bit in ChipCmd.
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*/
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enum ChipCmdBits {
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ChipReset = 0x100,
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RxReset = 0x20,
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TxReset = 0x10,
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RxOff = 0x08,
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RxOn = 0x04,
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TxOff = 0x02,
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TxOn = 0x01
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};
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enum ChipConfig_bits {
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CfgPhyDis = 0x200,
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CfgPhyRst = 0x400,
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CfgExtPhy = 0x1000,
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CfgAnegEnable = 0x2000,
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CfgAneg100 = 0x4000,
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CfgAnegFull = 0x8000,
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CfgAnegDone = 0x8000000,
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CfgFullDuplex = 0x20000000,
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CfgSpeed100 = 0x40000000,
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CfgLink = 0x80000000,
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};
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/* Bits in the RxMode register.
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*/
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enum rx_mode_bits {
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AcceptErr = 0x20,
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||||
AcceptRunt = 0x10,
|
||||
AcceptBroadcast = 0xC0000000,
|
||||
AcceptMulticast = 0x00200000,
|
||||
AcceptAllMulticast = 0x20000000,
|
||||
AcceptAllPhys = 0x10000000,
|
||||
AcceptMyPhys = 0x08000000,
|
||||
RxFilterEnable = 0x80000000
|
||||
};
|
||||
|
||||
/* Bits in network_desc.status
|
||||
*/
|
||||
enum desc_status_bits {
|
||||
DescOwn = 0x80000000,
|
||||
DescMore = 0x40000000,
|
||||
DescIntr = 0x20000000,
|
||||
DescNoCRC = 0x10000000,
|
||||
DescPktOK = 0x08000000,
|
||||
RxTooLong = 0x00400000
|
||||
};
|
||||
|
||||
/*Bits in Interrupt Mask register
|
||||
*/
|
||||
enum Intr_mask_register_bits {
|
||||
RxOk = 0x001,
|
||||
RxErr = 0x004,
|
||||
TxOk = 0x040,
|
||||
TxErr = 0x100
|
||||
};
|
||||
|
||||
enum MIntrCtrl_bits {
|
||||
MICRIntEn = 0x2,
|
||||
};
|
||||
|
||||
/* CFG bits [13:16] [18:23] */
|
||||
#define CFG_RESET_SAVE 0xfde000
|
||||
/* WCSR bits [0:4] [9:10] */
|
||||
#define WCSR_RESET_SAVE 0x61f
|
||||
/* RFCR bits [20] [22] [27:31] */
|
||||
#define RFCR_RESET_SAVE 0xf8500000;
|
||||
|
||||
/* Delay between EEPROM clock transitions.
|
||||
No extra delay is needed with 33Mhz PCI, but future 66Mhz access may need
|
||||
a delay. */
|
||||
#define eeprom_delay(ee_addr) inl(ee_addr)
|
||||
|
||||
enum EEPROM_Ctrl_Bits {
|
||||
EE_ShiftClk = 0x04,
|
||||
EE_DataIn = 0x01,
|
||||
EE_ChipSelect = 0x08,
|
||||
EE_DataOut = 0x02
|
||||
};
|
||||
|
||||
#define EE_Write0 (EE_ChipSelect)
|
||||
#define EE_Write1 (EE_ChipSelect | EE_DataIn)
|
||||
|
||||
/* The EEPROM commands include the alway-set leading bit. */
|
||||
enum EEPROM_Cmds {
|
||||
EE_WriteCmd=(5 << 6), EE_ReadCmd=(6 << 6), EE_EraseCmd=(7 << 6),
|
||||
};
|
||||
|
||||
/* EEPROM access , values are devices specific
|
||||
*/
|
||||
#define EE_CS 0x08 /* EEPROM chip select */
|
||||
#define EE_SK 0x04 /* EEPROM shift clock */
|
||||
#define EE_DI 0x01 /* Data in */
|
||||
#define EE_DO 0x02 /* Data out */
|
||||
|
||||
/* Offsets within EEPROM (these are word offsets)
|
||||
*/
|
||||
#define EE_MAC 7
|
||||
#define EE_REG EECtrl
|
||||
|
||||
static const uint8_t natsemi_ee_bits[] = {
|
||||
[SPI_BIT_SCLK] = EE_SK,
|
||||
[SPI_BIT_MOSI] = EE_DI,
|
||||
[SPI_BIT_MISO] = EE_DO,
|
||||
[SPI_BIT_SS(0)] = EE_CS,
|
||||
};
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* _NATSEMI_H */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -61,6 +61,19 @@ init_at93cx6 ( struct spi_device *device, unsigned int organisation ) {
|
||||
device->nvs.write = threewire_write;
|
||||
}
|
||||
|
||||
/**
|
||||
* Initialise Atmel AT93C06 serial EEPROM
|
||||
*
|
||||
* @v device SPI device
|
||||
* @v organisation Word organisation (8 or 16)
|
||||
*/
|
||||
static inline __attribute__ (( always_inline )) void
|
||||
init_at93c06 ( struct spi_device *device, unsigned int organisation ) {
|
||||
device->nvs.size = ( 256 / organisation );
|
||||
device->address_len = ( ( organisation == 8 ) ? 7 : 6 );
|
||||
init_at93cx6 ( device, organisation );
|
||||
}
|
||||
|
||||
/**
|
||||
* Initialise Atmel AT93C46 serial EEPROM
|
||||
*
|
||||
|
||||
Loading…
Reference in New Issue
Block a user