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Reverted driver/net/mlx_ipoib to clean master state
This commit is contained in:
Michael Brown
parent
148055dd79
commit
0f60150c44
@ -1,455 +0,0 @@
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#ifndef _ARBEL_H
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#define _ARBEL_H
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/** @file
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*
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* Mellanox Arbel Infiniband HCA driver
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*
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*/
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#include <stdint.h>
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#include <gpxe/uaccess.h>
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/*
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* Hardware constants
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*
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*/
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/* PCI BARs */
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#define ARBEL_PCI_CONFIG_BAR PCI_BASE_ADDRESS_0
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#define ARBEL_PCI_CONFIG_BAR_SIZE 0x100000
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#define ARBEL_PCI_UAR_BAR PCI_BASE_ADDRESS_2
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#define ARBEL_PCI_UAR_IDX 1
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#define ARBEL_PCI_UAR_SIZE 0x1000
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/* UAR context table (UCE) resource types */
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#define ARBEL_UAR_RES_NONE 0x00
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#define ARBEL_UAR_RES_CQ_CI 0x01
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#define ARBEL_UAR_RES_CQ_ARM 0x02
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#define ARBEL_UAR_RES_SQ 0x03
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#define ARBEL_UAR_RES_RQ 0x04
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#define ARBEL_UAR_RES_GROUP_SEP 0x07
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/* Work queue entry and completion queue entry opcodes */
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#define ARBEL_OPCODE_SEND 0x0a
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#define ARBEL_OPCODE_RECV_ERROR 0xfe
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#define ARBEL_OPCODE_SEND_ERROR 0xff
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/* HCA command register opcodes */
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#define ARBEL_HCR_QUERY_DEV_LIM 0x0003
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#define ARBEL_HCR_QUERY_FW 0x0004
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#define ARBEL_HCR_INIT_HCA 0x0007
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#define ARBEL_HCR_CLOSE_HCA 0x0008
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#define ARBEL_HCR_INIT_IB 0x0009
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#define ARBEL_HCR_CLOSE_IB 0x000a
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#define ARBEL_HCR_SW2HW_MPT 0x000d
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#define ARBEL_HCR_MAP_EQ 0x0012
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#define ARBEL_HCR_SW2HW_EQ 0x0013
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#define ARBEL_HCR_HW2SW_EQ 0x0014
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#define ARBEL_HCR_SW2HW_CQ 0x0016
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#define ARBEL_HCR_HW2SW_CQ 0x0017
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#define ARBEL_HCR_RST2INIT_QPEE 0x0019
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#define ARBEL_HCR_INIT2RTR_QPEE 0x001a
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#define ARBEL_HCR_RTR2RTS_QPEE 0x001b
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#define ARBEL_HCR_2RST_QPEE 0x0021
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#define ARBEL_HCR_MAD_IFC 0x0024
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#define ARBEL_HCR_READ_MGM 0x0025
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#define ARBEL_HCR_WRITE_MGM 0x0026
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#define ARBEL_HCR_MGID_HASH 0x0027
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#define ARBEL_HCR_RUN_FW 0x0ff6
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#define ARBEL_HCR_DISABLE_LAM 0x0ff7
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#define ARBEL_HCR_ENABLE_LAM 0x0ff8
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#define ARBEL_HCR_UNMAP_ICM 0x0ff9
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#define ARBEL_HCR_MAP_ICM 0x0ffa
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#define ARBEL_HCR_UNMAP_ICM_AUX 0x0ffb
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#define ARBEL_HCR_MAP_ICM_AUX 0x0ffc
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#define ARBEL_HCR_SET_ICM_SIZE 0x0ffd
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#define ARBEL_HCR_UNMAP_FA 0x0ffe
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#define ARBEL_HCR_MAP_FA 0x0fff
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/* Service types */
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#define ARBEL_ST_UD 0x03
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/* MTUs */
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#define ARBEL_MTU_2048 0x04
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#define ARBEL_NO_EQ 64
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#define ARBEL_INVALID_LKEY 0x00000100UL
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/*
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* Datatypes that seem to be missing from the autogenerated documentation
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*
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*/
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struct arbelprm_mgm_hash_st {
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pseudo_bit_t reserved0[0x00020];
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/* -------------- */
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pseudo_bit_t hash[0x00010];
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pseudo_bit_t reserved1[0x00010];
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} __attribute__ (( packed ));
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struct arbelprm_scalar_parameter_st {
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pseudo_bit_t reserved0[0x00020];
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/* -------------- */
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pseudo_bit_t value[0x00020];
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} __attribute__ (( packed ));
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/*
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* Wrapper structures for hardware datatypes
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*
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*/
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struct MLX_DECLARE_STRUCT ( arbelprm_access_lam );
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struct MLX_DECLARE_STRUCT ( arbelprm_completion_queue_context );
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struct MLX_DECLARE_STRUCT ( arbelprm_completion_queue_entry );
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struct MLX_DECLARE_STRUCT ( arbelprm_completion_with_error );
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struct MLX_DECLARE_STRUCT ( arbelprm_cq_arm_db_record );
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struct MLX_DECLARE_STRUCT ( arbelprm_cq_ci_db_record );
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struct MLX_DECLARE_STRUCT ( arbelprm_eqc );
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struct MLX_DECLARE_STRUCT ( arbelprm_hca_command_register );
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struct MLX_DECLARE_STRUCT ( arbelprm_init_hca );
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struct MLX_DECLARE_STRUCT ( arbelprm_init_ib );
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struct MLX_DECLARE_STRUCT ( arbelprm_mad_ifc );
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struct MLX_DECLARE_STRUCT ( arbelprm_mgm_entry );
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struct MLX_DECLARE_STRUCT ( arbelprm_mgm_hash );
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struct MLX_DECLARE_STRUCT ( arbelprm_mpt );
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struct MLX_DECLARE_STRUCT ( arbelprm_qp_db_record );
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struct MLX_DECLARE_STRUCT ( arbelprm_qp_ee_state_transitions );
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struct MLX_DECLARE_STRUCT ( arbelprm_query_dev_lim );
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struct MLX_DECLARE_STRUCT ( arbelprm_query_fw );
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struct MLX_DECLARE_STRUCT ( arbelprm_queue_pair_ee_context_entry );
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struct MLX_DECLARE_STRUCT ( arbelprm_recv_wqe_segment_next );
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struct MLX_DECLARE_STRUCT ( arbelprm_scalar_parameter );
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struct MLX_DECLARE_STRUCT ( arbelprm_send_doorbell );
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struct MLX_DECLARE_STRUCT ( arbelprm_ud_address_vector );
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struct MLX_DECLARE_STRUCT ( arbelprm_virtual_physical_mapping );
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struct MLX_DECLARE_STRUCT ( arbelprm_wqe_segment_ctrl_send );
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struct MLX_DECLARE_STRUCT ( arbelprm_wqe_segment_data_ptr );
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struct MLX_DECLARE_STRUCT ( arbelprm_wqe_segment_next );
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struct MLX_DECLARE_STRUCT ( arbelprm_wqe_segment_ud );
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/*
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* Composite hardware datatypes
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*
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*/
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#define ARBEL_MAX_GATHER 1
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struct arbelprm_ud_send_wqe {
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struct arbelprm_wqe_segment_next next;
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struct arbelprm_wqe_segment_ctrl_send ctrl;
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struct arbelprm_wqe_segment_ud ud;
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struct arbelprm_wqe_segment_data_ptr data[ARBEL_MAX_GATHER];
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} __attribute__ (( packed ));
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#define ARBEL_MAX_SCATTER 1
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struct arbelprm_recv_wqe {
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/* The autogenerated header is inconsistent between send and
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* receive WQEs. The "ctrl" structure for receive WQEs is
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* defined to include the "next" structure. Since the "ctrl"
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* part of the "ctrl" structure contains only "reserved, must
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* be zero" bits, we ignore its definition and provide
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* something more usable.
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*/
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struct arbelprm_recv_wqe_segment_next next;
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uint32_t ctrl[2]; /* All "reserved, must be zero" */
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struct arbelprm_wqe_segment_data_ptr data[ARBEL_MAX_SCATTER];
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} __attribute__ (( packed ));
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union arbelprm_completion_entry {
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struct arbelprm_completion_queue_entry normal;
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struct arbelprm_completion_with_error error;
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} __attribute__ (( packed ));
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union arbelprm_doorbell_record {
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struct arbelprm_cq_arm_db_record cq_arm;
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struct arbelprm_cq_ci_db_record cq_ci;
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struct arbelprm_qp_db_record qp;
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} __attribute__ (( packed ));
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union arbelprm_doorbell_register {
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struct arbelprm_send_doorbell send;
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uint32_t dword[2];
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} __attribute__ (( packed ));
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union arbelprm_mad {
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struct arbelprm_mad_ifc ifc;
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union ib_mad mad;
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} __attribute__ (( packed ));
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/*
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* gPXE-specific definitions
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*
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*/
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/** Arbel device limits */
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struct arbel_dev_limits {
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/** Number of reserved QPs */
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unsigned int reserved_qps;
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/** QP context entry size */
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size_t qpc_entry_size;
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/** Extended QP context entry size */
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size_t eqpc_entry_size;
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/** Number of reserved SRQs */
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unsigned int reserved_srqs;
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/** SRQ context entry size */
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size_t srqc_entry_size;
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/** Number of reserved EEs */
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unsigned int reserved_ees;
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/** EE context entry size */
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size_t eec_entry_size;
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/** Extended EE context entry size */
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size_t eeec_entry_size;
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/** Number of reserved CQs */
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unsigned int reserved_cqs;
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/** CQ context entry size */
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size_t cqc_entry_size;
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/** Number of reserved MTTs */
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unsigned int reserved_mtts;
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/** MTT entry size */
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size_t mtt_entry_size;
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/** Number of reserved MRWs */
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unsigned int reserved_mrws;
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/** MPT entry size */
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size_t mpt_entry_size;
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/** Number of reserved RDBs */
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unsigned int reserved_rdbs;
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/** EQ context entry size */
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size_t eqc_entry_size;
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/** Number of reserved UARs */
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unsigned int reserved_uars;
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};
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/** Alignment of Arbel send work queue entries */
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#define ARBEL_SEND_WQE_ALIGN 128
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/** An Arbel send work queue entry */
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union arbel_send_wqe {
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struct arbelprm_ud_send_wqe ud;
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uint8_t force_align[ARBEL_SEND_WQE_ALIGN];
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} __attribute__ (( packed ));
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/** An Arbel send work queue */
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struct arbel_send_work_queue {
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/** Doorbell record number */
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unsigned int doorbell_idx;
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/** Work queue entries */
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union arbel_send_wqe *wqe;
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/** Size of work queue */
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size_t wqe_size;
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};
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/** Alignment of Arbel receive work queue entries */
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#define ARBEL_RECV_WQE_ALIGN 64
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/** An Arbel receive work queue entry */
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union arbel_recv_wqe {
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struct arbelprm_recv_wqe recv;
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uint8_t force_align[ARBEL_RECV_WQE_ALIGN];
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} __attribute__ (( packed ));
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/** An Arbel receive work queue */
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struct arbel_recv_work_queue {
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/** Doorbell record number */
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unsigned int doorbell_idx;
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/** Work queue entries */
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union arbel_recv_wqe *wqe;
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/** Size of work queue */
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size_t wqe_size;
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};
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/** Maximum number of allocatable queue pairs
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*
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* This is a policy decision, not a device limit.
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*/
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#define ARBEL_MAX_QPS 8
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/** Base queue pair number */
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#define ARBEL_QPN_BASE 0x550000
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/** An Arbel queue pair */
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struct arbel_queue_pair {
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/** Send work queue */
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struct arbel_send_work_queue send;
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/** Receive work queue */
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struct arbel_recv_work_queue recv;
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};
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/** Maximum number of allocatable completion queues
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*
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* This is a policy decision, not a device limit.
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*/
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#define ARBEL_MAX_CQS 8
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/** An Arbel completion queue */
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struct arbel_completion_queue {
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/** Consumer counter doorbell record number */
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unsigned int ci_doorbell_idx;
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/** Arm queue doorbell record number */
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unsigned int arm_doorbell_idx;
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/** Completion queue entries */
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union arbelprm_completion_entry *cqe;
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/** Size of completion queue */
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size_t cqe_size;
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};
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/** An Arbel resource bitmask */
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typedef uint32_t arbel_bitmask_t;
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/** Size of an Arbel resource bitmask */
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#define ARBEL_BITMASK_SIZE(max_entries) \
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( ( (max_entries) + ( 8 * sizeof ( arbel_bitmask_t ) ) - 1 ) / \
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( 8 * sizeof ( arbel_bitmask_t ) ) )
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/** An Arbel device */
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struct arbel {
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/** PCI configuration registers */
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void *config;
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/** PCI user Access Region */
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void *uar;
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/** Command input mailbox */
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void *mailbox_in;
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/** Command output mailbox */
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void *mailbox_out;
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/** Firmware area in external memory */
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userptr_t firmware_area;
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/** ICM size */
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size_t icm_len;
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/** ICM AUX size */
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size_t icm_aux_len;
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/** ICM area */
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userptr_t icm;
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/** Doorbell records */
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union arbelprm_doorbell_record *db_rec;
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/** Reserved LKey
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*
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* Used to get unrestricted memory access.
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*/
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unsigned long reserved_lkey;
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/** Completion queue in-use bitmask */
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arbel_bitmask_t cq_inuse[ ARBEL_BITMASK_SIZE ( ARBEL_MAX_CQS ) ];
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/** Queue pair in-use bitmask */
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arbel_bitmask_t qp_inuse[ ARBEL_BITMASK_SIZE ( ARBEL_MAX_QPS ) ];
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/** Device limits */
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struct arbel_dev_limits limits;
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};
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/** Global protection domain */
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#define ARBEL_GLOBAL_PD 0x123456
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/** Memory key prefix */
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#define ARBEL_MKEY_PREFIX 0x77000000UL
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/*
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* HCA commands
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*
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*/
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#define ARBEL_HCR_BASE 0x80680
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#define ARBEL_HCR_REG(x) ( ARBEL_HCR_BASE + 4 * (x) )
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#define ARBEL_HCR_MAX_WAIT_MS 2000
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#define ARBEL_MBOX_ALIGN 4096
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#define ARBEL_MBOX_SIZE 512
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/* HCA command is split into
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*
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* bits 11:0 Opcode
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* bit 12 Input uses mailbox
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* bit 13 Output uses mailbox
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* bits 22:14 Input parameter length (in dwords)
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* bits 31:23 Output parameter length (in dwords)
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*
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* Encoding the information in this way allows us to cut out several
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* parameters to the arbel_command() call.
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*/
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#define ARBEL_HCR_IN_MBOX 0x00001000UL
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#define ARBEL_HCR_OUT_MBOX 0x00002000UL
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#define ARBEL_HCR_OPCODE( _command ) ( (_command) & 0xfff )
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#define ARBEL_HCR_IN_LEN( _command ) ( ( (_command) >> 12 ) & 0x7fc )
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#define ARBEL_HCR_OUT_LEN( _command ) ( ( (_command) >> 21 ) & 0x7fc )
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/** Build HCR command from component parts */
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#define ARBEL_HCR_INOUT_CMD( _opcode, _in_mbox, _in_len, \
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_out_mbox, _out_len ) \
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( (_opcode) | \
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( (_in_mbox) ? ARBEL_HCR_IN_MBOX : 0 ) | \
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( ( (_in_len) / 4 ) << 14 ) | \
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( (_out_mbox) ? ARBEL_HCR_OUT_MBOX : 0 ) | \
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( ( (_out_len) / 4 ) << 23 ) )
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#define ARBEL_HCR_IN_CMD( _opcode, _in_mbox, _in_len ) \
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ARBEL_HCR_INOUT_CMD ( _opcode, _in_mbox, _in_len, 0, 0 )
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#define ARBEL_HCR_OUT_CMD( _opcode, _out_mbox, _out_len ) \
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ARBEL_HCR_INOUT_CMD ( _opcode, 0, 0, _out_mbox, _out_len )
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#define ARBEL_HCR_VOID_CMD( _opcode ) \
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ARBEL_HCR_INOUT_CMD ( _opcode, 0, 0, 0, 0 )
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/*
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* Doorbell record allocation
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*
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* The doorbell record map looks like:
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*
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* ARBEL_MAX_CQS * Arm completion queue doorbell
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* ARBEL_MAX_QPS * Send work request doorbell
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* Group separator
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* ...(empty space)...
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* ARBEL_MAX_QPS * Receive work request doorbell
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* ARBEL_MAX_CQS * Completion queue consumer counter update doorbell
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*/
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#define ARBEL_MAX_DOORBELL_RECORDS 512
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#define ARBEL_GROUP_SEPARATOR_DOORBELL ( ARBEL_MAX_CQS + ARBEL_MAX_QPS )
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/**
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* Get arm completion queue doorbell index
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*
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* @v cqn_offset Completion queue number offset
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* @ret doorbell_idx Doorbell index
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*/
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static inline unsigned int
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arbel_cq_arm_doorbell_idx ( unsigned int cqn_offset ) {
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return cqn_offset;
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}
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/**
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* Get send work request doorbell index
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*
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* @v qpn_offset Queue pair number offset
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* @ret doorbell_idx Doorbell index
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*/
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static inline unsigned int
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arbel_send_doorbell_idx ( unsigned int qpn_offset ) {
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return ( ARBEL_MAX_CQS + qpn_offset );
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}
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/**
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* Get receive work request doorbell index
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*
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* @v qpn_offset Queue pair number offset
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* @ret doorbell_idx Doorbell index
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*/
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static inline unsigned int
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arbel_recv_doorbell_idx ( unsigned int qpn_offset ) {
|
||||
return ( ARBEL_MAX_DOORBELL_RECORDS - ARBEL_MAX_CQS - qpn_offset - 1 );
|
||||
}
|
||||
|
||||
/**
|
||||
* Get completion queue consumer counter doorbell index
|
||||
*
|
||||
* @v cqn_offset Completion queue number offset
|
||||
* @ret doorbell_idx Doorbell index
|
||||
*/
|
||||
static inline unsigned int
|
||||
arbel_cq_ci_doorbell_idx ( unsigned int cqn_offset ) {
|
||||
return ( ARBEL_MAX_DOORBELL_RECORDS - cqn_offset - 1 );
|
||||
}
|
||||
|
||||
#endif /* _ARBEL_H */
|
||||
@ -80,14 +80,6 @@ struct addr_64_st {
|
||||
*/
|
||||
#define MT_EXTRACT_ARRAY32(A,O,S) MT_EXTRACT32(((__u32*)A)[O >> 5],(O & MASK32(5)),S)
|
||||
|
||||
/*
|
||||
* MT_EXTRACT_ARRAY32_BE macro is similar to EXTRACT but works on an array of (__u32),
|
||||
* thus offset may be larger than 32 (but not size).
|
||||
*
|
||||
* (added by mcb30)
|
||||
*/
|
||||
#define MT_EXTRACT_ARRAY32_BE(A,O,S) MT_EXTRACT32(be32_to_cpu(((__u32*)A)[O >> 5]),(O & MASK32(5)),S)
|
||||
|
||||
/*
|
||||
* MT_INSERT_ARRAY32 macro is similar to INSERT but works on an array of (__u32),
|
||||
* thus offset may be larger than 32 (but not size).
|
||||
@ -98,8 +90,6 @@ struct addr_64_st {
|
||||
|
||||
#define EX_FLD(a, st, fld) MT_EXTRACT_ARRAY32(a, MT_BIT_OFFSET(st, fld), MT_BIT_SIZE(st, fld))
|
||||
|
||||
#define EX_FLD_BE(a, st, fld) MT_EXTRACT_ARRAY32_BE(a, MT_BIT_OFFSET(st, fld), MT_BIT_SIZE(st, fld))
|
||||
|
||||
/* return the address of the dword holding the field
|
||||
|
||||
buf = pointer to buffer where to place the value
|
||||
@ -133,185 +123,4 @@ struct addr_64_st {
|
||||
field; \
|
||||
})
|
||||
|
||||
|
||||
|
||||
/* Remaining code Copyright Fen Systems Ltd. 2007 */
|
||||
|
||||
/**
|
||||
* Wrapper structure for pseudo_bit_t structures
|
||||
*
|
||||
* This structure provides a wrapper around the autogenerated
|
||||
* pseudo_bit_t structures. It has the correct size, and also
|
||||
* encapsulates type information about the underlying pseudo_bit_t
|
||||
* structure, which allows the MLX_FILL etc. macros to work without
|
||||
* requiring explicit type information.
|
||||
*/
|
||||
#define MLX_DECLARE_STRUCT( _structure ) \
|
||||
_structure { \
|
||||
union { \
|
||||
uint8_t bytes[ sizeof ( struct _structure ## _st ) / 8 ]; \
|
||||
uint32_t dwords[ sizeof ( struct _structure ## _st ) / 32 ]; \
|
||||
struct _structure ## _st *dummy[0]; \
|
||||
} u; \
|
||||
}
|
||||
|
||||
/** Get pseudo_bit_t structure type from wrapper structure pointer */
|
||||
#define MLX_PSEUDO_STRUCT( _ptr ) \
|
||||
typeof ( *((_ptr)->u.dummy[0]) )
|
||||
|
||||
/** Bit offset of a field within a pseudo_bit_t structure */
|
||||
#define MLX_BIT_OFFSET( _structure_st, _field ) \
|
||||
offsetof ( _structure_st, _field )
|
||||
|
||||
/** Dword offset of a field within a pseudo_bit_t structure */
|
||||
#define MLX_DWORD_OFFSET( _structure_st, _field ) \
|
||||
( MLX_BIT_OFFSET ( _structure_st, _field ) / 32 )
|
||||
|
||||
/** Dword bit offset of a field within a pseudo_bit_t structure
|
||||
*
|
||||
* Yes, using mod-32 would work, but would lose the check for the
|
||||
* error of specifying a mismatched field name and dword index.
|
||||
*/
|
||||
#define MLX_DWORD_BIT_OFFSET( _structure_st, _index, _field ) \
|
||||
( MLX_BIT_OFFSET ( _structure_st, _field ) - ( 32 * (_index) ) )
|
||||
|
||||
/** Bit width of a field within a pseudo_bit_t structure */
|
||||
#define MLX_BIT_WIDTH( _structure_st, _field ) \
|
||||
sizeof ( ( ( _structure_st * ) NULL )->_field )
|
||||
|
||||
/** Bit mask for a field within a pseudo_bit_t structure */
|
||||
#define MLX_BIT_MASK( _structure_st, _field ) \
|
||||
( ( ~( ( uint32_t ) 0 ) ) >> \
|
||||
( 32 - MLX_BIT_WIDTH ( _structure_st, _field ) ) )
|
||||
|
||||
/*
|
||||
* Assemble native-endian dword from named fields and values
|
||||
*
|
||||
*/
|
||||
|
||||
#define MLX_ASSEMBLE_1( _structure_st, _index, _field, _value ) \
|
||||
( (_value) << MLX_DWORD_BIT_OFFSET ( _structure_st, _index, _field ) )
|
||||
|
||||
#define MLX_ASSEMBLE_2( _structure_st, _index, _field, _value, ... ) \
|
||||
( MLX_ASSEMBLE_1 ( _structure_st, _index, _field, _value ) | \
|
||||
MLX_ASSEMBLE_1 ( _structure_st, _index, __VA_ARGS__ ) )
|
||||
|
||||
#define MLX_ASSEMBLE_3( _structure_st, _index, _field, _value, ... ) \
|
||||
( MLX_ASSEMBLE_1 ( _structure_st, _index, _field, _value ) | \
|
||||
MLX_ASSEMBLE_2 ( _structure_st, _index, __VA_ARGS__ ) )
|
||||
|
||||
#define MLX_ASSEMBLE_4( _structure_st, _index, _field, _value, ... ) \
|
||||
( MLX_ASSEMBLE_1 ( _structure_st, _index, _field, _value ) | \
|
||||
MLX_ASSEMBLE_3 ( _structure_st, _index, __VA_ARGS__ ) )
|
||||
|
||||
#define MLX_ASSEMBLE_5( _structure_st, _index, _field, _value, ... ) \
|
||||
( MLX_ASSEMBLE_1 ( _structure_st, _index, _field, _value ) | \
|
||||
MLX_ASSEMBLE_4 ( _structure_st, _index, __VA_ARGS__ ) )
|
||||
|
||||
#define MLX_ASSEMBLE_6( _structure_st, _index, _field, _value, ... ) \
|
||||
( MLX_ASSEMBLE_1 ( _structure_st, _index, _field, _value ) | \
|
||||
MLX_ASSEMBLE_5 ( _structure_st, _index, __VA_ARGS__ ) )
|
||||
|
||||
/*
|
||||
* Build native-endian (positive) dword bitmasks from named fields
|
||||
*
|
||||
*/
|
||||
|
||||
#define MLX_MASK_1( _structure_st, _index, _field ) \
|
||||
( MLX_BIT_MASK ( _structure_st, _field ) << \
|
||||
MLX_DWORD_BIT_OFFSET ( _structure_st, _index, _field ) )
|
||||
|
||||
#define MLX_MASK_2( _structure_st, _index, _field, ... ) \
|
||||
( MLX_MASK_1 ( _structure_st, _index, _field ) | \
|
||||
MLX_MASK_1 ( _structure_st, _index, __VA_ARGS__ ) )
|
||||
|
||||
#define MLX_MASK_3( _structure_st, _index, _field, ... ) \
|
||||
( MLX_MASK_1 ( _structure_st, _index, _field ) | \
|
||||
MLX_MASK_2 ( _structure_st, _index, __VA_ARGS__ ) )
|
||||
|
||||
#define MLX_MASK_4( _structure_st, _index, _field, ... ) \
|
||||
( MLX_MASK_1 ( _structure_st, _index, _field ) | \
|
||||
MLX_MASK_3 ( _structure_st, _index, __VA_ARGS__ ) )
|
||||
|
||||
#define MLX_MASK_5( _structure_st, _index, _field, ... ) \
|
||||
( MLX_MASK_1 ( _structure_st, _index, _field ) | \
|
||||
MLX_MASK_4 ( _structure_st, _index, __VA_ARGS__ ) )
|
||||
|
||||
#define MLX_MASK_6( _structure_st, _index, _field, ... ) \
|
||||
( MLX_MASK_1 ( _structure_st, _index, _field ) | \
|
||||
MLX_MASK_5 ( _structure_st, _index, __VA_ARGS__ ) )
|
||||
|
||||
/*
|
||||
* Populate big-endian dwords from named fields and values
|
||||
*
|
||||
*/
|
||||
|
||||
#define MLX_FILL( _ptr, _index, _assembled ) \
|
||||
do { \
|
||||
uint32_t *__ptr = &(_ptr)->u.dwords[(_index)]; \
|
||||
uint32_t __assembled = (_assembled); \
|
||||
*__ptr = cpu_to_be32 ( __assembled ); \
|
||||
} while ( 0 )
|
||||
|
||||
#define MLX_FILL_1( _ptr, _index, ... ) \
|
||||
MLX_FILL ( _ptr, _index, MLX_ASSEMBLE_1 ( MLX_PSEUDO_STRUCT ( _ptr ),\
|
||||
_index, __VA_ARGS__ ) )
|
||||
|
||||
#define MLX_FILL_2( _ptr, _index, ... ) \
|
||||
MLX_FILL ( _ptr, _index, MLX_ASSEMBLE_2 ( MLX_PSEUDO_STRUCT ( _ptr ),\
|
||||
_index, __VA_ARGS__ ) )
|
||||
|
||||
#define MLX_FILL_3( _ptr, _index, ... ) \
|
||||
MLX_FILL ( _ptr, _index, MLX_ASSEMBLE_3 ( MLX_PSEUDO_STRUCT ( _ptr ),\
|
||||
_index, __VA_ARGS__ ) )
|
||||
|
||||
#define MLX_FILL_4( _ptr, _index, ... ) \
|
||||
MLX_FILL ( _ptr, _index, MLX_ASSEMBLE_4 ( MLX_PSEUDO_STRUCT ( _ptr ),\
|
||||
_index, __VA_ARGS__ ) )
|
||||
|
||||
#define MLX_FILL_5( _ptr, _index, ... ) \
|
||||
MLX_FILL ( _ptr, _index, MLX_ASSEMBLE_5 ( MLX_PSEUDO_STRUCT ( _ptr ),\
|
||||
_index, __VA_ARGS__ ) )
|
||||
|
||||
#define MLX_FILL_6( _ptr, _index, ... ) \
|
||||
MLX_FILL ( _ptr, _index, MLX_ASSEMBLE_6 ( MLX_PSEUDO_STRUCT ( _ptr ),\
|
||||
_index, __VA_ARGS__ ) )
|
||||
|
||||
/*
|
||||
* Modify big-endian dword using named field and value
|
||||
*
|
||||
*/
|
||||
|
||||
#define MLX_SET( _ptr, _field, _value ) \
|
||||
do { \
|
||||
unsigned int __index = \
|
||||
MLX_DWORD_OFFSET ( MLX_PSEUDO_STRUCT ( _ptr ), _field ); \
|
||||
uint32_t *__ptr = &(_ptr)->u.dwords[__index]; \
|
||||
uint32_t __value = be32_to_cpu ( *__ptr ); \
|
||||
__value &= ~( MLX_MASK_1 ( MLX_PSEUDO_STRUCT ( _ptr ), \
|
||||
__index, _field ) ); \
|
||||
__value |= MLX_ASSEMBLE_1 ( MLX_PSEUDO_STRUCT ( _ptr ), \
|
||||
__index, _field, _value ); \
|
||||
*__ptr = cpu_to_be32 ( __value ); \
|
||||
} while ( 0 )
|
||||
|
||||
/*
|
||||
* Extract value of named field
|
||||
*
|
||||
*/
|
||||
|
||||
#define MLX_GET( _ptr, _field ) \
|
||||
( { \
|
||||
unsigned int __index = \
|
||||
MLX_DWORD_OFFSET ( MLX_PSEUDO_STRUCT ( _ptr ), _field ); \
|
||||
uint32_t *__ptr = &(_ptr)->u.dwords[__index]; \
|
||||
uint32_t __value = be32_to_cpu ( *__ptr ); \
|
||||
__value >>= \
|
||||
MLX_DWORD_BIT_OFFSET ( MLX_PSEUDO_STRUCT ( _ptr ), \
|
||||
__index, _field ); \
|
||||
__value &= \
|
||||
MLX_BIT_MASK ( MLX_PSEUDO_STRUCT ( _ptr ), _field ); \
|
||||
__value; \
|
||||
} )
|
||||
|
||||
#endif /* __bit_ops_h__ */
|
||||
|
||||
@ -112,8 +112,6 @@ static XHH_cmd_status_t cmd_invoke(command_fields_t * cmd_prms)
|
||||
__u32 hcr[7], data;
|
||||
__u8 status;
|
||||
|
||||
DBG ( "Executing command:\n" );
|
||||
|
||||
/* check if go bit is free */
|
||||
ret = cmdif_is_free(&is_free);
|
||||
if (ret) {
|
||||
@ -131,15 +129,6 @@ static XHH_cmd_status_t cmd_invoke(command_fields_t * cmd_prms)
|
||||
edit_hcr(cmd_prms, hcr);
|
||||
__asm__ __volatile__("":::"memory");
|
||||
|
||||
DBG_HD ( &hcr[0], sizeof ( hcr ) );
|
||||
if ( cmd_prms->in_trans == TRANS_MAILBOX ) {
|
||||
size_t size = ( 4 * cmd_prms->in_param_size );
|
||||
if ( size > 512 )
|
||||
size = 512;
|
||||
DBG2 ( "Input mailbox:\n" );
|
||||
DBG2_HD ( &cmd_prms->in_param[0], size );
|
||||
}
|
||||
|
||||
for (i = 0; i < 7; ++i) {
|
||||
ret = gw_write_cr(HCR_BASE + i * 4, hcr[i]);
|
||||
if (ret) {
|
||||
@ -170,14 +159,6 @@ static XHH_cmd_status_t cmd_invoke(command_fields_t * cmd_prms)
|
||||
return status;
|
||||
}
|
||||
|
||||
if ( cmd_prms->out_trans == TRANS_MAILBOX ) {
|
||||
size_t size = ( 4 * cmd_prms->out_param_size );
|
||||
if ( size > 512 )
|
||||
size = 512;
|
||||
DBG2 ( "Output mailbox:\n" );
|
||||
DBG2_HD ( &cmd_prms->out_param[0], size );
|
||||
}
|
||||
|
||||
if (cmd_prms->out_trans == TRANS_MAILBOX)
|
||||
be_to_cpu_buf(cmd_prms->out_param, cmd_prms->out_param_size);
|
||||
else if (cmd_prms->out_trans == TRANS_IMMEDIATE) {
|
||||
@ -187,8 +168,6 @@ static XHH_cmd_status_t cmd_invoke(command_fields_t * cmd_prms)
|
||||
return -1;
|
||||
}
|
||||
|
||||
DBG ( "Command executed successfully\n" );
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -563,10 +542,7 @@ static int cmd_mgid_hash(__u8 * gid, __u16 * mgid_hash_p)
|
||||
{
|
||||
int rc;
|
||||
command_fields_t cmd_desc;
|
||||
union {
|
||||
__u32 u32;
|
||||
__u16 u16[2];
|
||||
} result;
|
||||
__u16 result[2];
|
||||
|
||||
memset(&cmd_desc, 0, sizeof cmd_desc);
|
||||
|
||||
@ -578,9 +554,9 @@ static int cmd_mgid_hash(__u8 * gid, __u16 * mgid_hash_p)
|
||||
|
||||
rc = cmd_invoke(&cmd_desc);
|
||||
if (!rc) {
|
||||
rc = gw_read_cr(HCR_BASE + 16, &result.u32);
|
||||
rc = gw_read_cr(HCR_BASE + 16, (__u32 *) result);
|
||||
if (!rc) {
|
||||
*mgid_hash_p = result.u16[0];
|
||||
*mgid_hash_p = result[0];
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -22,6 +22,14 @@
|
||||
#include "cmdif_priv.h"
|
||||
#include "mt25218.h"
|
||||
|
||||
/*
|
||||
* cmd_sys_dis
|
||||
*/
|
||||
static int cmd_sys_dis(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* cmd_write_mgm
|
||||
*/
|
||||
@ -317,24 +325,6 @@ static int cmd_map_icm_aux(struct map_icm_st *map_icm_aux_p)
|
||||
return rc;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* cmd_unmap_icm_aux
|
||||
*/
|
||||
static int cmd_unmap_icm_aux(void)
|
||||
{
|
||||
int rc;
|
||||
command_fields_t cmd_desc;
|
||||
|
||||
memset(&cmd_desc, 0, sizeof cmd_desc);
|
||||
|
||||
cmd_desc.opcode = MEMFREE_CMD_UNMAP_ICM_AUX;
|
||||
|
||||
rc = cmd_invoke(&cmd_desc);
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
/*
|
||||
* cmd_map_icm
|
||||
*/
|
||||
@ -381,31 +371,6 @@ static int cmd_map_icm(struct map_icm_st *map_icm_p)
|
||||
return rc;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* cmd_unmap_icm
|
||||
*/
|
||||
static int cmd_unmap_icm(struct map_icm_st *map_icm_p)
|
||||
{
|
||||
int rc;
|
||||
command_fields_t cmd_desc;
|
||||
__u32 iprm[2];
|
||||
|
||||
memset(&cmd_desc, 0, sizeof cmd_desc);
|
||||
|
||||
cmd_desc.opcode = MEMFREE_CMD_UNMAP_ICM;
|
||||
iprm[0] = map_icm_p->vpm_arr[0].va_h;
|
||||
iprm[1] = map_icm_p->vpm_arr[0].va_l;
|
||||
cmd_desc.in_param = iprm;
|
||||
cmd_desc.in_trans = TRANS_IMMEDIATE;
|
||||
cmd_desc.input_modifier = 1 << map_icm_p->vpm_arr[0].log2_size;
|
||||
|
||||
rc = cmd_invoke(&cmd_desc);
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
/*
|
||||
* cmd_query_dev_lim
|
||||
*/
|
||||
|
||||
@ -92,11 +92,13 @@ files with .mlx extension also available from Mellanox's web site.
|
||||
|
||||
6. Preparing the DHCP Server
|
||||
-----------------------------
|
||||
The DHCP server may need to be modified in order to work on IPOIB. Some
|
||||
distributuions alreay support this (Some SUSE distributuions) while others
|
||||
do not. If the pre-installed server does not support IPOIB, the user can download
|
||||
the sources from ISC http://www.isc.org/ and apply the appropriate patch in
|
||||
the patches directory.
|
||||
DHCP messages over IP Over IB are transmitted as broadcasts. In order to
|
||||
distinguish between messages belonging to a certain DHCP session, the messages
|
||||
must carry the client identifier option (see ietf documentation referred to
|
||||
above). As of November 2005, ISC DHCP servers do not support this feature.
|
||||
They are expected to support this at the end of 2005. In order to work this
|
||||
out, the appropriate patch must be applied (see patches directory). It has
|
||||
been tested on version isc-dhcpd-V3.0.4b2.
|
||||
|
||||
The DHCP server must run on a machine which supports IP Over IB. The Mellanox
|
||||
IBGD package (gen1 or gen2) can be used to provide this.
|
||||
@ -169,14 +171,6 @@ PXE_IB_PORT.
|
||||
|
||||
14. Installing a package from Mellanox
|
||||
--------------------------------------
|
||||
The package comes as a compressed file with extension .bz2 or .gz. Follow
|
||||
these steps:
|
||||
1. Create a directory
|
||||
2. cd to this directory
|
||||
3. tar jxf <package file name> for .bz2 files or
|
||||
tar zxf <package file name> for .gz files
|
||||
|
||||
The binaries can be found under src/bin
|
||||
When using a package obtained from Mellanox Technologies' web site, the
|
||||
directory src/bin will contain the driver binary files. The files have a .bin
|
||||
extension and are equivalent to the same files with .zrom extension.
|
||||
|
||||
@ -62,9 +62,6 @@ static int wait_logic_link_up(__u8 port)
|
||||
return 0;
|
||||
}
|
||||
|
||||
unsigned long ipoib_qkey;
|
||||
unsigned long hack_ipoib_qkey;
|
||||
|
||||
static int ib_driver_init(struct pci_device *pci, udqp_t * ipoib_qph_p)
|
||||
{
|
||||
int rc;
|
||||
@ -150,9 +147,6 @@ static int ib_driver_init(struct pci_device *pci, udqp_t * ipoib_qph_p)
|
||||
qkey, mlid);
|
||||
}
|
||||
|
||||
hack_ipoib_qkey = ipoib_qkey = qkey;
|
||||
|
||||
#if 0
|
||||
rc = create_ipoib_qp(&ib_data.ipoib_qp,
|
||||
&ib_data.ipoib_snd_cq,
|
||||
&ib_data.ipoib_rcv_cq, qkey);
|
||||
@ -172,7 +166,6 @@ static int ib_driver_init(struct pci_device *pci, udqp_t * ipoib_qph_p)
|
||||
} else {
|
||||
tprintf("add_qp_to_mcast_group() success");
|
||||
}
|
||||
#endif
|
||||
|
||||
/* create a broadcast group ud AV */
|
||||
av = alloc_ud_av();
|
||||
@ -185,19 +178,6 @@ static int ib_driver_init(struct pci_device *pci, udqp_t * ipoib_qph_p)
|
||||
tprintf("modify_av_params() success");
|
||||
ib_data.bcast_av = av;
|
||||
|
||||
#if ! CREATE_OWN
|
||||
rc = create_ipoib_qp(&ib_data.ipoib_qp,
|
||||
&ib_data.ipoib_snd_cq,
|
||||
&ib_data.ipoib_rcv_cq, qkey);
|
||||
if (rc) {
|
||||
eprintf("");
|
||||
return rc;
|
||||
}
|
||||
|
||||
tprintf("create_ipoib_qp() success");
|
||||
*ipoib_qph_p = ib_data.ipoib_qp;
|
||||
#endif
|
||||
|
||||
do {
|
||||
rc = poll_eq(&ib_eqe, &num_eqe);
|
||||
if (rc) {
|
||||
@ -268,10 +248,12 @@ static int ib_driver_close(int fw_fatal)
|
||||
ret = 1;
|
||||
}
|
||||
|
||||
rc = unset_hca();
|
||||
if (rc) {
|
||||
eprintf("");
|
||||
ret = 1;
|
||||
if (!fw_fatal) {
|
||||
rc = cmd_sys_dis();
|
||||
if (rc) {
|
||||
eprintf("");
|
||||
ret = 1;
|
||||
}
|
||||
}
|
||||
|
||||
return ret;
|
||||
@ -286,7 +268,7 @@ static int poll_cqe_tout(cq_t cqh, __u16 tout, void **wqe, int *good_p)
|
||||
|
||||
end = currticks() + tout;
|
||||
do {
|
||||
rc = ib_poll_cqx(cqh, &ib_cqe, &num_cqes);
|
||||
rc = ib_poll_cq(cqh, &ib_cqe, &num_cqes);
|
||||
if (rc)
|
||||
return rc;
|
||||
|
||||
|
||||
@ -49,17 +49,17 @@
|
||||
#define QPN_BASE 0x550000
|
||||
|
||||
enum {
|
||||
MADS_QPN_SN,
|
||||
IPOIB_QPN_SN,
|
||||
MADS_QPN_SN = 4,
|
||||
MAX_APP_QPS = 8
|
||||
MAX_APP_QPS
|
||||
};
|
||||
|
||||
enum {
|
||||
MADS_SND_CQN_SN,
|
||||
MADS_RCV_CQN_SN,
|
||||
IPOIB_SND_CQN_SN,
|
||||
IPOIB_RCV_CQN_SN,
|
||||
MADS_SND_CQN_SN = 4,
|
||||
MADS_RCV_CQN_SN,
|
||||
MAX_APP_CQS = 8
|
||||
MAX_APP_CQS
|
||||
};
|
||||
|
||||
enum {
|
||||
@ -153,7 +153,7 @@ static int gw_read_cr(__u32 addr, __u32 * result);
|
||||
static int gw_write_cr(__u32 addr, __u32 data);
|
||||
static ud_av_t alloc_ud_av(void);
|
||||
static void free_ud_av(ud_av_t av);
|
||||
static int ib_poll_cqx(cq_t cq, struct ib_cqe_st *ib_cqe_p, __u8 * num_cqes);
|
||||
static int ib_poll_cq(cq_t cq, struct ib_cqe_st *ib_cqe_p, __u8 * num_cqes);
|
||||
static int add_qp_to_mcast_group(union ib_gid_u mcast_gid, __u8 add);
|
||||
static int clear_interrupt(void);
|
||||
static int poll_cqe_tout(cq_t cqh, __u16 tout, void **wqe, int *good_p);
|
||||
|
||||
@ -158,7 +158,7 @@ static int join_mc_group(__u32 * qkey_p, __u16 * mlid_p, __u8 join)
|
||||
eprintf("");
|
||||
return -1;
|
||||
}
|
||||
tprintf("allocated snd_wqe=%p", snd_wqe);
|
||||
tprintf("allocated snd_wqe=0x%lx", snd_wqe);
|
||||
|
||||
mad = get_send_wqe_buf(snd_wqe, 0);
|
||||
memset(mad, 0, 256);
|
||||
@ -264,7 +264,7 @@ static int join_mc_group(__u32 * qkey_p, __u16 * mlid_p, __u8 join)
|
||||
return is_good ? 0 : -1;
|
||||
}
|
||||
|
||||
int get_path_record(union ib_gid_u *dgid, __u16 * dlid_p, u8 * sl_p,
|
||||
static int get_path_record(union ib_gid_u *dgid, __u16 * dlid_p, u8 * sl_p,
|
||||
u8 * rate_p)
|
||||
{
|
||||
struct path_record_mad_st *mad, *rcv_mad;
|
||||
@ -321,9 +321,6 @@ int get_path_record(union ib_gid_u *dgid, __u16 * dlid_p, u8 * sl_p,
|
||||
cpu_to_be_buf(mad, sizeof *mad);
|
||||
memcpy(mad->path_record.sgid.raw, ib_data.port_gid.raw, 16);
|
||||
|
||||
DBG ( "data:\n" );
|
||||
DBG_HD ( mad, sizeof ( *mad ) );
|
||||
|
||||
rc = post_send_req(qp, snd_wqe, 1);
|
||||
if (rc) {
|
||||
eprintf("");
|
||||
|
||||
@ -104,7 +104,7 @@ union mad_u {
|
||||
struct ib_mad_st mad;
|
||||
} __attribute__ ((packed));
|
||||
|
||||
int get_path_record(union ib_gid_u *dgid, __u16 * dlid_p, __u8 * sl_p,
|
||||
static int get_path_record(union ib_gid_u *dgid, __u16 * dlid_p, __u8 * sl_p,
|
||||
__u8 * rate_p);
|
||||
|
||||
#endif /* __ib_mad_h__ */
|
||||
|
||||
@ -92,12 +92,7 @@ static int find_mlx_bridge(__u8 hca_bus, __u8 * br_bus_p, __u8 * br_devfn_p)
|
||||
for (bus = 0; bus < 256; ++bus) {
|
||||
for (dev = 0; dev < 32; ++dev) {
|
||||
devfn = (dev << 3);
|
||||
|
||||
struct pci_device tmp;
|
||||
tmp.bus = bus;
|
||||
tmp.devfn = devfn;
|
||||
|
||||
rc = pcibios_read_config_word(&tmp, PCI_VENDOR_ID,
|
||||
rc = pcibios_read_config_word(bus, devfn, PCI_VENDOR_ID,
|
||||
&vendor);
|
||||
if (rc)
|
||||
return rc;
|
||||
@ -105,7 +100,7 @@ static int find_mlx_bridge(__u8 hca_bus, __u8 * br_bus_p, __u8 * br_devfn_p)
|
||||
if (vendor != MELLANOX_VENDOR_ID)
|
||||
continue;
|
||||
|
||||
rc = pcibios_read_config_word(&tmp, PCI_DEVICE_ID,
|
||||
rc = pcibios_read_config_word(bus, devfn, PCI_DEVICE_ID,
|
||||
&dev_id);
|
||||
if (rc)
|
||||
return rc;
|
||||
@ -113,7 +108,7 @@ static int find_mlx_bridge(__u8 hca_bus, __u8 * br_bus_p, __u8 * br_devfn_p)
|
||||
if (dev_id != TAVOR_BRIDGE_DEVICE_ID)
|
||||
continue;
|
||||
|
||||
rc = pcibios_read_config_byte(&tmp,
|
||||
rc = pcibios_read_config_byte(bus, devfn,
|
||||
PCI_SECONDARY_BUS,
|
||||
&sec_bus);
|
||||
if (rc)
|
||||
@ -166,7 +161,7 @@ static int ib_device_init(struct pci_device *dev)
|
||||
tavor_pci_dev.dev.dev = dev;
|
||||
|
||||
tprintf("");
|
||||
if (dev->device == TAVOR_DEVICE_ID) {
|
||||
if (dev->dev_id == TAVOR_DEVICE_ID) {
|
||||
|
||||
rc = find_mlx_bridge(dev->bus, &br_bus, &br_devfn);
|
||||
if (rc) {
|
||||
@ -180,12 +175,7 @@ static int ib_device_init(struct pci_device *dev)
|
||||
tprintf("bus=%d devfn=0x%x", br_bus, br_devfn);
|
||||
/* save config space */
|
||||
for (i = 0; i < 64; ++i) {
|
||||
|
||||
struct pci_device tmp;
|
||||
tmp.bus = br_bus;
|
||||
tmp.devfn = br_devfn;
|
||||
|
||||
rc = pcibios_read_config_dword(&tmp, i << 2,
|
||||
rc = pcibios_read_config_dword(br_bus, br_devfn, i << 2,
|
||||
&tavor_pci_dev.br.
|
||||
dev_config_space[i]);
|
||||
if (rc) {
|
||||
@ -213,7 +203,7 @@ static int ib_device_init(struct pci_device *dev)
|
||||
eprintf("");
|
||||
return -1;
|
||||
}
|
||||
tprintf("uar_base (pa:va) = 0x%lx %p",
|
||||
tprintf("uar_base (pa:va) = 0x%lx 0x%lx",
|
||||
tavor_pci_dev.dev.bar[2] + UAR_IDX * 0x1000, tavor_pci_dev.uar);
|
||||
|
||||
tprintf("");
|
||||
@ -235,7 +225,7 @@ static int init_dev_data(void)
|
||||
|
||||
dev_buffers_p = bus_to_virt(tmp);
|
||||
memreg_size = (__u32) (&memreg_size) - (__u32) dev_buffers_p;
|
||||
tprintf("src_buf=%p, dev_buffers_p=%p, memreg_size=0x%lx", src_buf,
|
||||
tprintf("src_buf=0x%lx, dev_buffers_p=0x%lx, memreg_size=0x%x", src_buf,
|
||||
dev_buffers_p, memreg_size);
|
||||
|
||||
return 0;
|
||||
@ -246,14 +236,10 @@ static int restore_config(void)
|
||||
int i;
|
||||
int rc;
|
||||
|
||||
if (tavor_pci_dev.dev.dev->device == TAVOR_DEVICE_ID) {
|
||||
if (tavor_pci_dev.dev.dev->dev_id == TAVOR_DEVICE_ID) {
|
||||
for (i = 0; i < 64; ++i) {
|
||||
|
||||
struct pci_device tmp;
|
||||
tmp.bus = tavor_pci_dev.br.bus;
|
||||
tmp.devfn = tavor_pci_dev.br.devfn;
|
||||
|
||||
rc = pcibios_write_config_dword(&tmp,
|
||||
rc = pcibios_write_config_dword(tavor_pci_dev.br.bus,
|
||||
tavor_pci_dev.br.devfn,
|
||||
i << 2,
|
||||
tavor_pci_dev.br.
|
||||
dev_config_space[i]);
|
||||
@ -565,9 +551,9 @@ static int setup_hca(__u8 port, void **eq_p)
|
||||
tprintf("fw_rev_major=%d", qfw.fw_rev_major);
|
||||
tprintf("fw_rev_minor=%d", qfw.fw_rev_minor);
|
||||
tprintf("fw_rev_subminor=%d", qfw.fw_rev_subminor);
|
||||
tprintf("error_buf_start_h=0x%lx", qfw.error_buf_start_h);
|
||||
tprintf("error_buf_start_l=0x%lx", qfw.error_buf_start_l);
|
||||
tprintf("error_buf_size=%ld", qfw.error_buf_size);
|
||||
tprintf("error_buf_start_h=0x%x", qfw.error_buf_start_h);
|
||||
tprintf("error_buf_start_l=0x%x", qfw.error_buf_start_l);
|
||||
tprintf("error_buf_size=%d", qfw.error_buf_size);
|
||||
}
|
||||
|
||||
if (qfw.error_buf_start_h) {
|
||||
@ -813,20 +799,6 @@ static int setup_hca(__u8 port, void **eq_p)
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
static int unset_hca(void)
|
||||
{
|
||||
int rc = 0;
|
||||
|
||||
if (!fw_fatal) {
|
||||
rc = cmd_sys_dis();
|
||||
if (rc)
|
||||
eprintf("");
|
||||
}
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
static void *get_inprm_buf(void)
|
||||
{
|
||||
return dev_buffers_p->inprm_buf;
|
||||
@ -958,7 +930,7 @@ static int post_send_req(void *qph, void *wqeh, __u8 num_gather)
|
||||
__u32 *psrc, *pdst;
|
||||
__u32 nds;
|
||||
|
||||
tprintf("snd_wqe=%p, virt_to_bus(snd_wqe)=0x%lx", snd_wqe,
|
||||
tprintf("snd_wqe=0x%lx, virt_to_bus(snd_wqe)=0x%lx", snd_wqe,
|
||||
virt_to_bus(snd_wqe));
|
||||
|
||||
memset(&dbell, 0, sizeof dbell);
|
||||
@ -1082,7 +1054,7 @@ static int create_ipoib_qp(void **qp_pp,
|
||||
/* update data */
|
||||
qp->rcv_wq[i].wqe_cont.qp = qp;
|
||||
qp->rcv_bufs[i] = ib_buffers.ipoib_rcv_buf[i];
|
||||
tprintf("rcv_buf=%p", qp->rcv_bufs[i]);
|
||||
tprintf("rcv_buf=%lx", qp->rcv_bufs[i]);
|
||||
}
|
||||
|
||||
/* init send queue WQEs list */
|
||||
@ -1415,7 +1387,7 @@ static int ib_poll_cq(void *cqh, struct ib_cqe_st *ib_cqe_p, u8 * num_cqes)
|
||||
eprintf("syndrome=0x%lx",
|
||||
EX_FLD(cqe.error_cqe, tavorprm_completion_with_error_st,
|
||||
syndrome));
|
||||
eprintf("wqe_addr=%p", wqe_p);
|
||||
eprintf("wqe_addr=0x%lx", wqe_p);
|
||||
eprintf("wqe_size=0x%lx",
|
||||
EX_FLD(cqe.error_cqe, tavorprm_completion_with_error_st,
|
||||
wqe_size));
|
||||
@ -1544,7 +1516,7 @@ static struct recv_wqe_st *alloc_rcv_wqe(struct udqp_st *qp)
|
||||
wqe->mpointer[1].lkey = dev_ib_data.mkey;
|
||||
wqe->mpointer[1].byte_count = qp->rcv_buf_sz;
|
||||
|
||||
tprintf("rcv_buf=%p\n", qp->rcv_bufs[new_entry]);
|
||||
tprintf("rcv_buf=%lx\n", qp->rcv_bufs[new_entry]);
|
||||
|
||||
/* we do it only on the data segment since the control
|
||||
segment is always owned by HW */
|
||||
@ -1671,7 +1643,7 @@ static int poll_eq(struct ib_eqe_st *ib_eqe_p, __u8 * num_eqes)
|
||||
struct eq_st *eq = &dev_ib_data.eq;
|
||||
|
||||
ptr = (__u32 *) (&(eq->eq_buf[eq->cons_idx]));
|
||||
tprintf("cons)idx=%ld, addr(eqe)=%lx, val=0x%lx", eq->cons_idx, virt_to_bus(ptr), ptr[7]);
|
||||
tprintf("cons)idx=%d, addr(eqe)=%x, val=0x%x", eq->cons_idx, virt_to_bus(ptr), ptr[7]);
|
||||
owner = (ptr[7] & 0x80000000) ? OWNER_HW : OWNER_SW;
|
||||
if (owner == OWNER_SW) {
|
||||
tprintf("got eqe");
|
||||
|
||||
@ -89,10 +89,6 @@ static struct dev_pci_struct memfree_pci_dev;
|
||||
static struct device_buffers_st *dev_buffers_p;
|
||||
static struct device_ib_data_st dev_ib_data;
|
||||
|
||||
|
||||
|
||||
struct map_icm_st icm_map_obj;
|
||||
|
||||
static int gw_write_cr(__u32 addr, __u32 data)
|
||||
{
|
||||
writel(htonl(data), memfree_pci_dev.cr_space + addr);
|
||||
@ -159,7 +155,7 @@ static int ib_device_init(struct pci_device *dev)
|
||||
eprintf("");
|
||||
return -1;
|
||||
}
|
||||
tprintf("uar_base (pa:va) = 0x%lx %p",
|
||||
tprintf("uar_base (pa:va) = 0x%lx 0x%lx",
|
||||
memfree_pci_dev.dev.bar[2] + UAR_IDX * 0x1000,
|
||||
memfree_pci_dev.uar);
|
||||
|
||||
@ -174,8 +170,6 @@ static inline unsigned long lalign(unsigned long buf, unsigned long align)
|
||||
(~(((unsigned long)align) - 1)));
|
||||
}
|
||||
|
||||
#include <gpxe/umalloc.h>
|
||||
|
||||
static int init_dev_data(void)
|
||||
{
|
||||
unsigned long tmp;
|
||||
@ -185,21 +179,17 @@ static int init_dev_data(void)
|
||||
|
||||
dev_buffers_p = bus_to_virt(tmp);
|
||||
memreg_size = (__u32) (&memreg_size) - (__u32) dev_buffers_p;
|
||||
tprintf("src_buf=%p, dev_buffers_p=%p, memreg_size=0x%lx", src_buf,
|
||||
tprintf("src_buf=0x%lx, dev_buffers_p=0x%lx, memreg_size=0x%x", src_buf,
|
||||
dev_buffers_p, memreg_size);
|
||||
|
||||
tprintf("inprm: va=%p, pa=0x%lx", dev_buffers_p->inprm_buf,
|
||||
tprintf("inprm: va=0x%lx, pa=0x%lx", dev_buffers_p->inprm_buf,
|
||||
virt_to_bus(dev_buffers_p->inprm_buf));
|
||||
tprintf("outprm: va=%p, pa=0x%lx", dev_buffers_p->outprm_buf,
|
||||
tprintf("outprm: va=0x%lx, pa=0x%lx", dev_buffers_p->outprm_buf,
|
||||
virt_to_bus(dev_buffers_p->outprm_buf));
|
||||
|
||||
userptr_t lotsofmem = umalloc ( reserve_size * 2 );
|
||||
if ( ! lotsofmem ) {
|
||||
printf ( "Could not allocate large memblock\n" );
|
||||
return -1;
|
||||
}
|
||||
phys_mem.base = ( ( user_to_phys ( lotsofmem, 0 ) + reserve_size ) &
|
||||
~( reserve_size - 1 ) );
|
||||
phys_mem.base =
|
||||
(virt_to_phys(_text) - reserve_size) & (~(reserve_size - 1));
|
||||
|
||||
phys_mem.offset = 0;
|
||||
|
||||
return 0;
|
||||
@ -333,13 +323,9 @@ static void prep_sw2hw_mpt_buf(void *buf, __u32 mkey)
|
||||
INS_FLD(1, buf, arbelprm_mpt_st, r_w);
|
||||
INS_FLD(mkey, buf, arbelprm_mpt_st, mem_key);
|
||||
INS_FLD(GLOBAL_PD, buf, arbelprm_mpt_st, pd);
|
||||
// INS_FLD(virt_to_bus(dev_buffers_p), buf, arbelprm_mpt_st,
|
||||
// start_address_l);
|
||||
// INS_FLD(memreg_size, buf, arbelprm_mpt_st, reg_wnd_len_l);
|
||||
INS_FLD(0, buf, arbelprm_mpt_st, start_address_l);
|
||||
INS_FLD(0, buf, arbelprm_mpt_st, start_address_h);
|
||||
INS_FLD(0xffffffffUL, buf, arbelprm_mpt_st, reg_wnd_len_l);
|
||||
INS_FLD(0xffffffffUL, buf, arbelprm_mpt_st, reg_wnd_len_h);
|
||||
INS_FLD(virt_to_bus(dev_buffers_p), buf, arbelprm_mpt_st,
|
||||
start_address_l);
|
||||
INS_FLD(memreg_size, buf, arbelprm_mpt_st, reg_wnd_len_l);
|
||||
}
|
||||
|
||||
static void prep_sw2hw_eq_buf(void *buf, struct eqe_t *eq_buf)
|
||||
@ -675,9 +661,9 @@ static int setup_hca(__u8 port, void **eq_p)
|
||||
tprintf("fw_rev_major=%d", qfw.fw_rev_major);
|
||||
tprintf("fw_rev_minor=%d", qfw.fw_rev_minor);
|
||||
tprintf("fw_rev_subminor=%d", qfw.fw_rev_subminor);
|
||||
tprintf("error_buf_start_h=0x%lx", qfw.error_buf_start_h);
|
||||
tprintf("error_buf_start_l=0x%lx", qfw.error_buf_start_l);
|
||||
tprintf("error_buf_size=%ld", qfw.error_buf_size);
|
||||
tprintf("error_buf_start_h=0x%x", qfw.error_buf_start_h);
|
||||
tprintf("error_buf_start_l=0x%x", qfw.error_buf_start_l);
|
||||
tprintf("error_buf_size=%d", qfw.error_buf_size);
|
||||
}
|
||||
|
||||
|
||||
@ -758,20 +744,17 @@ static int setup_hca(__u8 port, void **eq_p)
|
||||
tmp = get_req_icm_pages(dev_lim.log2_rsvd_qps,
|
||||
MAX_APP_QPS,
|
||||
dev_lim.qpc_entry_sz, &log2_entries);
|
||||
DBG ( "qpc_base_addr_l = %lx\n", icm_start );
|
||||
init_hca.qpc_base_addr_l = icm_start;
|
||||
init_hca.log_num_of_qp = log2_entries;
|
||||
icm_start += (tmp << 12);
|
||||
icm_size += (tmp << 12);
|
||||
|
||||
DBG ( "eqpc_base_addr_l = %lx\n", icm_start );
|
||||
init_hca.eqpc_base_addr_l = icm_start;
|
||||
icm_start += (tmp << 12);
|
||||
icm_size += (tmp << 12);
|
||||
|
||||
tmp = get_req_icm_pages(dev_lim.log2_rsvd_srqs,
|
||||
0, dev_lim.srq_entry_sz, &log2_entries);
|
||||
DBG ( "srqc_base_addr_l = %lx\n", icm_start );
|
||||
init_hca.srqc_base_addr_l = icm_start;
|
||||
init_hca.log_num_of_srq = log2_entries;
|
||||
icm_start += (tmp << 12);
|
||||
@ -779,18 +762,15 @@ static int setup_hca(__u8 port, void **eq_p)
|
||||
|
||||
tmp = get_req_icm_pages(dev_lim.log2_rsvd_ees,
|
||||
0, dev_lim.eec_entry_sz, &log2_entries);
|
||||
DBG ( "eec_base_addr_l = %lx\n", icm_start );
|
||||
init_hca.eec_base_addr_l = icm_start;
|
||||
init_hca.log_num_of_ee = log2_entries;
|
||||
icm_start += (tmp << 12);
|
||||
icm_size += (tmp << 12);
|
||||
|
||||
DBG ( "eeec_base_addr_l = %lx\n", icm_start );
|
||||
init_hca.eeec_base_addr_l = icm_start;
|
||||
icm_start += (tmp << 12);
|
||||
icm_size += (tmp << 12);
|
||||
|
||||
DBG ( "cqc_base_addr_l = %lx\n", icm_start );
|
||||
tmp = get_req_icm_pages(dev_lim.log2_rsvd_cqs,
|
||||
MAX_APP_CQS,
|
||||
dev_lim.cqc_entry_sz, &log2_entries);
|
||||
@ -801,35 +781,29 @@ static int setup_hca(__u8 port, void **eq_p)
|
||||
|
||||
tmp = get_req_icm_pages(dev_lim.log2_rsvd_mtts,
|
||||
0, dev_lim.mtt_entry_sz, &log2_entries);
|
||||
DBG ( "mtt_base_addr_l = %lx\n", icm_start );
|
||||
init_hca.mtt_base_addr_l = icm_start;
|
||||
icm_start += (tmp << 12);
|
||||
icm_size += (tmp << 12);
|
||||
|
||||
tmp = get_req_icm_pages(dev_lim.log2_rsvd_mrws,
|
||||
1, dev_lim.mpt_entry_sz, &log2_entries);
|
||||
DBG ( "mpt_base_addr_l = %lx\n", icm_start );
|
||||
init_hca.mpt_base_addr_l = icm_start;
|
||||
init_hca.log_mpt_sz = log2_entries;
|
||||
DBG ( "log2_entries for mpt = %ld\n", log2_entries );
|
||||
icm_start += (tmp << 12);
|
||||
icm_size += (tmp << 12);
|
||||
|
||||
tmp = get_req_icm_pages(dev_lim.log2_rsvd_rdbs, 1, 32, /* size of rdb entry */
|
||||
&log2_entries);
|
||||
DBG ( "rdb_base_addr_l = %lx\n", icm_start );
|
||||
init_hca.rdb_base_addr_l = icm_start;
|
||||
icm_start += (tmp << 12);
|
||||
icm_size += (tmp << 12);
|
||||
|
||||
DBG ( "eqc_base_addr_l = %lx\n", icm_start );
|
||||
init_hca.eqc_base_addr_l = icm_start;
|
||||
init_hca.log_num_of_eq = LOG2_EQS;
|
||||
tmp = dev_lim.eqc_entry_sz * (1 << LOG2_EQS);
|
||||
icm_start += tmp;
|
||||
icm_size += tmp;
|
||||
|
||||
DBG ( "mc_base_addr_l = %lx\n", icm_start );
|
||||
init_hca.mc_base_addr_l = icm_start;
|
||||
init_hca.log_mc_table_entry_sz =
|
||||
my_log2(MT_STRUCT_SIZE(arbelprm_mgm_entry_st));
|
||||
@ -840,8 +814,6 @@ static int setup_hca(__u8 port, void **eq_p)
|
||||
icm_start +=
|
||||
(MT_STRUCT_SIZE(arbelprm_mgm_entry_st) * init_hca.mc_table_hash_sz);
|
||||
|
||||
DBG ( "icm_size = %lx\n", icm_size );
|
||||
|
||||
rc = cmd_set_icm_size(icm_size, &aux_pages);
|
||||
if (rc) {
|
||||
ret = -1;
|
||||
@ -864,7 +836,7 @@ static int setup_hca(__u8 port, void **eq_p)
|
||||
uar_context_pa = phys_mem.base + phys_mem.offset +
|
||||
dev_ib_data.uar_idx * 4096;
|
||||
uar_context_va = phys_to_virt(uar_context_pa);
|
||||
tprintf("uar_context: va=%p, pa=0x%lx", uar_context_va,
|
||||
tprintf("uar_context: va=0x%lx, pa=0x%lx", uar_context_va,
|
||||
uar_context_pa);
|
||||
dev_ib_data.uar_context_base = uar_context_va;
|
||||
|
||||
@ -878,12 +850,10 @@ static int setup_hca(__u8 port, void **eq_p)
|
||||
eprintf("");
|
||||
goto undo_map_fa;
|
||||
}
|
||||
icm_map_obj = map_obj;
|
||||
|
||||
phys_mem.offset += (1 << (map_obj.vpm_arr[0].log2_size + 12));
|
||||
|
||||
init_hca.log_max_uars = log_max_uars;
|
||||
tprintf("inprm: va=%p, pa=0x%lx", inprm, virt_to_bus(inprm));
|
||||
tprintf("inprm: va=0x%lx, pa=0x%lx", inprm, virt_to_bus(inprm));
|
||||
prep_init_hca_buf(&init_hca, inprm);
|
||||
rc = cmd_init_hca(inprm, MT_STRUCT_SIZE(arbelprm_init_hca_st));
|
||||
if (rc) {
|
||||
@ -1008,30 +978,6 @@ static int setup_hca(__u8 port, void **eq_p)
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
static int unset_hca(void)
|
||||
{
|
||||
int rc, ret = 0;
|
||||
|
||||
rc = cmd_unmap_icm(&icm_map_obj);
|
||||
if (rc)
|
||||
eprintf("");
|
||||
ret |= rc;
|
||||
|
||||
|
||||
rc = cmd_unmap_icm_aux();
|
||||
if (rc)
|
||||
eprintf("");
|
||||
ret |= rc;
|
||||
|
||||
rc = cmd_unmap_fa();
|
||||
if (rc)
|
||||
eprintf("");
|
||||
ret |= rc;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void *get_inprm_buf(void)
|
||||
{
|
||||
return dev_buffers_p->inprm_buf;
|
||||
@ -1140,14 +1086,9 @@ static int post_send_req(void *qph, void *wqeh, __u8 num_gather)
|
||||
struct send_doorbell_st dbell;
|
||||
__u32 nds;
|
||||
|
||||
DBG ( "Work queue entry:\n" );
|
||||
DBG_HD ( snd_wqe, sizeof ( *snd_wqe ) );
|
||||
|
||||
qp->post_send_counter++;
|
||||
|
||||
WRITE_WORD_VOL(qp->send_uar_context, 2, htons(qp->post_send_counter));
|
||||
DBG ( "Doorbell record:\n" );
|
||||
DBG_HD ( qp->send_uar_context, 8 );
|
||||
|
||||
memset(&dbell, 0, sizeof dbell);
|
||||
INS_FLD(XDEV_NOPCODE_SEND, &dbell, arbelprm_send_doorbell_st, nopcode);
|
||||
@ -1171,10 +1112,6 @@ static int post_send_req(void *qph, void *wqeh, __u8 num_gather)
|
||||
INS_FLD_TO_BE(XDEV_NOPCODE_SEND,
|
||||
&qp->last_posted_snd_wqe->next.next,
|
||||
arbelprm_wqe_segment_next_st, nopcode);
|
||||
|
||||
DBG ( "Previous work queue entry's next field:\n" );
|
||||
DBG_HD ( &qp->last_posted_snd_wqe->next.next,
|
||||
sizeof ( qp->last_posted_snd_wqe->next.next ) );
|
||||
}
|
||||
|
||||
rc = cmd_post_doorbell(&dbell, POST_SND_OFFSET);
|
||||
@ -1195,8 +1132,6 @@ static int create_mads_qp(void **qp_pp, void **snd_cq_pp, void **rcv_cq_pp)
|
||||
__u8 nds;
|
||||
void *ptr;
|
||||
|
||||
DBG ( "*** Creating MADS queue pair ***\n" );
|
||||
|
||||
qp = &dev_ib_data.mads_qp;
|
||||
|
||||
/* set the pointer to the receive WQEs buffer */
|
||||
@ -1307,8 +1242,6 @@ static int create_mads_qp(void **qp_pp, void **snd_cq_pp, void **rcv_cq_pp)
|
||||
*rcv_cq_pp = &qp->rcv_cq;
|
||||
}
|
||||
|
||||
DBG ( "*** Created MADS queue pair ***\n" );
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
@ -1322,8 +1255,6 @@ static int create_ipoib_qp(void **qp_pp,
|
||||
__u8 nds;
|
||||
void *ptr;
|
||||
|
||||
DBG ( "*** Creating IPoIB queue pair ***\n" );
|
||||
|
||||
qp = &dev_ib_data.ipoib_qp;
|
||||
|
||||
/* set the pointer to the receive WQEs buffer */
|
||||
@ -1333,7 +1264,7 @@ static int create_ipoib_qp(void **qp_pp,
|
||||
qp->rcv_buf_sz = IPOIB_RCV_BUF_SZ;
|
||||
|
||||
qp->max_recv_wqes = NUM_IPOIB_RCV_WQES;
|
||||
qp->recv_wqe_cur_free = 0; //NUM_IPOIB_RCV_WQES;
|
||||
qp->recv_wqe_cur_free = NUM_IPOIB_RCV_WQES;
|
||||
|
||||
qp->rcv_uar_context =
|
||||
dev_ib_data.uar_context_base + 8 * IPOIB_RCV_QP_DB_IDX;
|
||||
@ -1429,8 +1360,6 @@ static int create_ipoib_qp(void **qp_pp,
|
||||
*rcv_cq_pp = &qp->rcv_cq;
|
||||
}
|
||||
|
||||
DBG ( "*** Created IPoIB queue pair ***\n" );
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
@ -1451,8 +1380,6 @@ static int create_udqp(struct udqp_st *qp)
|
||||
qp->snd_cq.ci_db_ctx_pointer =
|
||||
dev_ib_data.uar_context_base + 8 * qp->snd_cq.ci_db_ctx_idx;
|
||||
|
||||
DBG ( "* Creating send CQ *\n" );
|
||||
|
||||
/* create send CQ */
|
||||
init_cq_buf(qp->snd_cq.cq_buf, qp->snd_cq.num_cqes);
|
||||
qp->snd_cq.cons_counter = 0;
|
||||
@ -1469,8 +1396,6 @@ static int create_udqp(struct udqp_st *qp)
|
||||
goto exit;
|
||||
}
|
||||
|
||||
DBG ( "* Creating receive CQ *\n" );
|
||||
|
||||
/* create receive CQ */
|
||||
init_cq_buf(qp->rcv_cq.cq_buf, qp->rcv_cq.num_cqes);
|
||||
qp->rcv_cq.cons_counter = 0;
|
||||
@ -1488,8 +1413,6 @@ static int create_udqp(struct udqp_st *qp)
|
||||
goto undo_snd_cq;
|
||||
}
|
||||
|
||||
DBG ( "* Creating QP *\n" );
|
||||
|
||||
prep_rst2init_qpee_buf(inprm,
|
||||
qp->snd_cq.cqn,
|
||||
qp->rcv_cq.cqn,
|
||||
@ -1627,15 +1550,6 @@ static void prep_send_wqe_buf(void *qph,
|
||||
len += offset;
|
||||
}
|
||||
snd_wqe->mpointer[0].byte_count = cpu_to_be32(len);
|
||||
|
||||
#if 0
|
||||
DBG ( "prep_send_wqe_buf()\n" );
|
||||
DBG ( "snd_wqe:\n" );
|
||||
DBG_HD ( snd_wqe, sizeof ( *snd_wqe ) );
|
||||
DBG ( "packet:\n" );
|
||||
DBG_HD ( bus_to_virt(be32_to_cpu(snd_wqe->mpointer[0].local_addr_l)),
|
||||
len );
|
||||
#endif
|
||||
}
|
||||
|
||||
static void *alloc_ud_av(void)
|
||||
@ -1744,7 +1658,7 @@ static void dev2ib_cqe(struct ib_cqe_st *ib_cqe_p, union cqe_st *cqe_p)
|
||||
byte_cnt);
|
||||
}
|
||||
|
||||
static int ib_poll_cqx(void *cqh, struct ib_cqe_st *ib_cqe_p, u8 * num_cqes)
|
||||
static int ib_poll_cq(void *cqh, struct ib_cqe_st *ib_cqe_p, u8 * num_cqes)
|
||||
{
|
||||
int rc;
|
||||
union cqe_st cqe;
|
||||
@ -1776,7 +1690,7 @@ static int ib_poll_cqx(void *cqh, struct ib_cqe_st *ib_cqe_p, u8 * num_cqes)
|
||||
eprintf("vendor_syndrome=0x%lx",
|
||||
EX_FLD(cqe.error_cqe, arbelprm_completion_with_error_st,
|
||||
vendor_code));
|
||||
eprintf("wqe_addr=%p", wqe_p);
|
||||
eprintf("wqe_addr=0x%lx", wqe_p);
|
||||
eprintf("myqpn=0x%lx",
|
||||
EX_FLD(cqe.error_cqe, arbelprm_completion_with_error_st,
|
||||
myqpn));
|
||||
@ -2006,9 +1920,6 @@ static void dev_post_dbell(void *dbell, __u32 offset)
|
||||
address = (unsigned long)(memfree_pci_dev.uar) + offset;
|
||||
tprintf("va=0x%lx pa=0x%lx", address,
|
||||
virt_to_bus((const void *)address));
|
||||
DBG ( "dev_post_dbell %08lx:%08lx to %lx\n",
|
||||
htonl ( ptr[0] ), htonl ( ptr[1] ),
|
||||
virt_to_phys ( memfree_pci_dev.uar + offset ) );
|
||||
writel(htonl(ptr[0]), memfree_pci_dev.uar + offset);
|
||||
barrier();
|
||||
address += 4;
|
||||
|
||||
@ -357,12 +357,52 @@ static void modify_dhcp_resp(void *buf, __u16 size)
|
||||
modify_udp_csum(buf, size);
|
||||
}
|
||||
|
||||
static void get_my_client_id(__u8 * my_client_id)
|
||||
{
|
||||
|
||||
my_client_id[0] = 0;
|
||||
qpn2buf(ipoib_data.ipoib_qpn, my_client_id + 1);
|
||||
memcpy(my_client_id + 4, ipoib_data.port_gid_raw, 16);
|
||||
}
|
||||
|
||||
static const __u8 *get_client_id(const void *buf, int len)
|
||||
{
|
||||
const __u8 *ptr;
|
||||
int delta;
|
||||
|
||||
if (len < 268)
|
||||
return NULL;
|
||||
|
||||
/* pointer to just after magic cookie */
|
||||
ptr = (const __u8 *)buf + 268;
|
||||
|
||||
/* find last client identifier option */
|
||||
do {
|
||||
if (ptr[0] == 255) {
|
||||
/* found end of options list */
|
||||
return NULL;
|
||||
}
|
||||
|
||||
if (ptr[0] == 0x3d) {
|
||||
/* client identifer option */
|
||||
return ptr + 3;
|
||||
}
|
||||
|
||||
delta = ptr[1] + 2;
|
||||
ptr += delta;
|
||||
len -= delta;
|
||||
} while (len > 0);
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static int handle_ipv4_packet(void *buf, void **out_buf_p,
|
||||
unsigned int *new_size_p, int *is_bcast_p)
|
||||
{
|
||||
void *new_buf;
|
||||
__u16 new_size;
|
||||
__u8 msg_type;
|
||||
__u8 my_client_id[20];
|
||||
|
||||
new_buf = (void *)(((__u8 *) buf) + 4);
|
||||
new_size = (*new_size_p) - 4;
|
||||
@ -371,6 +411,7 @@ static int handle_ipv4_packet(void *buf, void **out_buf_p,
|
||||
|
||||
if (get_ip_protocl(new_buf) == IP_PROT_UDP) {
|
||||
__u16 udp_dst_port;
|
||||
const __u8 *client_id;
|
||||
|
||||
udp_dst_port = get_udp_dst_port(new_buf);
|
||||
|
||||
@ -379,6 +420,22 @@ static int handle_ipv4_packet(void *buf, void **out_buf_p,
|
||||
*out_buf_p = 0;
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (udp_dst_port == 68) {
|
||||
get_my_client_id(my_client_id);
|
||||
|
||||
/* packet client id */
|
||||
client_id = get_client_id(new_buf, new_size);
|
||||
if (!client_id) {
|
||||
*out_buf_p = 0;
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (memcmp(client_id, my_client_id, 20)) {
|
||||
*out_buf_p = 0;
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
msg_type = get_dhcp_msg_type(new_buf);
|
||||
@ -458,9 +515,8 @@ static int ipoib_handle_rcv(void *buf, void **out_buf_p,
|
||||
rc = handle_ipv4_packet(buf, out_buf_p, new_size_p, is_bcast_p);
|
||||
return rc;
|
||||
}
|
||||
tprintf("prot=0x%x", prot_type);
|
||||
*out_buf_p = NULL;
|
||||
return 0;
|
||||
eprintf("prot=0x%x", prot_type);
|
||||
return -1;
|
||||
}
|
||||
|
||||
static int is_null_mac(const __u8 * mac)
|
||||
@ -879,7 +935,7 @@ static int ipoib_read_packet(__u16 * prot_p, void *data, unsigned int *size_p,
|
||||
void *buf, *out_buf;
|
||||
__u16 prot_type;
|
||||
|
||||
rc = ib_poll_cqx(ipoib_data.rcv_cqh, &ib_cqe, &num_cqes);
|
||||
rc = ib_poll_cq(ipoib_data.rcv_cqh, &ib_cqe, &num_cqes);
|
||||
if (rc) {
|
||||
return rc;
|
||||
}
|
||||
@ -897,7 +953,7 @@ static int ipoib_read_packet(__u16 * prot_p, void *data, unsigned int *size_p,
|
||||
|
||||
new_size = ib_cqe.count - GRH_SIZE;
|
||||
buf = get_rcv_wqe_buf(ib_cqe.wqe, 1);
|
||||
tprintf("buf=%p", buf);
|
||||
tprintf("buf=%lx", buf);
|
||||
rc = ipoib_handle_rcv(buf, &out_buf, &new_size, is_bcast_p);
|
||||
if (rc) {
|
||||
eprintf("");
|
||||
@ -944,7 +1000,7 @@ static int ipoib_init(struct pci_device *pci)
|
||||
ipoib_data.ipoib_qpn = ib_get_qpn(qph);
|
||||
|
||||
if(print_info)
|
||||
printf("local ipoib qpn=0x%lx\n", ipoib_data.ipoib_qpn);
|
||||
printf("local ipoib qpn=0x%x\n", ipoib_data.ipoib_qpn);
|
||||
|
||||
ipoib_data.bcast_av = ib_data.bcast_av;
|
||||
ipoib_data.port_gid_raw = ib_data.port_gid.raw;
|
||||
|
||||
@ -14,6 +14,10 @@ Skeleton NIC driver for Etherboot
|
||||
#include "etherboot.h"
|
||||
/* to get the interface to the body of the program */
|
||||
#include "nic.h"
|
||||
/* to get the PCI support functions, if this is a PCI NIC */
|
||||
#include <gpxe/pci.h>
|
||||
/* to get the ISA support functions, if this is an ISA NIC */
|
||||
#include <gpxe/isa.h>
|
||||
|
||||
#include "mt_version.c"
|
||||
#include "mt23108_imp.c"
|
||||
@ -148,7 +152,7 @@ static void tavor_transmit(struct nic *nic, const char *dest, /* Destination */
|
||||
/**************************************************************************
|
||||
DISABLE - Turn off ethernet interface
|
||||
***************************************************************************/
|
||||
static void tavor_disable(struct nic *nic)
|
||||
static void tavor_disable(struct dev *dev)
|
||||
{
|
||||
/* put the card in its initial state */
|
||||
/* This function serves 3 purposes.
|
||||
@ -160,24 +164,18 @@ static void tavor_disable(struct nic *nic)
|
||||
* This allows etherboot to reinitialize the interface
|
||||
* if something is something goes wrong.
|
||||
*/
|
||||
if (nic || 1) { // ????
|
||||
if (dev || 1) { // ????
|
||||
disable_imp();
|
||||
}
|
||||
}
|
||||
|
||||
static struct nic_operations tavor_operations = {
|
||||
.connect = dummy_connect,
|
||||
.poll = tavor_poll,
|
||||
.transmit = tavor_transmit,
|
||||
.irq = tavor_irq,
|
||||
};
|
||||
|
||||
/**************************************************************************
|
||||
PROBE - Look for an adapter, this routine's visible to the outside
|
||||
***************************************************************************/
|
||||
|
||||
static int tavor_probe(struct nic *nic, struct pci_device *pci)
|
||||
static int tavor_probe(struct dev *dev, struct pci_device *pci)
|
||||
{
|
||||
struct nic *nic = (struct nic *)dev;
|
||||
int rc;
|
||||
unsigned char user_request;
|
||||
|
||||
@ -221,7 +219,10 @@ static int tavor_probe(struct nic *nic, struct pci_device *pci)
|
||||
nic->ioaddr = pci->ioaddr & ~3;
|
||||
nic->irqno = pci->irq;
|
||||
/* point to NIC specific routines */
|
||||
nic->nic_op = &tavor_operations;
|
||||
dev->disable = tavor_disable;
|
||||
nic->poll = tavor_poll;
|
||||
nic->transmit = tavor_transmit;
|
||||
nic->irq = tavor_irq;
|
||||
|
||||
return 1;
|
||||
}
|
||||
@ -229,12 +230,16 @@ static int tavor_probe(struct nic *nic, struct pci_device *pci)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct pci_device_id tavor_nics[] = {
|
||||
static struct pci_id tavor_nics[] = {
|
||||
PCI_ROM(0x15b3, 0x5a44, "MT23108", "MT23108 HCA driver"),
|
||||
PCI_ROM(0x15b3, 0x6278, "MT25208", "MT25208 HCA driver"),
|
||||
};
|
||||
|
||||
PCI_DRIVER ( tavor_driver, tavor_nics, PCI_NO_CLASS );
|
||||
|
||||
DRIVER ( "MT23108/MT25208", nic_driver, pci_driver, tavor_driver,
|
||||
tavor_probe, tavor_disable );
|
||||
struct pci_driver tavor_driver __pci_driver = {
|
||||
.type = NIC_DRIVER,
|
||||
.name = "MT23108/MT25208",
|
||||
.probe = tavor_probe,
|
||||
.ids = tavor_nics,
|
||||
.id_count = sizeof(tavor_nics) / sizeof(tavor_nics[0]),
|
||||
.class = 0,
|
||||
};
|
||||
|
||||
@ -91,12 +91,10 @@ static int transmit_imp(const char *dest, /* Destination */
|
||||
rc = ipoib_send_packet(dest, type, packet, size);
|
||||
if (rc) {
|
||||
printf("*** ERROR IN SEND FLOW ***\n");
|
||||
#if 0
|
||||
printf("restarting Etherboot\n");
|
||||
sleep(1);
|
||||
longjmp(restart_etherboot, -1);
|
||||
/* we should not be here ... */
|
||||
#endif
|
||||
return -1;
|
||||
}
|
||||
|
||||
@ -108,7 +106,7 @@ static void hd(void *where, int n)
|
||||
int i;
|
||||
|
||||
while (n > 0) {
|
||||
printf("%p ", where);
|
||||
printf("%X ", where);
|
||||
for (i = 0; i < ((n > 16) ? 16 : n); i++)
|
||||
printf(" %hhX", ((char *)where)[i]);
|
||||
printf("\n");
|
||||
@ -224,11 +222,9 @@ static int poll_imp(struct nic *nic, int retrieve, unsigned int *size_p)
|
||||
|
||||
fatal_handling:
|
||||
printf("restarting Etherboot\n");
|
||||
#if 0
|
||||
sleep(1);
|
||||
longjmp(restart_etherboot, -1);
|
||||
/* we should not be here ... */
|
||||
#endif
|
||||
return -1;
|
||||
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -26,9 +26,7 @@
|
||||
#define MEMFREE_CMD_RUN_FW 0xff6
|
||||
#define MEMFREE_CMD_SET_ICM_SIZE 0xffd
|
||||
#define MEMFREE_CMD_MAP_ICM_AUX 0xffc
|
||||
#define MEMFREE_CMD_UNMAP_ICM_AUX 0xffb
|
||||
#define MEMFREE_CMD_MAP_ICM 0xffa
|
||||
#define MEMFREE_CMD_UNMAP_ICM 0xff9
|
||||
#define MEMFREE_CMD_QUERY_DEV_LIM 0x003
|
||||
|
||||
/*
|
||||
@ -146,24 +144,24 @@
|
||||
|
||||
/* uar context indexes */
|
||||
enum {
|
||||
MADS_SND_CQ_ARM_DB_IDX = MADS_SND_CQN_SN,
|
||||
MADS_RCV_CQ_ARM_DB_IDX = MADS_RCV_CQN_SN,
|
||||
IPOIB_SND_CQ_ARM_DB_IDX = IPOIB_SND_CQN_SN,
|
||||
IPOIB_RCV_CQ_ARM_DB_IDX = IPOIB_RCV_CQN_SN,
|
||||
MADS_SND_QP_DB_IDX = ( MAX_APP_CQS + MADS_QPN_SN ),
|
||||
IPOIB_SND_QP_DB_IDX = ( MAX_APP_CQS + IPOIB_QPN_SN ),
|
||||
GROUP_SEP_IDX = ( MAX_APP_CQS + MAX_APP_QPS ),
|
||||
// START_UNMAPPED_DB_IDX,
|
||||
MADS_RCV_CQ_ARM_DB_IDX,
|
||||
MADS_SND_CQ_ARM_DB_IDX,
|
||||
IPOIB_RCV_CQ_ARM_DB_IDX,
|
||||
IPOIB_SND_CQ_ARM_DB_IDX,
|
||||
MADS_SND_QP_DB_IDX,
|
||||
IPOIB_SND_QP_DB_IDX,
|
||||
GROUP_SEP_IDX,
|
||||
START_UNMAPPED_DB_IDX,
|
||||
/* --------------------------
|
||||
unmapped doorbell records
|
||||
-------------------------- */
|
||||
// END_UNMAPPED_DB_IDX,
|
||||
IPOIB_RCV_QP_DB_IDX = ( 512 - MAX_APP_CQS - IPOIB_QPN_SN - 1 ),
|
||||
MADS_RCV_QP_DB_IDX = ( 512 - MAX_APP_CQS - MADS_QPN_SN - 1 ),
|
||||
IPOIB_RCV_CQ_CI_DB_IDX = ( 512 - IPOIB_RCV_CQN_SN - 1 ),
|
||||
IPOIB_SND_CQ_CI_DB_IDX = ( 512 - IPOIB_SND_CQN_SN - 1 ),
|
||||
MADS_RCV_CQ_CI_DB_IDX = ( 512 - MADS_RCV_CQN_SN - 1 ),
|
||||
MADS_SND_CQ_CI_DB_IDX = ( 512 - MADS_SND_CQN_SN - 1 ),
|
||||
END_UNMAPPED_DB_IDX = 505,
|
||||
MADS_RCV_QP_DB_IDX = 506,
|
||||
IPOIB_RCV_QP_DB_IDX = 507,
|
||||
MADS_RCV_CQ_CI_DB_IDX = 508,
|
||||
MADS_SND_CQ_CI_DB_IDX = 509,
|
||||
IPOIB_RCV_CQ_CI_DB_IDX = 510,
|
||||
IPOIB_SND_CQ_CI_DB_IDX = 511
|
||||
};
|
||||
|
||||
/* uar resources types */
|
||||
@ -342,24 +340,6 @@ struct cq_dbell_st {
|
||||
__u8 raw[MT_STRUCT_SIZE(arbelprm_cq_cmd_doorbell_st)];
|
||||
} __attribute__ ((packed));
|
||||
|
||||
struct qp_db_record_st {
|
||||
__u8 raw[MT_STRUCT_SIZE(arbelprm_qp_db_record_st)];
|
||||
} __attribute__ ((packed));
|
||||
|
||||
struct cq_arm_db_record_st {
|
||||
__u8 raw[MT_STRUCT_SIZE(arbelprm_cq_arm_db_record_st)];
|
||||
} __attribute__ ((packed));
|
||||
|
||||
struct cq_ci_db_record_st {
|
||||
__u8 raw[MT_STRUCT_SIZE(arbelprm_cq_ci_db_record_st)];
|
||||
} __attribute__ ((packed));
|
||||
|
||||
union db_record_st {
|
||||
struct qp_db_record_st qp;
|
||||
struct cq_arm_db_record_st cq_arm;
|
||||
struct cq_ci_db_record_st cq_ci;
|
||||
} __attribute__ ((packed));
|
||||
|
||||
struct mad_ifc_inprm_st {
|
||||
union mad_u mad;
|
||||
} __attribute__ ((packed));
|
||||
|
||||
@ -45,7 +45,6 @@ static void be_to_cpu_buf(void *buf, int size)
|
||||
#include "ib_driver.c"
|
||||
#include "ipoib.c"
|
||||
|
||||
#if 0
|
||||
static int probe_imp(struct pci_device *pci, struct nic *nic)
|
||||
{
|
||||
int rc;
|
||||
@ -92,12 +91,10 @@ static int transmit_imp(const char *dest, /* Destination */
|
||||
rc = ipoib_send_packet(dest, type, packet, size);
|
||||
if (rc) {
|
||||
printf("*** ERROR IN SEND FLOW ***\n");
|
||||
#if 0
|
||||
printf("restarting Etherboot\n");
|
||||
sleep(1);
|
||||
longjmp(restart_etherboot, -1);
|
||||
/* we should not be here ... */
|
||||
#endif
|
||||
return -1;
|
||||
}
|
||||
|
||||
@ -109,7 +106,7 @@ static void hd(void *where, int n)
|
||||
int i;
|
||||
|
||||
while (n > 0) {
|
||||
printf("%p ", where);
|
||||
printf("%X ", where);
|
||||
for (i = 0; i < ((n > 16) ? 16 : n); i++)
|
||||
printf(" %hhX", ((char *)where)[i]);
|
||||
printf("\n");
|
||||
@ -224,13 +221,10 @@ static int poll_imp(struct nic *nic, int retrieve, unsigned int *size_p)
|
||||
return 0;
|
||||
|
||||
fatal_handling:
|
||||
#if 0
|
||||
printf("restarting Etherboot\n");
|
||||
sleep(1);
|
||||
longjmp(restart_etherboot, -1);
|
||||
/* we should not be here ... */
|
||||
#endif
|
||||
return -1;
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -20,4 +20,4 @@
|
||||
*/
|
||||
|
||||
/* definition of the build version goes here */
|
||||
const char *build_revision= "191";
|
||||
const char *build_revision= "113";
|
||||
|
||||
@ -1,7 +1,17 @@
|
||||
Index: dhcp-3.0.4b3/includes/site.h
|
||||
===================================================================
|
||||
--- dhcp-3.0.4b3.orig/includes/site.h 2002-03-12 20:33:39.000000000 +0200
|
||||
+++ dhcp-3.0.4b3/includes/site.h 2006-03-15 12:50:00.000000000 +0200
|
||||
diff -ru ../../orig/dhcp-3.0.4b2/common/options.c ./common/options.c
|
||||
--- ../../orig/dhcp-3.0.4b2/common/options.c 2005-11-02 01:19:03.000000000 +0200
|
||||
+++ ./common/options.c 2005-12-06 14:38:17.000000000 +0200
|
||||
@@ -537,6 +537,7 @@
|
||||
priority_list [priority_len++] = DHO_DHCP_LEASE_TIME;
|
||||
priority_list [priority_len++] = DHO_DHCP_MESSAGE;
|
||||
priority_list [priority_len++] = DHO_DHCP_REQUESTED_ADDRESS;
|
||||
+ priority_list [priority_len++] = DHO_DHCP_CLIENT_IDENTIFIER;
|
||||
priority_list [priority_len++] = DHO_FQDN;
|
||||
|
||||
if (prl && prl -> len > 0) {
|
||||
diff -ru ../../orig/dhcp-3.0.4b2/includes/site.h ./includes/site.h
|
||||
--- ../../orig/dhcp-3.0.4b2/includes/site.h 2002-03-12 20:33:39.000000000 +0200
|
||||
+++ ./includes/site.h 2005-12-06 14:36:55.000000000 +0200
|
||||
@@ -135,7 +135,7 @@
|
||||
the aforementioned problems do not matter to you, or if no other
|
||||
API is supported for your system, you may want to go with it. */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user