841 lines
25 KiB
C
841 lines
25 KiB
C
/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of Code Aurora Forum, Inc. nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* QUP driver for Qualcomm MSM platforms
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*
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*/
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#include <debug.h>
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#include <arch/arm.h>
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#include <reg.h>
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#include <kernel/thread.h>
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#include <i2c_qup.h>
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#include <platform/irqs.h>
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#include <platform/iomap.h>
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#include <platform/gpio_hw.h>
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static struct qup_i2c_dev *dev_addr = NULL;
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/* QUP Registers */
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enum {
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QUP_CONFIG = 0x0,
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QUP_STATE = 0x4,
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QUP_IO_MODE = 0x8,
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QUP_SW_RESET = 0xC,
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QUP_OPERATIONAL = 0x18,
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QUP_ERROR_FLAGS = 0x1C,
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QUP_ERROR_FLAGS_EN = 0x20,
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QUP_MX_READ_CNT = 0x208,
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QUP_MX_INPUT_CNT = 0x200,
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QUP_MX_WR_CNT = 0x100,
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QUP_OUT_DEBUG = 0x108,
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QUP_OUT_FIFO_CNT = 0x10C,
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QUP_OUT_FIFO_BASE = 0x110,
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QUP_IN_READ_CUR = 0x20C,
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QUP_IN_DEBUG = 0x210,
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QUP_IN_FIFO_CNT = 0x214,
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QUP_IN_FIFO_BASE = 0x218,
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QUP_I2C_CLK_CTL = 0x400,
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QUP_I2C_STATUS = 0x404,
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};
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/* QUP States and reset values */
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enum {
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QUP_RESET_STATE = 0,
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QUP_RUN_STATE = 1U,
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QUP_STATE_MASK = 3U,
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QUP_PAUSE_STATE = 3U,
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QUP_STATE_VALID = 1U << 2,
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QUP_I2C_MAST_GEN = 1U << 4,
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QUP_OPERATIONAL_RESET = 0xFF0,
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QUP_I2C_STATUS_RESET = 0xFFFFFC,
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};
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/* QUP OPERATIONAL FLAGS */
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enum {
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QUP_OUT_SVC_FLAG = 1U << 8,
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QUP_IN_SVC_FLAG = 1U << 9,
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QUP_MX_INPUT_DONE = 1U << 11,
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};
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/* I2C mini core related values */
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enum {
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I2C_MINI_CORE = 2U << 8,
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I2C_N_VAL = 0xF,
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};
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/* Packing Unpacking words in FIFOs , and IO modes*/
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enum {
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QUP_WR_BLK_MODE = 1U << 10,
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QUP_RD_BLK_MODE = 1U << 12,
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QUP_UNPACK_EN = 1U << 14,
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QUP_PACK_EN = 1U << 15,
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};
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/* QUP tags */
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enum {
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QUP_OUT_NOP = 0,
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QUP_OUT_START = 1U << 8,
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QUP_OUT_DATA = 2U << 8,
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QUP_OUT_STOP = 3U << 8,
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QUP_OUT_REC = 4U << 8,
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QUP_IN_DATA = 5U << 8,
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QUP_IN_STOP = 6U << 8,
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QUP_IN_NACK = 7U << 8,
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};
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/* Status, Error flags */
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enum {
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I2C_STATUS_WR_BUFFER_FULL = 1U << 0,
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I2C_STATUS_BUS_ACTIVE = 1U << 8,
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I2C_STATUS_ERROR_MASK = 0x38000FC,
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QUP_I2C_NACK_FLAG = 1U << 3,
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QUP_IN_NOT_EMPTY = 1U << 5,
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QUP_STATUS_ERROR_FLAGS = 0x7C,
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};
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void set_i2c_clk(struct qup_i2c_dev *dev)
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{
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uint32_t md = 0;
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uint32_t ns = 0;
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switch (dev->src_clk_freq) {
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case 24000000:
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ns = I2C_APPS_CLK_NS_24MHz;
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md = I2C_APPS_CLK_MD_24MHz;
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break;
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default:
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return;
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}
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/* Enable the GSBI8 HCLK */
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writel((GSBI8_HCLK_CTL_CLK_ENA << GSBI8_HCLK_CTL_S),
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GSBIn_HCLK_CTL(dev->gsbi_number));
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clock_config(ns,
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md,
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GSBIn_QUP_APPS_NS(dev->gsbi_number),
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GSBIn_QUP_APPS_MD(dev->gsbi_number));
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}
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void i2c_gpio_cfg(uint32_t base)
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{
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switch (base) {
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case GSBI8_BASE:
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gpio_tlmm_config(64, 1, GPIO_OUTPUT, GPIO_NO_PULL,
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GPIO_2MA, GPIO_DISABLE);
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gpio_tlmm_config(65, 1, GPIO_OUTPUT, GPIO_NO_PULL,
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GPIO_2MA, GPIO_DISABLE);
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break;
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default:
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break;
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}
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}
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#ifdef DEBUG
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static void qup_print_status(struct qup_i2c_dev *dev)
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{
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unsigned val;
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val = readl(dev->base + QUP_CONFIG);
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dprintf(INFO, "Qup config is :0x%x\n", val);
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val = readl(dev->base + QUP_STATE);
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dprintf(INFO, "Qup state is :0x%x\n", val);
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val = readl(dev->base + QUP_IO_MODE);
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dprintf(INFO, "Qup mode is :0x%x\n", val);
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}
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#else
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static inline void qup_print_status(struct qup_i2c_dev *dev)
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{
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}
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#endif
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void i2c_gpio_cfg(unsigned base);
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static irqreturn_t qup_i2c_interrupt(void)
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{
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struct qup_i2c_dev *dev = dev_addr;
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if (!dev) {
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dprintf(CRITICAL,
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"dev_addr is NULL, that means i2c_qup_init failed...\n");
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return IRQ_FAIL;
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}
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unsigned status = readl(dev->base + QUP_I2C_STATUS);
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unsigned status1 = readl(dev->base + QUP_ERROR_FLAGS);
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unsigned op_flgs = readl(dev->base + QUP_OPERATIONAL);
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int err = 0;
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if (!dev->msg)
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return IRQ_HANDLED;
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if (status & I2C_STATUS_ERROR_MASK) {
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dprintf(CRITICAL, "QUP: I2C status flags :0x%x \n", status);
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err = -status;
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/* Clear Error interrupt if it's a level triggered interrupt */
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if (dev->num_irqs == 1) {
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writel(QUP_RESET_STATE, dev->base + QUP_STATE);
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}
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goto intr_done;
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}
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if (status1 & 0x7F) {
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dprintf(CRITICAL, "QUP: QUP status flags :0x%x\n", status1);
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err = -status1;
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/* Clear Error interrupt if it's a level triggered interrupt */
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if (dev->num_irqs == 1)
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writel((status1 & QUP_STATUS_ERROR_FLAGS),
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dev->base + QUP_ERROR_FLAGS);
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goto intr_done;
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}
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if (op_flgs & QUP_OUT_SVC_FLAG)
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writel(QUP_OUT_SVC_FLAG, dev->base + QUP_OPERATIONAL);
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if (dev->msg->flags == I2C_M_RD) {
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if ((op_flgs & QUP_MX_INPUT_DONE) || (op_flgs & QUP_IN_SVC_FLAG))
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writel(QUP_IN_SVC_FLAG, dev->base + QUP_OPERATIONAL);
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else
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return IRQ_HANDLED;
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}
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intr_done:
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dev->err = err;
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return IRQ_HANDLED;
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}
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static int qup_i2c_poll_writeready(struct qup_i2c_dev *dev)
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{
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unsigned retries = 0;
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while (retries != 2000) {
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unsigned status = readl(dev->base + QUP_I2C_STATUS);
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if (!(status & I2C_STATUS_WR_BUFFER_FULL)) {
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if (!(status & I2C_STATUS_BUS_ACTIVE))
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return 0;
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else /* 1-bit delay before we check for bus busy */
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udelay(dev->one_bit_t);
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}
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if (retries++ == 1000)
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udelay(100);
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}
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qup_print_status(dev);
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return -ETIMEDOUT;
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}
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static int qup_i2c_poll_state(struct qup_i2c_dev *dev, unsigned state)
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{
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unsigned retries = 0;
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dprintf(CRITICAL, "Polling Status for state:0x%x\n", state);
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while (retries != 2000) {
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unsigned status = readl(dev->base + QUP_STATE);
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if ((status & (QUP_STATE_VALID | state)) == (QUP_STATE_VALID | state))
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return 0;
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else if (retries++ == 1000)
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udelay(100);
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}
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return -ETIMEDOUT;
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}
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#ifdef DEBUG
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static void qup_verify_fifo(struct qup_i2c_dev *dev, unsigned val,
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unsigned addr, int rdwr)
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{
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if (rdwr)
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dprintf(INFO, "RD:Wrote 0x%x to out_ff:0x%x\n", val, addr);
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else
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dprintf(INFO, "WR:Wrote 0x%x to out_ff:0x%x\n", val, addr);
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}
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#else
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static inline void qup_verify_fifo(struct qup_i2c_dev *dev, unsigned val,
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unsigned addr, int rdwr)
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{
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}
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#endif
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static void
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qup_issue_read(struct qup_i2c_dev *dev, struct i2c_msg *msg, int *idx,
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unsigned carry_over)
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{
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uint16_t addr = (msg->addr << 1) | 1;
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/* QUP limit 256 bytes per read. By HW design, 0 in the 8-bit field is
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treated as 256 byte read. */
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uint16_t rd_len = ((dev->cnt == 256) ? 0 : dev->cnt);
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if (*idx % 4) {
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writel(carry_over | ((QUP_OUT_START | addr) << 16),
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dev->base + QUP_OUT_FIFO_BASE);
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qup_verify_fifo(dev, carry_over |
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((QUP_OUT_START | addr) << 16), (unsigned)dev->base
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+ QUP_OUT_FIFO_BASE + (*idx - 2), 1);
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writel((QUP_OUT_REC | rd_len), dev->base + QUP_OUT_FIFO_BASE);
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qup_verify_fifo(dev, (QUP_OUT_REC | rd_len),
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(unsigned)dev->base + QUP_OUT_FIFO_BASE + (*idx + 2),
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1);
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} else {
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writel(((QUP_OUT_REC | rd_len) << 16) |
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QUP_OUT_START | addr, dev->base + QUP_OUT_FIFO_BASE);
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qup_verify_fifo(dev, QUP_OUT_REC << 16 | rd_len << 16 |
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QUP_OUT_START | addr,
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(unsigned)dev->base + QUP_OUT_FIFO_BASE + (*idx), 1);
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}
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*idx += 4;
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}
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static void
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qup_issue_write(struct qup_i2c_dev *dev, struct i2c_msg *msg, int rem,
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int *idx, unsigned *carry_over)
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{
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int entries = dev->cnt;
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int empty_sl = dev->wr_sz - ((*idx) >> 1);
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int i = 0;
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unsigned val = 0;
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unsigned last_entry = 0;
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uint16_t addr = msg->addr << 1;
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if (dev->pos == 0) {
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if (*idx % 4) {
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writel(*carry_over | ((QUP_OUT_START | addr) << 16),
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dev->base + QUP_OUT_FIFO_BASE);
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qup_verify_fifo(dev, *carry_over | QUP_OUT_DATA << 16 |
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addr << 16, (unsigned)dev->base +
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QUP_OUT_FIFO_BASE + (*idx) - 2, 0);
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} else
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val = QUP_OUT_START | addr;
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*idx += 2;
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i++;
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entries++;
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} else {
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/* Avoid setp time issue by adding 1 NOP when number of bytes are more
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than FIFO/BLOCK size. setup time issue can't appear otherwise since
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next byte to be written will always be ready */
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val = (QUP_OUT_NOP | 1);
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*idx += 2;
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i++;
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entries++;
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}
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if (entries > empty_sl)
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entries = empty_sl;
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for (; i < (entries - 1); i++) {
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if (*idx % 4) {
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writel(val | ((QUP_OUT_DATA |
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msg->buf[dev->pos]) << 16),
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dev->base + QUP_OUT_FIFO_BASE);
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qup_verify_fifo(dev, val | QUP_OUT_DATA << 16 |
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msg->buf[dev->pos] << 16, (unsigned)dev->base +
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QUP_OUT_FIFO_BASE + (*idx) - 2, 0);
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} else
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val = QUP_OUT_DATA | msg->buf[dev->pos];
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(*idx) += 2;
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dev->pos++;
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}
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if (dev->pos < (msg->len - 1))
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last_entry = QUP_OUT_DATA;
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else if (rem > 1) /* not last array entry */
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last_entry = QUP_OUT_DATA;
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else
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last_entry = QUP_OUT_STOP;
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if ((*idx % 4) == 0) {
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/*
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* If read-start and read-command end up in different fifos, it
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* may result in extra-byte being read due to extra-read cycle.
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* Avoid that by inserting NOP as the last entry of fifo only
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* if write command(s) leave 1 space in fifo.
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*/
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if (rem > 1) {
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struct i2c_msg *next = msg + 1;
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if (next->addr == msg->addr && (next->flags | I2C_M_RD)
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&& *idx == ((dev->wr_sz * 2) - 4)) {
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writel(((last_entry | msg->buf[dev->pos]) |
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((1 | QUP_OUT_NOP) << 16)),
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dev->base + QUP_OUT_FIFO_BASE);
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*idx += 2;
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} else
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*carry_over = (last_entry | msg->buf[dev->pos]);
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} else {
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writel((last_entry | msg->buf[dev->pos]),
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dev->base + QUP_OUT_FIFO_BASE);
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qup_verify_fifo(dev, last_entry | msg->buf[dev->pos],
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(unsigned)dev->base + QUP_OUT_FIFO_BASE +
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(*idx), 0);
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}
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} else {
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writel(val | ((last_entry | msg->buf[dev->pos]) << 16),
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dev->base + QUP_OUT_FIFO_BASE);
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qup_verify_fifo(dev, val | (last_entry << 16) |
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(msg->buf[dev->pos] << 16), (unsigned)dev->base +
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QUP_OUT_FIFO_BASE + (*idx) - 2, 0);
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}
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*idx += 2;
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dev->pos++;
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dev->cnt = msg->len - dev->pos;
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}
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static int qup_update_state(struct qup_i2c_dev *dev, unsigned state)
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{
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if (qup_i2c_poll_state(dev, 0) != 0)
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return -EIO;
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writel(state, dev->base + QUP_STATE);
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if (qup_i2c_poll_state(dev, state) != 0)
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return -EIO;
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return 0;
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}
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static int qup_set_read_mode(struct qup_i2c_dev *dev, int rd_len)
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{
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unsigned wr_mode = (dev->wr_sz < dev->out_fifo_sz) ? QUP_WR_BLK_MODE : 0;
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if (rd_len > 256) {
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dprintf(INFO, "HW doesn't support READs > 256 bytes\n");
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return -EPROTONOSUPPORT;
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}
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if (rd_len <= dev->in_fifo_sz) {
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writel(wr_mode | QUP_PACK_EN | QUP_UNPACK_EN, dev->base + QUP_IO_MODE);
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writel(rd_len, dev->base + QUP_MX_READ_CNT);
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} else {
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writel(wr_mode | QUP_RD_BLK_MODE |
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QUP_PACK_EN | QUP_UNPACK_EN, dev->base + QUP_IO_MODE);
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writel(rd_len, dev->base + QUP_MX_INPUT_CNT);
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}
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return 0;
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}
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static int qup_set_wr_mode(struct qup_i2c_dev *dev, int rem)
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{
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int total_len = 0;
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int ret = 0;
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if (dev->msg->len >= (dev->out_fifo_sz - 1)) {
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total_len = dev->msg->len + 1 + (dev->msg->len / (dev->out_blk_sz - 1));
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writel(QUP_WR_BLK_MODE | QUP_PACK_EN | QUP_UNPACK_EN,
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dev->base + QUP_IO_MODE);
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dev->wr_sz = dev->out_blk_sz;
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} else
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writel(QUP_PACK_EN | QUP_UNPACK_EN, dev->base + QUP_IO_MODE);
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if (rem > 1) {
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struct i2c_msg *next = dev->msg + 1;
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if (next->addr == dev->msg->addr && next->flags == I2C_M_RD) {
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ret = qup_set_read_mode(dev, next->len);
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/* make sure read start & read command are in 1 blk */
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if ((total_len % dev->out_blk_sz) == (dev->out_blk_sz - 1))
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total_len += 3;
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else
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total_len += 2;
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}
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}
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/* WRITE COUNT register valid/used only in block mode */
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if (dev->wr_sz == dev->out_blk_sz)
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writel(total_len, dev->base + QUP_MX_WR_CNT);
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return ret;
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}
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int qup_i2c_xfer(struct qup_i2c_dev *dev, struct i2c_msg msgs[], int num)
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{
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|
int ret;
|
|
int rem = num;
|
|
int err;
|
|
|
|
if (dev->suspended) {
|
|
return -EIO;
|
|
}
|
|
|
|
/* Set the GSBIn_QUP_APPS_CLK to 24MHz, then below figure out what speed to
|
|
run I2C_MASTER_CORE at. */
|
|
if (dev->clk_state == 0) {
|
|
if (dev->clk_ctl == 0) {
|
|
set_i2c_clk(dev);
|
|
}
|
|
}
|
|
/* Initialize QUP registers during first transfer */
|
|
if (dev->clk_ctl == 0) {
|
|
int fs_div;
|
|
int hs_div;
|
|
unsigned fifo_reg;
|
|
/* Configure the GSBI Protocol Code for i2c */
|
|
writel((GSBI_PROTOCOL_CODE_I2C <<
|
|
GSBI_CTRL_REG_PROTOCOL_CODE_S), dev->base);
|
|
|
|
fs_div = ((dev->src_clk_freq / dev->clk_freq) / 2) - 3;
|
|
hs_div = 3;
|
|
dev->clk_ctl = ((hs_div & 0x7) << 8) | (fs_div & 0xff);
|
|
fifo_reg = readl(dev->base + QUP_IO_MODE);
|
|
if (fifo_reg & 0x3)
|
|
dev->out_blk_sz = (fifo_reg & 0x3) * 16;
|
|
else
|
|
dev->out_blk_sz = 16;
|
|
if (fifo_reg & 0x60)
|
|
dev->in_blk_sz = ((fifo_reg & 0x60) >> 5) * 16;
|
|
else
|
|
dev->in_blk_sz = 16;
|
|
/*
|
|
* The block/fifo size w.r.t. 'actual data' is 1/2 due to 'tag'
|
|
* associated with each byte written/received
|
|
*/
|
|
dev->out_blk_sz /= 2;
|
|
dev->in_blk_sz /= 2;
|
|
dev->out_fifo_sz = dev->out_blk_sz * (2 << ((fifo_reg & 0x1C) >> 2));
|
|
dev->in_fifo_sz = dev->in_blk_sz * (2 << ((fifo_reg & 0x380) >> 7));
|
|
dprintf(CRITICAL, "QUP IN:bl:%d, ff:%d, OUT:bl:%d, ff:%d\n",
|
|
dev->in_blk_sz, dev->in_fifo_sz,
|
|
dev->out_blk_sz, dev->out_fifo_sz);
|
|
}
|
|
|
|
unmask_interrupt(dev->qup_irq);
|
|
writel(1, dev->base + QUP_SW_RESET);
|
|
ret = qup_i2c_poll_state(dev, QUP_RESET_STATE);
|
|
if (ret) {
|
|
dprintf(INFO, "QUP Busy:Trying to recover\n");
|
|
goto out_err;
|
|
}
|
|
|
|
/* Initialize QUP registers */
|
|
writel(0, dev->base + QUP_CONFIG);
|
|
writel(QUP_OPERATIONAL_RESET, dev->base + QUP_OPERATIONAL);
|
|
writel(QUP_STATUS_ERROR_FLAGS, dev->base + QUP_ERROR_FLAGS_EN);
|
|
|
|
writel(I2C_MINI_CORE | I2C_N_VAL, dev->base + QUP_CONFIG);
|
|
|
|
/* Initialize I2C mini core registers */
|
|
writel(0, dev->base + QUP_I2C_CLK_CTL);
|
|
writel(QUP_I2C_STATUS_RESET, dev->base + QUP_I2C_STATUS);
|
|
|
|
dev->cnt = msgs->len;
|
|
dev->pos = 0;
|
|
dev->msg = msgs;
|
|
while (rem) {
|
|
int filled = FALSE;
|
|
|
|
dev->wr_sz = dev->out_fifo_sz;
|
|
dev->err = 0;
|
|
|
|
if (qup_i2c_poll_state(dev, QUP_I2C_MAST_GEN) != 0) {
|
|
ret = -EIO;
|
|
goto out_err;
|
|
}
|
|
|
|
qup_print_status(dev);
|
|
/* HW limits Read upto 256 bytes in 1 read without stop */
|
|
if (dev->msg->flags & I2C_M_RD) {
|
|
ret = qup_set_read_mode(dev, dev->cnt);
|
|
if (ret != 0)
|
|
goto out_err;
|
|
} else {
|
|
ret = qup_set_wr_mode(dev, rem);
|
|
if (ret != 0)
|
|
goto out_err;
|
|
/* Don't fill block till we get interrupt */
|
|
if (dev->wr_sz == dev->out_blk_sz)
|
|
filled = TRUE;
|
|
}
|
|
|
|
err = qup_update_state(dev, QUP_RUN_STATE);
|
|
if (err < 0) {
|
|
ret = err;
|
|
goto out_err;
|
|
}
|
|
|
|
qup_print_status(dev);
|
|
writel(dev->clk_ctl, dev->base + QUP_I2C_CLK_CTL);
|
|
|
|
do {
|
|
int idx = 0;
|
|
unsigned carry_over = 0;
|
|
|
|
/* Transition to PAUSE state only possible from RUN */
|
|
err = qup_update_state(dev, QUP_PAUSE_STATE);
|
|
if (err < 0) {
|
|
ret = err;
|
|
goto out_err;
|
|
}
|
|
|
|
qup_print_status(dev);
|
|
/* This operation is Write, check the next operation and decide
|
|
mode */
|
|
while (filled == FALSE) {
|
|
if ((msgs->flags & I2C_M_RD) && (dev->cnt == msgs->len))
|
|
qup_issue_read(dev, msgs, &idx, carry_over);
|
|
else if (!(msgs->flags & I2C_M_RD))
|
|
qup_issue_write(dev, msgs, rem, &idx, &carry_over);
|
|
if (idx >= (dev->wr_sz << 1))
|
|
filled = TRUE;
|
|
/* Start new message */
|
|
if (filled == FALSE) {
|
|
if (msgs->flags & I2C_M_RD)
|
|
filled = TRUE;
|
|
else if (rem > 1) {
|
|
/* Only combine operations with same address */
|
|
struct i2c_msg *next = msgs + 1;
|
|
if (next->addr != msgs->addr || next->flags == 0)
|
|
filled = TRUE;
|
|
else {
|
|
rem--;
|
|
msgs++;
|
|
dev->msg = msgs;
|
|
dev->pos = 0;
|
|
dev->cnt = msgs->len;
|
|
}
|
|
} else
|
|
filled = TRUE;
|
|
}
|
|
}
|
|
err = qup_update_state(dev, QUP_RUN_STATE);
|
|
if (err < 0) {
|
|
ret = err;
|
|
goto out_err;
|
|
}
|
|
dprintf(CRITICAL, "idx:%d, rem:%d, num:%d, mode:%d\n",
|
|
idx, rem, num, dev->mode);
|
|
|
|
qup_print_status(dev);
|
|
if (dev->err) {
|
|
if (dev->err & QUP_I2C_NACK_FLAG) {
|
|
dprintf(CRITICAL,
|
|
"I2C slave addr:0x%x not connected\n",
|
|
dev->msg->addr);
|
|
} else {
|
|
dprintf(INFO, "QUP data xfer error %d\n", dev->err);
|
|
}
|
|
ret = dev->err;
|
|
goto out_err;
|
|
}
|
|
if (dev->msg->flags & I2C_M_RD) {
|
|
int i;
|
|
unsigned dval = 0;
|
|
for (i = 0; dev->pos < dev->msg->len; i++, dev->pos++) {
|
|
unsigned rd_status = readl(dev->base + QUP_OPERATIONAL);
|
|
if (i % 2 == 0) {
|
|
if ((rd_status & QUP_IN_NOT_EMPTY) == 0)
|
|
break;
|
|
dval = readl(dev->base + QUP_IN_FIFO_BASE);
|
|
dev->msg->buf[dev->pos] = dval & 0xFF;
|
|
} else
|
|
dev->msg->buf[dev->pos] = ((dval & 0xFF0000) >> 16);
|
|
}
|
|
dev->cnt -= i;
|
|
} else
|
|
filled = FALSE; /* refill output FIFO */
|
|
} while (dev->cnt > 0);
|
|
if (dev->cnt == 0) {
|
|
rem--;
|
|
msgs++;
|
|
if (rem) {
|
|
dev->pos = 0;
|
|
dev->cnt = msgs->len;
|
|
dev->msg = msgs;
|
|
}
|
|
}
|
|
/* Wait for I2C bus to be idle */
|
|
ret = qup_i2c_poll_writeready(dev);
|
|
if (ret) {
|
|
dprintf(INFO, "Error waiting for write ready\n");
|
|
goto out_err;
|
|
}
|
|
}
|
|
|
|
ret = num;
|
|
out_err:
|
|
dev->msg = NULL;
|
|
dev->pos = 0;
|
|
dev->err = 0;
|
|
dev->cnt = 0;
|
|
mask_interrupt(dev->qup_irq);
|
|
return ret;
|
|
}
|
|
|
|
static int set_gsbi_number(struct qup_i2c_dev *dev)
|
|
{
|
|
switch (dev->base) {
|
|
case GSBI1_QUP_BASE:
|
|
dev->gsbi_number = 1;
|
|
break;
|
|
case GSBI2_QUP_BASE:
|
|
dev->gsbi_number = 2;
|
|
break;
|
|
case GSBI3_QUP_BASE:
|
|
dev->gsbi_number = 3;
|
|
break;
|
|
case GSBI4_QUP_BASE:
|
|
dev->gsbi_number = 4;
|
|
break;
|
|
case GSBI5_QUP_BASE:
|
|
dev->gsbi_number = 5;
|
|
break;
|
|
case GSBI6_QUP_BASE:
|
|
dev->gsbi_number = 6;
|
|
break;
|
|
case GSBI7_QUP_BASE:
|
|
dev->gsbi_number = 7;
|
|
break;
|
|
case GSBI8_QUP_BASE:
|
|
dev->gsbi_number = 8;
|
|
break;
|
|
case GSBI9_QUP_BASE:
|
|
dev->gsbi_number = 9;
|
|
break;
|
|
case GSBI10_QUP_BASE:
|
|
dev->gsbi_number = 10;
|
|
break;
|
|
case GSBI11_QUP_BASE:
|
|
dev->gsbi_number = 11;
|
|
break;
|
|
case GSBI12_QUP_BASE:
|
|
dev->gsbi_number = 12;
|
|
break;
|
|
default:
|
|
return 1;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static int set_qup_irq(struct qup_i2c_dev *dev)
|
|
{
|
|
switch (dev->base) {
|
|
case GSBI1_QUP_BASE:
|
|
dev->qup_irq = GSBI1_QUP_IRQ;
|
|
break;
|
|
case GSBI2_QUP_BASE:
|
|
dev->qup_irq = GSBI2_QUP_IRQ;
|
|
break;
|
|
case GSBI3_QUP_BASE:
|
|
dev->qup_irq = GSBI3_QUP_IRQ;
|
|
break;
|
|
case GSBI4_QUP_BASE:
|
|
dev->qup_irq = GSBI4_QUP_IRQ;
|
|
break;
|
|
case GSBI5_QUP_BASE:
|
|
dev->qup_irq = GSBI5_QUP_IRQ;
|
|
break;
|
|
case GSBI6_QUP_BASE:
|
|
dev->qup_irq = GSBI6_QUP_IRQ;
|
|
break;
|
|
case GSBI7_QUP_BASE:
|
|
dev->qup_irq = GSBI7_QUP_IRQ;
|
|
break;
|
|
case GSBI8_QUP_BASE:
|
|
dev->qup_irq = GSBI8_QUP_IRQ;
|
|
break;
|
|
case GSBI9_QUP_BASE:
|
|
dev->qup_irq = GSBI9_QUP_IRQ;
|
|
break;
|
|
case GSBI10_QUP_BASE:
|
|
dev->qup_irq = GSBI10_QUP_IRQ;
|
|
break;
|
|
case GSBI11_QUP_BASE:
|
|
dev->qup_irq = GSBI11_QUP_IRQ;
|
|
break;
|
|
case GSBI12_QUP_BASE:
|
|
dev->qup_irq = GSBI12_QUP_IRQ;
|
|
break;
|
|
default:
|
|
return 1;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
struct qup_i2c_dev *qup_i2c_init(unsigned base,
|
|
unsigned clk_freq, unsigned src_clk_freq)
|
|
{
|
|
struct qup_i2c_dev *dev;
|
|
if (dev_addr != NULL) {
|
|
return dev_addr;
|
|
}
|
|
|
|
dev = malloc(sizeof(struct qup_i2c_dev));
|
|
if (!dev) {
|
|
return NULL;
|
|
}
|
|
dev = memset(dev, 0, sizeof(struct qup_i2c_dev));
|
|
|
|
/* This must be done for qup_i2c_interrupt to work. */
|
|
dev_addr = dev;
|
|
|
|
/* Initialize the GPIO for GSBIn as i2c */
|
|
i2c_gpio_cfg(base);
|
|
|
|
/* Configure GSBIn in i2c mode */
|
|
writel(GSBI_CTL_PROTOCOL_CODE_I2C, base);
|
|
|
|
/* Set the base address for GSBIn QUP The reason we add 0x80000 is to make
|
|
the GSBIn base address be the GSBIn QUP base address, which is what the
|
|
i2c driver wants. */
|
|
dev->base = base + 0x80000;
|
|
|
|
/* Set clk_freq and src_clk_freq for i2c. */
|
|
dev->clk_freq = clk_freq;
|
|
dev->src_clk_freq = src_clk_freq;
|
|
|
|
dev->num_irqs = 1;
|
|
|
|
dev->one_bit_t = USEC_PER_SEC / dev->clk_freq;
|
|
dev->clk_ctl = 0;
|
|
|
|
/* Set the IRQ number for GSBIn_BASE address */
|
|
if (set_qup_irq(dev)) {
|
|
dprintf(INFO,
|
|
"Could not find a valid QUP IRQ value based on GSBIn_BASE: %d\n",
|
|
base);
|
|
dprintf(INFO, "Please double check the GSBIn_BASE address.\n");
|
|
return NULL;
|
|
}
|
|
|
|
/* Set the GSBI number based on GSBIn_BASE address */
|
|
if (set_gsbi_number(dev)) {
|
|
dprintf(INFO, "Could not find a valid GSBI # based on GSBIn_BASE: %d\n",
|
|
base);
|
|
dprintf(INFO, "Please double check the GSBIn_BASE address.\n");
|
|
return NULL;
|
|
}
|
|
|
|
/* Register the GSBIn QUP IRQ */
|
|
register_int_handler(dev->qup_irq, qup_i2c_interrupt, 0);
|
|
|
|
/* Then disable it */
|
|
mask_interrupt(dev->qup_irq);
|
|
|
|
return dev;
|
|
}
|
|
|
|
int qup_i2c_deinit(struct qup_i2c_dev *dev)
|
|
{
|
|
/* Disable the qup_irq */
|
|
mask_interrupt(dev->qup_irq);
|
|
/* Free the memory used for dev */
|
|
free(dev);
|
|
return 0;
|
|
}
|