675 lines
28 KiB
C
675 lines
28 KiB
C
/*
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* Copyright (c) 2007, Google Inc.
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* All rights reserved.
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*
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* Copyright (c) 2009-2010, Code Aurora Forum. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Code Aurora nor
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* the names of its contributors may be used to endorse or promote
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* products derived from this software without specific prior written
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* permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <debug.h>
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#include <dev/gpio.h>
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#include <kernel/thread.h>
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#include "gpio_hw.h"
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#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
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static int display_common_power(int);
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#if DISPLAY_TYPE_MDDI
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#include <mddi.h>
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#define MDDI_CLIENT_CORE_BASE 0x108000
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#define LCD_CONTROL_BLOCK_BASE 0x110000
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#define SPI_BLOCK_BASE 0x120000
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#define I2C_BLOCK_BASE 0x130000
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#define PWM_BLOCK_BASE 0x140000
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#define GPIO_BLOCK_BASE 0x150000
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#define SYSTEM_BLOCK1_BASE 0x160000
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#define SYSTEM_BLOCK2_BASE 0x170000
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#define MDDICAP0 (MDDI_CLIENT_CORE_BASE|0x00)
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#define MDDICAP1 (MDDI_CLIENT_CORE_BASE|0x04)
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#define MDDICAP2 (MDDI_CLIENT_CORE_BASE|0x08)
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#define MDDICAP3 (MDDI_CLIENT_CORE_BASE|0x0C)
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#define MDCAPCHG (MDDI_CLIENT_CORE_BASE|0x10)
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#define MDCRCERC (MDDI_CLIENT_CORE_BASE|0x14)
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#define TTBUSSEL (MDDI_CLIENT_CORE_BASE|0x18)
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#define DPSET0 (MDDI_CLIENT_CORE_BASE|0x1C)
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#define DPSET1 (MDDI_CLIENT_CORE_BASE|0x20)
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#define DPSUS (MDDI_CLIENT_CORE_BASE|0x24)
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#define DPRUN (MDDI_CLIENT_CORE_BASE|0x28)
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#define SYSCKENA (MDDI_CLIENT_CORE_BASE|0x2C)
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#define TESTMODE (MDDI_CLIENT_CORE_BASE|0x30)
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#define FIFOMONI (MDDI_CLIENT_CORE_BASE|0x34)
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#define INTMONI (MDDI_CLIENT_CORE_BASE|0x38)
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#define MDIOBIST (MDDI_CLIENT_CORE_BASE|0x3C)
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#define MDIOPSET (MDDI_CLIENT_CORE_BASE|0x40)
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#define BITMAP0 (MDDI_CLIENT_CORE_BASE|0x44)
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#define BITMAP1 (MDDI_CLIENT_CORE_BASE|0x48)
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#define BITMAP2 (MDDI_CLIENT_CORE_BASE|0x4C)
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#define BITMAP3 (MDDI_CLIENT_CORE_BASE|0x50)
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#define BITMAP4 (MDDI_CLIENT_CORE_BASE|0x54)
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#define SRST (LCD_CONTROL_BLOCK_BASE|0x00)
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#define PORT_ENB (LCD_CONTROL_BLOCK_BASE|0x04)
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#define START (LCD_CONTROL_BLOCK_BASE|0x08)
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#define PORT (LCD_CONTROL_BLOCK_BASE|0x0C)
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#define CMN (LCD_CONTROL_BLOCK_BASE|0x10)
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#define GAMMA (LCD_CONTROL_BLOCK_BASE|0x14)
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#define INTFLG (LCD_CONTROL_BLOCK_BASE|0x18)
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#define INTMSK (LCD_CONTROL_BLOCK_BASE|0x1C)
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#define MPLFBUF (LCD_CONTROL_BLOCK_BASE|0x20)
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#define HDE_LEFT (LCD_CONTROL_BLOCK_BASE|0x24)
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#define VDE_TOP (LCD_CONTROL_BLOCK_BASE|0x28)
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#define PXL (LCD_CONTROL_BLOCK_BASE|0x30)
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#define HCYCLE (LCD_CONTROL_BLOCK_BASE|0x34)
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#define HSW (LCD_CONTROL_BLOCK_BASE|0x38)
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#define HDE_START (LCD_CONTROL_BLOCK_BASE|0x3C)
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#define HDE_SIZE (LCD_CONTROL_BLOCK_BASE|0x40)
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#define VCYCLE (LCD_CONTROL_BLOCK_BASE|0x44)
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#define VSW (LCD_CONTROL_BLOCK_BASE|0x48)
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#define VDE_START (LCD_CONTROL_BLOCK_BASE|0x4C)
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#define VDE_SIZE (LCD_CONTROL_BLOCK_BASE|0x50)
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#define WAKEUP (LCD_CONTROL_BLOCK_BASE|0x54)
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#define WSYN_DLY (LCD_CONTROL_BLOCK_BASE|0x58)
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#define REGENB (LCD_CONTROL_BLOCK_BASE|0x5C)
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#define VSYNIF (LCD_CONTROL_BLOCK_BASE|0x60)
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#define WRSTB (LCD_CONTROL_BLOCK_BASE|0x64)
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#define RDSTB (LCD_CONTROL_BLOCK_BASE|0x68)
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#define ASY_DATA (LCD_CONTROL_BLOCK_BASE|0x6C)
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#define ASY_DATB (LCD_CONTROL_BLOCK_BASE|0x70)
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#define ASY_DATC (LCD_CONTROL_BLOCK_BASE|0x74)
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#define ASY_DATD (LCD_CONTROL_BLOCK_BASE|0x78)
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#define ASY_DATE (LCD_CONTROL_BLOCK_BASE|0x7C)
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#define ASY_DATF (LCD_CONTROL_BLOCK_BASE|0x80)
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#define ASY_DATG (LCD_CONTROL_BLOCK_BASE|0x84)
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#define ASY_DATH (LCD_CONTROL_BLOCK_BASE|0x88)
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#define ASY_CMDSET (LCD_CONTROL_BLOCK_BASE|0x8C)
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#define MONI (LCD_CONTROL_BLOCK_BASE|0xB0)
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#define Current (LCD_CONTROL_BLOCK_BASE|0xC0)
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#define LCD (LCD_CONTROL_BLOCK_BASE|0xC4)
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#define COMMAND (LCD_CONTROL_BLOCK_BASE|0xC8)
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#define SSICTL (SPI_BLOCK_BASE|0x00)
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#define SSITIME (SPI_BLOCK_BASE|0x04)
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#define SSITX (SPI_BLOCK_BASE|0x08)
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#define SSIRX (SPI_BLOCK_BASE|0x0C)
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#define SSIINTC (SPI_BLOCK_BASE|0x10)
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#define SSIINTS (SPI_BLOCK_BASE|0x14)
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#define SSIDBG1 (SPI_BLOCK_BASE|0x18)
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#define SSIDBG2 (SPI_BLOCK_BASE|0x1C)
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#define SSIID (SPI_BLOCK_BASE|0x20)
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#define I2CSETUP (I2C_BLOCK_BASE|0x00)
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#define I2CCTRL (I2C_BLOCK_BASE|0x04)
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#define TIMER0LOAD (PWM_BLOCK_BASE|0x00)
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#define TIMER0VALUE (PWM_BLOCK_BASE|0x04)
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#define TIMER0CONTROL (PWM_BLOCK_BASE|0x08)
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#define TIMER0INTCLR (PWM_BLOCK_BASE|0x0C)
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#define TIMER0RIS (PWM_BLOCK_BASE|0x10)
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#define TIMER0MIS (PWM_BLOCK_BASE|0x14)
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#define TIMER0BGLOAD (PWM_BLOCK_BASE|0x18)
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#define PWM0OFF (PWM_BLOCK_BASE|0x1C)
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#define TIMER1LOAD (PWM_BLOCK_BASE|0x20)
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#define TIMER1VALUE (PWM_BLOCK_BASE|0x24)
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#define TIMER1CONTROL (PWM_BLOCK_BASE|0x28)
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#define TIMER1INTCLR (PWM_BLOCK_BASE|0x2C)
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#define TIMER1RIS (PWM_BLOCK_BASE|0x30)
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#define TIMER1MIS (PWM_BLOCK_BASE|0x34)
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#define TIMER1BGLOAD (PWM_BLOCK_BASE|0x38)
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#define PWM1OFF (PWM_BLOCK_BASE|0x3C)
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#define TIMERITCR (PWM_BLOCK_BASE|0x60)
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#define TIMERITOP (PWM_BLOCK_BASE|0x64)
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#define PWMCR (PWM_BLOCK_BASE|0x68)
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#define PWMID (PWM_BLOCK_BASE|0x6C)
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#define PWMMON (PWM_BLOCK_BASE|0x70)
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#define GPIODATA (GPIO_BLOCK_BASE|0x00)
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#define GPIODIR (GPIO_BLOCK_BASE|0x04)
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#define GPIOIS (GPIO_BLOCK_BASE|0x08)
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#define GPIOIBE (GPIO_BLOCK_BASE|0x0C)
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#define GPIOIEV (GPIO_BLOCK_BASE|0x10)
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#define GPIOIE (GPIO_BLOCK_BASE|0x14)
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#define GPIORIS (GPIO_BLOCK_BASE|0x18)
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#define GPIOMIS (GPIO_BLOCK_BASE|0x1C)
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#define GPIOIC (GPIO_BLOCK_BASE|0x20)
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#define GPIOOMS (GPIO_BLOCK_BASE|0x24)
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#define GPIOPC (GPIO_BLOCK_BASE|0x28)
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#define GPIOID (GPIO_BLOCK_BASE|0x30)
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#define WKREQ (SYSTEM_BLOCK1_BASE|0x00)
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#define CLKENB (SYSTEM_BLOCK1_BASE|0x04)
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#define DRAMPWR (SYSTEM_BLOCK1_BASE|0x08)
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#define INTMASK (SYSTEM_BLOCK1_BASE|0x0C)
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#define CNT_DIS (SYSTEM_BLOCK1_BASE|0x10)
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#define GPIOSEL (SYSTEM_BLOCK2_BASE|0x00)
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struct init_table {
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unsigned int reg;
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unsigned int val;
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};
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static struct init_table toshiba_480x800_init_table[] = {
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{ DPSET0, 0x4BEC0066 }, // # MDC.DPSET0 # Setup DPLL parameters
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{ DPSET1, 0x00000113 }, // # MDC.DPSET1
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{ DPSUS, 0x00000000 }, // # MDC.DPSUS # Set DPLL oscillation enable
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{ DPRUN, 0x00000001 }, // # MDC.DPRUN # Release reset signal for DPLL
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{ 0, 15 }, // wait_ms(15);
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{ SYSCKENA, 0x00000001 }, // # MDC.SYSCKENA # Enable system clock output
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{ CLKENB, 0x000000E9 }, // # SYS.CLKENB # Enable clocks for each module (without DCLK , i2cCLK)
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{ GPIO_BLOCK_BASE, 0x03FF0000 }, // # GPI .GPIODATA # GPIO2(RESET_LCD_N) set to 0 , GPIO3(eDRAM_Power) set to 0
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{ GPIODIR, 0x0000024D }, // # GPI .GPIODIR # Select direction of GPIO port (0,2,3,6,9 output)
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{ SYSTEM_BLOCK2_BASE, 0x00000173 }, // # SYS.GPIOSEL # GPIO port multiplexing control
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{ GPIOPC, 0x03C300C0 }, // # GPI .GPIOPC # GPIO2,3 PD cut
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{ SYSTEM_BLOCK1_BASE, 0x00000000 }, // # SYS.WKREQ # Wake-up request event is VSYNC alignment
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{ GPIOIS, 0x00000000 }, // # GPI .GPIOIS # Set interrupt sense of GPIO
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{ GPIOIEV, 0x00000001 }, // # GPI .GPIOIEV # Set interrupt event of GPIO
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{ GPIOIC, 0x000003FF }, // # GPI .GPIOIC # GPIO interrupt clear
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{ GPIO_BLOCK_BASE, 0x00040004 }, // # GPI .GPIODATA # Release LCDD reset
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{ GPIO_BLOCK_BASE, 0x00080008 }, // # GPI .GPIODATA # eDRAM VD supply
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{ DRAMPWR, 0x00000001 }, // # SYS.DRAMPWR # eDRAM power up
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{ CLKENB, 0x000000EB }, // # enable eDRAM clock
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{ PWMCR, 0x00000000 }, // # PWM.PWMCR # PWM output enable
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{ 0, 1 }, // wait_ms(1);
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{ SPI_BLOCK_BASE, 0x00060399}, // # SPI .SSICTL # SPI operation mode setting
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{ SSITIME, 0x00000100 }, // # SPI .SSITIME # SPI serial interface timing setting
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{ CNT_DIS, 0x00000002 }, // # SPI .SSITIME # SPI serial interface timing setting
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{ SPI_BLOCK_BASE, 0x0006039B }, // # SPI .SSICTL # Set SPI active mode
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{ SSITX, 0x00000000 }, // # SPI.SSITX # Release from Deep Stanby mode
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{ 0, 7 }, // wait_ms(2);
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{ SSITX, 0x00000000 }, // # SPI.SSITX
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{ 0, 7 }, // wait_ms(2);
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{ SSITX, 0x00000000 }, // # SPI.SSITX
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{ 0, 7 }, // wait_ms(2);
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{ SSITX, 0x000800BA }, // # SPI.SSITX *NOTE 1 # Command setting of SPI block
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{ SSITX, 0x00000111 }, // # Display mode setup(1) : Normaly Black
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{ SSITX, 0x00080036 }, // # Command setting of SPI block
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{ SSITX, 0x00000100 }, // # Memory access control
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{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
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{ SSITX, 0x0008003A }, // # Command setting of SPI block
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{ SSITX, 0x00000160 }, // # Display mode setup(2)
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{ SSITX, 0x000800B1 }, // # Command setting of SPI block
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{ SSITX, 0x0000015D }, // # RGB Interface data format
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{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
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{ SSITX, 0x000800B2 }, // # Command setting of SPI block
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{ SSITX, 0x00000133 }, // # Drivnig method
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{ SSITX, 0x000800B3 }, // # Command setting of SPI block
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{ SSITX, 0x00000122 }, // # Booster operation setup
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{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
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{ SSITX, 0x000800B4 }, // # Command setting of SPI block
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{ SSITX, 0x00000102 }, // # OP-amp capability/System clock freq. division setup
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{ SSITX, 0x000800B5 }, // # Command setting of SPI block
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{ SSITX, 0x0000011E }, // # VCS Voltage adjustment (1C->1F for Rev 2)
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{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
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{ SSITX, 0x000800B6 }, // # Command setting of SPI block
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{ SSITX, 0x00000127 }, // # VCOM Voltage adjustment
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{ SSITX, 0x000800B7 }, // # Command setting of SPI block
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{ SSITX, 0x00000103 }, // # Configure an external display signal
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{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
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{ SSITX, 0x000800B9 }, // # Command setting of SPI block
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{ SSITX, 0x00000124 }, // # DCCK/DCEV timing setup
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{ SSITX, 0x000800BD }, // # Command setting of SPI block
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{ SSITX, 0x000001A1 }, // # ASW signal control
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{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
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{ SSITX, 0x000800BB }, // # Command setting of SPI block
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{ SSITX, 0x00000100 }, // # Dummy display (white/black) count setup for QUAD Data operation
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{ SSITX, 0x000800BF }, // # Command setting of SPI block
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{ SSITX, 0x00000101 }, // # Dummy display (white/black) count setup for QUAD Data operation
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{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
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{ SSITX, 0x000800BE }, // # Command setting of SPI block
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{ SSITX, 0x00000100 }, // # wait_ms(-out FR count setup (A)
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{ SSITX, 0x000800C0 }, // # Command setting of SPI block
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{ SSITX, 0x00000111 }, // # wait_ms(-out FR count setup (A)
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{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
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{ SSITX, 0x000800C1 }, // # Command setting of SPI block
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{ SSITX, 0x00000111 }, // # wait_ms(-out FR count setup (B)
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{ SSITX, 0x000800C2 }, // # Command setting of SPI block
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{ SSITX, 0x00000111 }, // # wait_ms(-out FR count setup (C)
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{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
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{ SSITX, 0x000800C3 }, // # Command setting of SPI block
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{ SSITX, 0x00080132 }, // # wait_ms(-in line clock count setup (D)
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{ SSITX, 0x00000132 }, //
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{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
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{ SSITX, 0x000800C4 }, // # Command setting of SPI block
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{ SSITX, 0x00080132 }, // # Seep-in line clock count setup (E)
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{ SSITX, 0x00000132 }, //
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{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
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{ SSITX, 0x000800C5 }, // # Command setting of SPI block
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{ SSITX, 0x00080132 }, // # wait_ms(-in line clock count setup (F)
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{ SSITX, 0x00000132 }, //
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{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
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{ SSITX, 0x000800C6 }, // # Command setting of SPI block
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{ SSITX, 0x00080132 }, // # wait_ms(-in line clock setup (G)
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{ SSITX, 0x00000132 }, //
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{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
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{ SSITX, 0x000800C7 }, // # Command setting of SPI block
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{ SSITX, 0x00080164 }, // # Gamma 1 fine tuning (1)
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{ SSITX, 0x00000145 }, //
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{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
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{ SSITX, 0x000800C8 }, // # Command setting of SPI block
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{ SSITX, 0x00000144 }, // # Gamma 1 fine tuning (2)
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{ SSITX, 0x000800C9 }, // # Command setting of SPI block
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{ SSITX, 0x00000152 }, // # Gamma 1 inclination adjustment
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{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
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{ SSITX, 0x000800CA }, // # Command setting of SPI block
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{ SSITX, 0x00000100 }, // # Gamma 1 blue offset adjustment
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{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
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{ SSITX, 0x000800EC }, // # Command setting of SPI block
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{ SSITX, 0x00080102 }, // # Total number of horizontal clock cycles (1) [PCLK Sync. VGA setting]
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{ SSITX, 0x00000118 }, //
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{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
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{ SSITX, 0x000800CF }, // # Command setting of SPI block
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{ SSITX, 0x00000101 }, // # Blanking period control (1) [PCLK Sync. Table1 for VGA]
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{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
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{ SSITX, 0x000800D0 }, // # Command setting of SPI block
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{ SSITX, 0x00080110 }, // # Blanking period control (2) [PCLK Sync. Table1 for VGA]
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{ SSITX, 0x00000104 }, //
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{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
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{ SSITX, 0x000800D1 }, // # Command setting of SPI block
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{ SSITX, 0x00000101 }, // # CKV timing control on/off [PCLK Sync. Table1 for VGA]
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{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
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{ SSITX, 0x000800D2 }, // # Command setting of SPI block
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{ SSITX, 0x00080100 }, // # CKV1,2 timing control [PCLK Sync. Table1 for VGA]
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{ SSITX, 0x00000128 }, //
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{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
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{ SSITX, 0x000800D3 }, // # Command setting of SPI block
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{ SSITX, 0x00080100 }, // # OEV timing control [PCLK Sync. Table1 for VGA]
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{ SSITX, 0x00000128 }, //
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{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
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{ SSITX, 0x000800D4 }, // # Command setting of SPI block
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{ SSITX, 0x00080126 }, // # ASW timing control (1) [PCLK Sync. Table1 for VGA]
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{ SSITX, 0x000001A4 }, //
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{ 0, 1 }, // wait_ms(1); // # Wait SPI fifo empty
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{ SSITX, 0x000800D5 }, // # Command setting of SPI block
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{ SSITX, 0x00000120 }, // # ASW timing control (2) [PCLK Sync. Table1 for VGA]
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{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
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{ SSITX, 0x000800EF }, // # Command setting of SPI block
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{ SSITX, 0x00080132 }, // # Total number of horizontal clock cycles (2) [PCLK Sync. Table1 for QVGA ]
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{ SSITX, 0x00000100 }, //
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{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
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{ BITMAP0, 0x032001E0 }, // MDC.BITMAP0 ); // Setup of PITCH size to Frame buffer1
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{ BITMAP1, 0x032001E0 }, // MDC.BITMAP1 ); // Setup of PITCH size to Frame buffer1
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{ BITMAP2, 0x014000F0 }, // MDC.BITMAP3 ); // Setup of PITCH size to Frame buffer2
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|
{ BITMAP3, 0x014000F0 }, // MDC.BITMAP4 ); // Setup of PITCH size to Frame buffer3
|
|
{ BITMAP4, 0x014000F0 }, // MDC.BITMAP5 ); // Setup of PITCH size to Frame buffer4
|
|
{ CLKENB, 0x000001EB }, // SYS.CLKENB ); // DCLK supply
|
|
{ PORT_ENB, 0x00000001 }, // LCD.PORT_ENB ); // Synchronous port enable
|
|
{ PORT, 0x00000004 }, // LCD.PORT ); // Polarity of DE is set to high active
|
|
{ PXL, 0x00000002 }, // LCD.PXL ); // ACTMODE 2 set (1st frame black data output)
|
|
{ MPLFBUF, 0x00000000 }, // LCD.MPLFBUF ); // Select the reading buffer
|
|
{ HCYCLE, 0x0000010B }, // LCD.HCYCLE ); // Setup to VGA size
|
|
{ HSW, 0x00000003 }, // LCD.HSW
|
|
{ HDE_START, 0x00000007 }, // LCD.HDE_START
|
|
{ HDE_SIZE, 0x000000EF }, // LCD.HDE_SIZE
|
|
{ VCYCLE, 0x00000325 }, // LCD.VCYCLE
|
|
{ VSW, 0x00000001 }, // LCD.VSW
|
|
{ VDE_START, 0x00000003 }, // LCD.VDE_START
|
|
{ VDE_SIZE, 0x0000031F }, // LCD.VDE_SIZE
|
|
|
|
{ START, 0x00000001 }, // LCD.START ); // LCDC - Pixel data transfer start
|
|
|
|
{ 0, 10 }, // wait_ms( 10 );
|
|
{ SSITX, 0x000800BC }, // SPI.SSITX ); // Command setting of SPI block
|
|
{ SSITX, 0x00000180 }, // Display data setup
|
|
{ SSITX, 0x0008003B }, // Command setting of SPI block
|
|
{ SSITX, 0x00000100 }, // Quad Data configuration - VGA
|
|
{ 0, 1 }, // wait_ms( 1 ); // Wait SPI fifo empty
|
|
{ SSITX, 0x000800B0 }, // Command setting of SPI block
|
|
{ SSITX, 0x00000116 }, // Power supply ON/OFF control
|
|
{ 0, 1 }, // wait_ms( 1 ); // Wait SPI fifo empty
|
|
{ SSITX, 0x000800B8 }, // Command setting of SPI block
|
|
{ SSITX, 0x000801FF }, // Output control
|
|
{ SSITX, 0x000001F5 },
|
|
{ 0, 1 }, // wait_ms( 1); // Wait SPI fifo empty
|
|
{ SSITX, 0x00000011 }, // wait_ms(-out (Command only)
|
|
{ 0, 5 }, // wait_ms( 1); // Wait SPI fifo empty
|
|
{ SSITX, 0x00000029 }, // Display on (Command only)
|
|
|
|
//{ SYSTEM_BLOCK1_BASE, 0x00000002 }, // # wakeREQ -> GPIO
|
|
|
|
{ 0, 0 }
|
|
};
|
|
|
|
void mddi_panel_poweron(void)
|
|
{
|
|
display_common_power(1);
|
|
}
|
|
|
|
static void _panel_init(struct init_table *init_table)
|
|
{
|
|
unsigned n;
|
|
|
|
dprintf(INFO, "panel_init()\n");
|
|
|
|
n = 0;
|
|
while (init_table[n].reg != 0 || init_table[n].val != 0) {
|
|
if (init_table[n].reg != 0)
|
|
mddi_remote_write(init_table[n].val, init_table[n].reg);
|
|
else
|
|
mdelay(init_table[n].val);
|
|
n++;
|
|
}
|
|
|
|
dprintf(INFO, "panel_init() done\n");
|
|
}
|
|
|
|
void panel_init(struct mddi_client_caps *client_caps)
|
|
{
|
|
switch(client_caps->manufacturer_name) {
|
|
case 0xd263: // Toshiba
|
|
dprintf(INFO, "Found Toshiba panel\n");
|
|
_panel_init(toshiba_480x800_init_table);
|
|
break;
|
|
case 0x4474: //??
|
|
if (client_caps->product_code == 0xc065)
|
|
dprintf(INFO, "Found WVGA panel\n");
|
|
break;
|
|
}
|
|
}
|
|
#endif //mddi
|
|
|
|
void panel_poweron(void)
|
|
{
|
|
#if DISPLAY_TYPE_LCDC
|
|
panel_backlight(1);
|
|
lcdc_on();
|
|
#endif
|
|
}
|
|
|
|
void panel_backlight(int on)
|
|
{
|
|
unsigned char reg_data = 0xA0;
|
|
if(on)
|
|
pmic_write(0x132, reg_data);
|
|
else
|
|
pmic_write(0x132, 0);
|
|
}
|
|
|
|
static unsigned wega_reset_gpio =
|
|
GPIO_CFG(180, 0, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_2MA);
|
|
|
|
#define LDO12_CNTRL 0x015
|
|
#define LDO15_CNTRL 0x089
|
|
#define LDO16_CNTRL 0x08A
|
|
#define LDO20_CNTRL 0x11F // PM8058 only
|
|
#define LDO_LOCAL_EN_BMSK 0x80
|
|
|
|
static int display_common_power(int on)
|
|
{
|
|
int rc = 0, flag_on = !!on;
|
|
static int display_common_power_save_on;
|
|
unsigned int vreg_ldo12, vreg_ldo15, vreg_ldo20, vreg_ldo16, vreg_ldo8;
|
|
if (display_common_power_save_on == flag_on)
|
|
return 0;
|
|
|
|
display_common_power_save_on = flag_on;
|
|
|
|
if (on) {
|
|
/* reset Toshiba WeGA chip -- toggle reset pin -- gpio_180 */
|
|
rc = gpio_tlmm_config(wega_reset_gpio, GPIO_ENABLE);
|
|
if (rc) {
|
|
return rc;
|
|
}
|
|
|
|
gpio_set(180, 0); /* bring reset line low to hold reset*/
|
|
}
|
|
|
|
// Set power for WEGA chip.
|
|
// Set LD020 to 1.5V
|
|
pmic_write(LDO20_CNTRL, 0x00 | LDO_LOCAL_EN_BMSK);
|
|
mdelay(5);
|
|
|
|
// Set LD012 to 1.8V
|
|
pmic_write(LDO12_CNTRL, 0x06 | LDO_LOCAL_EN_BMSK);
|
|
mdelay(5);
|
|
|
|
// Set LD016 to 2.6V
|
|
pmic_write(LDO16_CNTRL, 0x16 | LDO_LOCAL_EN_BMSK);
|
|
mdelay(5);
|
|
|
|
// Set LD015 to 3.0V
|
|
pmic_write(LDO15_CNTRL, 0x1E | LDO_LOCAL_EN_BMSK);
|
|
mdelay(5);
|
|
|
|
gpio_set(180, 1); /* bring reset line high */
|
|
mdelay(10); /* 10 msec before IO can be accessed */
|
|
if (rc) {
|
|
return rc;
|
|
}
|
|
|
|
return rc;
|
|
}
|
|
|
|
#if DISPLAY_TYPE_LCDC
|
|
static struct msm_gpio lcd_panel_gpios[] = {
|
|
{ GPIO_CFG(45, 0, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_2MA), "spi_clk" },
|
|
{ GPIO_CFG(46, 0, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_2MA), "spi_cs0" },
|
|
{ GPIO_CFG(47, 0, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_2MA), "spi_mosi" },
|
|
{ GPIO_CFG(48, 0, GPIO_INPUT, GPIO_NO_PULL, GPIO_2MA), "spi_miso" }
|
|
};
|
|
|
|
int lcdc_toshiba_panel_power(int on)
|
|
{
|
|
int rc, i;
|
|
struct msm_gpio *gp;
|
|
|
|
rc = display_common_power(on);
|
|
if (rc < 0) {
|
|
return rc;
|
|
}
|
|
|
|
if (on) {
|
|
rc = platform_gpios_enable(lcd_panel_gpios,
|
|
ARRAY_SIZE(lcd_panel_gpios));
|
|
if(rc)
|
|
{
|
|
return rc;
|
|
}
|
|
} else { /* off */
|
|
gp = lcd_panel_gpios;
|
|
for (i = 0; i < ARRAY_SIZE(lcd_panel_gpios); i++) {
|
|
/* ouput low */
|
|
gpio_set(GPIO_PIN(gp->gpio_cfg), 0);
|
|
gp++;
|
|
}
|
|
}
|
|
|
|
return rc;
|
|
}
|
|
|
|
#define SPI_SCLK 45
|
|
#define SPI_CS 46
|
|
#define SPI_MOSI 47
|
|
#define SPI_MISO 48
|
|
|
|
static void toshiba_spi_write_byte(char dc, unsigned char data)
|
|
{
|
|
unsigned bit;
|
|
int bnum;
|
|
|
|
gpio_set(SPI_SCLK, 0); /* clk low */
|
|
/* dc: 0 for command, 1 for parameter */
|
|
gpio_set(SPI_MOSI, dc);
|
|
mdelay(1); /* at least 20 ns */
|
|
gpio_set(SPI_SCLK, 1); /* clk high */
|
|
mdelay(1); /* at least 20 ns */
|
|
bnum = 8; /* 8 data bits */
|
|
bit = 0x80;
|
|
while (bnum) {
|
|
gpio_set(SPI_SCLK, 0); /* clk low */
|
|
if (data & bit)
|
|
gpio_set(SPI_MOSI, 1);
|
|
else
|
|
gpio_set(SPI_MOSI, 0);
|
|
mdelay(1);
|
|
gpio_set(SPI_SCLK, 1); /* clk high */
|
|
mdelay(1);
|
|
bit >>= 1;
|
|
bnum--;
|
|
}
|
|
}
|
|
|
|
static int toshiba_spi_write (char cmd, unsigned data, int num)
|
|
{
|
|
char *bp;
|
|
gpio_set(SPI_CS, 1); /* cs high */
|
|
|
|
/* command byte first */
|
|
toshiba_spi_write_byte(0, cmd);
|
|
|
|
/* followed by parameter bytes */
|
|
if (num) {
|
|
bp = (char *)&data;;
|
|
bp += (num - 1);
|
|
while (num) {
|
|
toshiba_spi_write_byte(1, *bp);
|
|
num--;
|
|
bp--;
|
|
}
|
|
}
|
|
gpio_set(SPI_CS, 0); /* cs low */
|
|
mdelay(1);
|
|
return 0;
|
|
}
|
|
|
|
|
|
void lcdc_disp_on (void)
|
|
{
|
|
gpio_set(SPI_CS, 0); /* low */
|
|
gpio_set(SPI_SCLK, 1); /* high */
|
|
gpio_set(SPI_MOSI, 0);
|
|
gpio_set(SPI_MISO, 0);
|
|
|
|
if (1) {
|
|
toshiba_spi_write(0, 0, 0);
|
|
mdelay(7);
|
|
toshiba_spi_write(0, 0, 0);
|
|
mdelay(7);
|
|
toshiba_spi_write(0, 0, 0);
|
|
mdelay(7);
|
|
toshiba_spi_write(0xba, 0x11, 1);
|
|
toshiba_spi_write(0x36, 0x00, 1);
|
|
mdelay(1);
|
|
toshiba_spi_write(0x3a, 0x60, 1);
|
|
toshiba_spi_write(0xb1, 0x5d, 1);
|
|
mdelay(1);
|
|
toshiba_spi_write(0xb2, 0x33, 1);
|
|
toshiba_spi_write(0xb3, 0x22, 1);
|
|
mdelay(1);
|
|
toshiba_spi_write(0xb4, 0x02, 1);
|
|
toshiba_spi_write(0xb5, 0x1e, 1); /* vcs -- adjust brightness */
|
|
mdelay(1);
|
|
toshiba_spi_write(0xb6, 0x27, 1);
|
|
toshiba_spi_write(0xb7, 0x03, 1);
|
|
mdelay(1);
|
|
toshiba_spi_write(0xb9, 0x24, 1);
|
|
toshiba_spi_write(0xbd, 0xa1, 1);
|
|
mdelay(1);
|
|
toshiba_spi_write(0xbb, 0x00, 1);
|
|
toshiba_spi_write(0xbf, 0x01, 1);
|
|
mdelay(1);
|
|
toshiba_spi_write(0xbe, 0x00, 1);
|
|
toshiba_spi_write(0xc0, 0x11, 1);
|
|
mdelay(1);
|
|
toshiba_spi_write(0xc1, 0x11, 1);
|
|
toshiba_spi_write(0xc2, 0x11, 1);
|
|
mdelay(1);
|
|
toshiba_spi_write(0xc3, 0x3232, 2);
|
|
mdelay(1);
|
|
toshiba_spi_write(0xc4, 0x3232, 2);
|
|
mdelay(1);
|
|
toshiba_spi_write(0xc5, 0x3232, 2);
|
|
mdelay(1);
|
|
toshiba_spi_write(0xc6, 0x3232, 2);
|
|
mdelay(1);
|
|
toshiba_spi_write(0xc7, 0x6445, 2);
|
|
mdelay(1);
|
|
toshiba_spi_write(0xc8, 0x44, 1);
|
|
toshiba_spi_write(0xc9, 0x52, 1);
|
|
mdelay(1);
|
|
toshiba_spi_write(0xca, 0x00, 1);
|
|
mdelay(1);
|
|
toshiba_spi_write(0xec, 0x02a4, 2); /* 0x02a4 */
|
|
mdelay(1);
|
|
toshiba_spi_write(0xcf, 0x01, 1);
|
|
mdelay(1);
|
|
toshiba_spi_write(0xd0, 0xc003, 2); /* c003 */
|
|
mdelay(1);
|
|
toshiba_spi_write(0xd1, 0x01, 1);
|
|
mdelay(1);
|
|
toshiba_spi_write(0xd2, 0x0028, 2);
|
|
mdelay(1);
|
|
toshiba_spi_write(0xd3, 0x0028, 2);
|
|
mdelay(1);
|
|
toshiba_spi_write(0xd4, 0x26a4, 2);
|
|
mdelay(1);
|
|
toshiba_spi_write(0xd5, 0x20, 1);
|
|
mdelay(1);
|
|
toshiba_spi_write(0xef, 0x3200, 2);
|
|
mdelay(32);
|
|
toshiba_spi_write(0xbc, 0x80, 1); /* wvga pass through */
|
|
toshiba_spi_write(0x3b, 0x00, 1);
|
|
mdelay(1);
|
|
toshiba_spi_write(0xb0, 0x16, 1);
|
|
mdelay(1);
|
|
toshiba_spi_write(0xb8, 0xfff5, 2);
|
|
mdelay(1);
|
|
toshiba_spi_write(0x11, 0, 0);
|
|
mdelay(5);
|
|
toshiba_spi_write(0x29, 0, 0);
|
|
mdelay(5);
|
|
}
|
|
}
|
|
|
|
void lcdc_on(void)
|
|
{
|
|
lcdc_clock_init(27648000);
|
|
lcdc_toshiba_panel_power(1);
|
|
lcdc_disp_on();
|
|
}
|
|
|
|
#endif
|