154 lines
5.0 KiB
C
154 lines
5.0 KiB
C
/*
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* Copyright (c) 2008, Google Inc.
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* All rights reserved.
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* Copyright (c) 2009, Code Aurora Forum. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <stdint.h>
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#include <kernel/thread.h>
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#include <platform/iomap.h>
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#include <reg.h>
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#define ARRAY_SIZE(x) (sizeof(x)/sizeof((x)[0]))
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#define A11S_CLK_CNTL_ADDR (MSM_CSR_BASE + 0x100)
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#define A11S_CLK_SEL_ADDR (MSM_CSR_BASE + 0x104)
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#define VDD_SVS_PLEVEL_ADDR (MSM_CSR_BASE + 0x124)
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#define PLL2_L_VAL_ADDR (MSM_CLK_CTL_BASE + 0x33C)
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#define SRC_SEL_PLL1 1 /* PLL1. */
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#define SRC_SEL_PLL2 2 /* PLL2. */
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#define SRC_SEL_PLL3 3 /* PLL3. Used for 7x25. */
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#define DIV_4 3
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#define DIV_2 1
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#define WAIT_CNT 100
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#define VDD_LEVEL 7
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#define MIN_AXI_HZ 120000000
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#define ACPU_800MHZ 41
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void pll_request(unsigned pll, unsigned enable);
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void axi_clock_init(unsigned rate);
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/* The stepping frequencies have been choosen to make sure the step
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* is <= 256 MHz for both turbo mode and normal mode targets. The
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* table also assumes the ACPU is running at TCXO freq and AHB div is
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* set to DIV_1.
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*
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* To use the tables:
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* - Start at location 0/1 depending on clock source sel bit.
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* - Set values till end of table skipping every other entry.
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* - When you reach the end of the table, you are done scaling.
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*
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* TODO: Need to fix SRC_SEL_PLL1 for 7x25.
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*/
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uint32_t const clk_cntl_reg_val_7625[] = {
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(WAIT_CNT << 16) | (SRC_SEL_PLL1 << 4) | DIV_4,
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(WAIT_CNT << 16) | (SRC_SEL_PLL1 << 12) | (DIV_4 << 8),
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(WAIT_CNT << 16) | (SRC_SEL_PLL1 << 12) | (DIV_2 << 8),
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(WAIT_CNT << 16) | (SRC_SEL_PLL1 << 4) | DIV_2,
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(WAIT_CNT << 16) | (SRC_SEL_PLL3 << 4) | DIV_2,
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(WAIT_CNT << 16) | (SRC_SEL_PLL3 << 12) | (DIV_2 << 8),
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};
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uint32_t const clk_cntl_reg_val_7627[] = {
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(WAIT_CNT << 16) | (SRC_SEL_PLL1 << 4) | DIV_4,
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(WAIT_CNT << 16) | (SRC_SEL_PLL1 << 12) | (DIV_4 << 8),
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(WAIT_CNT << 16) | (SRC_SEL_PLL1 << 12) | (DIV_2 << 8),
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(WAIT_CNT << 16) | (SRC_SEL_PLL1 << 4) | DIV_2,
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(WAIT_CNT << 16) | (SRC_SEL_PLL2 << 4) | DIV_2,
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(WAIT_CNT << 16) | (SRC_SEL_PLL2 << 12) | (DIV_2 << 8),
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};
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uint32_t const clk_cntl_reg_val_7627T[] = {
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(WAIT_CNT << 16) | (SRC_SEL_PLL1 << 4) | DIV_4,
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(WAIT_CNT << 16) | (SRC_SEL_PLL1 << 12) | (DIV_4 << 8),
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(WAIT_CNT << 16) | (SRC_SEL_PLL1 << 12) | (DIV_2 << 8),
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(WAIT_CNT << 16) | (SRC_SEL_PLL1 << 4) | DIV_2,
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(WAIT_CNT << 16) | (SRC_SEL_PLL2 << 4),
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(WAIT_CNT << 16) | (SRC_SEL_PLL2 << 12),
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};
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/* Using DIV_4 for all cases to avoid worrying about turbo vs. normal
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* mode. Able to use DIV_4 for all steps because it's the largest AND
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* the final value. */
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uint32_t const clk_sel_reg_val[] = {
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DIV_4 << 1 | 1,
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DIV_4 << 1 | 0,
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DIV_4 << 1 | 0,
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DIV_4 << 1 | 1,
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DIV_4 << 1 | 1,
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DIV_4 << 1 | 0,
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};
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void mdelay(unsigned msecs);
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void acpu_clock_init(void)
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{
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unsigned i,clk;
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#if (!ENABLE_NANDWRITE)
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int *modem_stat_check = (MSM_SHARED_BASE + 0x14);
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/* Wait for modem to be ready before clock init */
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while (readl(modem_stat_check) != 1);
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#endif
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/* Increase VDD level to the final value. */
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writel((1 << 7) | (VDD_LEVEL << 3), VDD_SVS_PLEVEL_ADDR);
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#if (!ENABLE_NANDWRITE)
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thread_sleep(1);
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#else
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mdelay(1);
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#endif
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/* Read clock source select bit. */
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i = readl(A11S_CLK_SEL_ADDR) & 1;
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clk = readl(PLL2_L_VAL_ADDR) & 0x3F;
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/* Jump into table and set every other entry. */
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for(; i < ARRAY_SIZE(clk_cntl_reg_val_7627); i += 2) {
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#ifdef ENABLE_PLL3
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writel(clk_cntl_reg_val_7625[i], A11S_CLK_CNTL_ADDR);
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#else
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if(clk == ACPU_800MHZ)
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writel(clk_cntl_reg_val_7627T[i], A11S_CLK_CNTL_ADDR);
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else
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writel(clk_cntl_reg_val_7627[i], A11S_CLK_CNTL_ADDR);
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#endif
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/* Would need a dmb() here but the whole address space is
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* strongly ordered, so it should be fine.
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*/
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writel(clk_sel_reg_val[i], A11S_CLK_SEL_ADDR);
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#if (!ENABLE_NANDWRITE)
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thread_sleep(1);
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#else
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mdelay(1);
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#endif
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}
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}
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