214 lines
4.6 KiB
ArmAsm
214 lines
4.6 KiB
ArmAsm
/*
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* Copyright (c) 2008 Travis Geiselbrecht
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files
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* (the "Software"), to deal in the Software without restriction,
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* including without limitation the rights to use, copy, modify, merge,
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* publish, distribute, sublicense, and/or sell copies of the Software,
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* and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <asm.h>
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.text
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/* void arch_enable_ints(void); */
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FUNCTION(arch_enable_ints)
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mrs r0, cpsr
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bic r0, r0, #(1<<7) /* clear the I bit */
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msr cpsr_c, r0
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bx lr
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/* void arch_disable_ints(void); */
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FUNCTION(arch_disable_ints)
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mrs r0, cpsr
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orr r0, r0, #(1<<7)
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msr cpsr_c, r0
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bx lr
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/* int atomic_swap(int *ptr, int val); */
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FUNCTION(atomic_swap)
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swp r0, r2, [r1]
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bx lr
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/* int atomic_add(int *ptr, int val); */
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FUNCTION(atomic_add)
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#if ARM_ISA_ARMV6 || ARM_ISA_ARMV7
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/* use load/store exclusive */
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.L_loop_add:
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ldrex r12, [r0]
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add r2, r12, r1
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strex r3, r2, [r0]
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cmp r3, #0
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bne .L_loop_add
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/* save old value */
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mov r0, r12
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bx lr
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#else
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/* disable interrupts, do the add, and reenable */
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mrs r2, cpsr
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mov r12, r2
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orr r2, r2, #(3<<6)
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msr cpsr_c, r2
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/* ints disabled, old cpsr state in r12 */
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/* do the add, leave the previous value in r0 */
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mov r3, r0
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ldr r0, [r3]
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add r2, r0, r1
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str r2, [r3]
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/* restore interrupts and exit */
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msr cpsr_c, r12
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bx lr
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#endif
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/* int atomic_and(int *ptr, int val); */
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FUNCTION(atomic_and)
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#if ARM_ISA_ARMV6 || ARM_ISA_ARMV7
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/* use load/store exclusive */
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.L_loop_and:
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ldrex r12, [r0]
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and r2, r12, r1
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strex r3, r2, [r0]
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cmp r3, #0
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bne .L_loop_and
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/* save old value */
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mov r0, r12
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bx lr
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#else
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/* disable interrupts, do the and, and reenable */
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mrs r2, cpsr
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mov r12, r2
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orr r2, r2, #(3<<6)
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msr cpsr_c, r2
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/* ints disabled, old cpsr state in r12 */
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/* do the and, leave the previous value in r0 */
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mov r3, r0
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ldr r0, [r3]
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and r2, r0, r1
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str r2, [r3]
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/* restore interrupts and exit */
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msr cpsr_c, r12
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bx lr
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#endif
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/* int atomic_or(int *ptr, int val); */
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FUNCTION(atomic_or)
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#if ARM_ISA_ARMV6 || ARM_ISA_ARMV7
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/* use load/store exclusive */
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.L_loop_or:
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ldrex r12, [r0]
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orr r2, r12, r1
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strex r3, r2, [r0]
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cmp r3, #0
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bne .L_loop_or
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/* save old value */
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mov r0, r12
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bx lr
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#else
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/* disable interrupts, do the or, and reenable */
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mrs r2, cpsr
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mov r12, r2
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orr r2, r2, #(3<<6)
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msr cpsr_c, r2
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/* ints disabled, old cpsr state in r12 */
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/* do the or, leave the previous value in r0 */
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mov r3, r0
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ldr r0, [r3]
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orr r2, r0, r1
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str r2, [r3]
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/* restore interrupts and exit */
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msr cpsr_c, r12
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bx lr
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#endif
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/* void arch_idle(); */
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FUNCTION(arch_idle)
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#if ARM_CPU_CORTEX_A8
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.word 0xe320f003 /* wfi */
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#elif PLATFORM_MSM7K
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/* TODO: safely handle wfi */
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#elif ARM_CPU_ARM1136 || ARM_CPU_ARM926
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mov r0, #0
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mcr p15, 0, r0, c7, c0, #4
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#elif ARM_CPU_ARM7
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/* nothing to do here */
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#else
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#error unknown cpu
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#endif
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bx lr
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/* uint32_t arm_read_cr1(void) */
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FUNCTION(arm_read_cr1)
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mrc p15, 0, r0, c1, c0, 0
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bx lr
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/* void arm_write_cr1(uint32_t val) */
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FUNCTION(arm_write_cr1)
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mcr p15, 0, r0, c1, c0, 0
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bx lr
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/* uint32_t arm_read_cr1_aux(void) */
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FUNCTION(arm_read_cr1_aux)
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mrc p15, 0, r0, c1, c0, 1
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bx lr
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/* void arm_write_cr1_aux(uint32_t val) */
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FUNCTION(arm_write_cr1_aux)
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mcr p15, 0, r0, c1, c0, 1
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bx lr
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/* void arm_write_ttbr(uint32_t val) */
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FUNCTION(arm_write_ttbr)
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mcr p15, 0, r0, c2, c0, 0
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bx lr
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/* void arm_write_dacr(uint32_t val) */
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FUNCTION(arm_write_dacr)
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mcr p15, 0, r0, c3, c0, 0
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bx lr
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/* void arm_invalidate_tlb(void) */
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FUNCTION(arm_invalidate_tlb)
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mov r0, #0
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mcr p15, 0, r0, c8, c7, 0
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bx lr
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/* void arch_switch_stacks_and_call(addr_t call, addr_t stack) */
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FUNCTION(arch_switch_stacks_and_call)
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mov sp, r1
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bx r0
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/*void dmb(void) */
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FUNCTION(dmb)
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#if ARM_CPU_CORTEX_A8
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dmb sy
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#elif ARM_CPU_ARM1136
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mov r0, #0
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mcr p15, 0, r0, c7, c10, 5
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#endif
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bx lr
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