160 lines
5.6 KiB
C
160 lines
5.6 KiB
C
/*
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* Copyright (c) 2008, Google Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Google, Inc. nor the names of its contributors
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* may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <debug.h>
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#include <arch/arm.h>
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#include <reg.h>
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#include <kernel/thread.h>
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#include <platform/interrupts.h>
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#include <platform/irqs.h>
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#include <platform/iomap.h>
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#define VIC_REG(off) (MSM_VIC_BASE + (off))
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#define VIC_INT_SELECT0 VIC_REG(0x0000) /* 1: FIQ, 0: IRQ */
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#define VIC_INT_SELECT1 VIC_REG(0x0004) /* 1: FIQ, 0: IRQ */
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#define VIC_INT_EN0 VIC_REG(0x0010)
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#define VIC_INT_EN1 VIC_REG(0x0014)
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#define VIC_INT_ENCLEAR0 VIC_REG(0x0020)
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#define VIC_INT_ENCLEAR1 VIC_REG(0x0024)
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#define VIC_INT_ENSET0 VIC_REG(0x0030)
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#define VIC_INT_ENSET1 VIC_REG(0x0034)
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#define VIC_INT_TYPE0 VIC_REG(0x0040) /* 1: EDGE, 0: LEVEL */
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#define VIC_INT_TYPE1 VIC_REG(0x0044) /* 1: EDGE, 0: LEVEL */
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#define VIC_INT_POLARITY0 VIC_REG(0x0050) /* 1: NEG, 0: POS */
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#define VIC_INT_POLARITY1 VIC_REG(0x0054) /* 1: NEG, 0: POS */
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#define VIC_NO_PEND_VAL VIC_REG(0x0060)
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#define VIC_INT_MASTEREN VIC_REG(0x0068) /* 1: IRQ, 2: FIQ */
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#define VIC_CONFIG VIC_REG(0x006C) /* 1: USE ARM1136 VIC */
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#define VIC_SECURITY0 VIC_REG(0x0070)
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#define VIC_SECURITY1 VIC_REG(0x0074)
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#define VIC_IRQ_STATUS0 VIC_REG(0x0080)
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#define VIC_IRQ_STATUS1 VIC_REG(0x0084)
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#define VIC_FIQ_STATUS0 VIC_REG(0x0090)
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#define VIC_FIQ_STATUS1 VIC_REG(0x0094)
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#define VIC_RAW_STATUS0 VIC_REG(0x00A0)
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#define VIC_RAW_STATUS1 VIC_REG(0x00A4)
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#define VIC_INT_CLEAR0 VIC_REG(0x00B0)
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#define VIC_INT_CLEAR1 VIC_REG(0x00B4)
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#define VIC_SOFTINT0 VIC_REG(0x00C0)
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#define VIC_SOFTINT1 VIC_REG(0x00C4)
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#define VIC_IRQ_VEC_RD VIC_REG(0x00D0) /* pending int # */
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#define VIC_IRQ_VEC_PEND_RD VIC_REG(0x00D4) /* pending vector addr */
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#define VIC_IRQ_VEC_WR VIC_REG(0x00D8)
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#define VIC_FIQ_VEC_RD VIC_REG(0x00DC) /* pending int # */
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#define VIC_FIQ_VEC_PEND_RD VIC_REG(0x00E0) /* pending vector addr */
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#define VIC_FIQ_VEC_WR VIC_REG(0x00E4)
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#define VIC_IRQ_IN_SERVICE VIC_REG(0x00E8)
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#define VIC_IRQ_IN_STACK VIC_REG(0x00EC)
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#define VIC_FIQ_IN_SERVICE VIC_REG(0x00F0)
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#define VIC_FIQ_IN_STACK VIC_REG(0x00F4)
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#define VIC_TEST_BUS_SEL VIC_REG(0x00F8)
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#define SIRC_REG(off) (MSM_SIRC_BASE + (off))
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#define SIRC_INT_SELECT SIRC_REG(0x0000) /* 0: IRQ0 1: IRQ1 */
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#define SIRC_INT_ENABLE SIRC_REG(0x0004)
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#define SIRC_INT_ENCLEAR SIRC_REG(0x0008)
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#define SIRC_INT_ENSET SIRC_REG(0x000C)
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#define SIRC_INT_TYPE SIRC_REG(0x0010) /* 1: EDGE, 0: LEVEL */
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#define SIRC_INT_POLARITY SIRC_REG(0x0014) /* 1: NEG, 0: POS */
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#define SIRC_SECURITY SIRC_REG(0x0018) /* 0: SEC, 1: NSEC */
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#define SIRC_IRQ0_STATUS SIRC_REG(0x001C)
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#define SIRC_IRQ1_STATUS SIRC_REG(0x0020)
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#define SIRC_RAW_STATUS SIRC_REG(0x0024)
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struct ihandler {
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int_handler func;
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void *arg;
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};
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static struct ihandler handler[NR_IRQS];
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void platform_init_interrupts(void)
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{
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writel(0xffffffff, VIC_INT_CLEAR0);
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writel(0xffffffff, VIC_INT_CLEAR1);
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writel(0, VIC_INT_SELECT0);
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writel(0, VIC_INT_SELECT1);
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writel(0xffffffff, VIC_INT_TYPE0);
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writel(0xffffffff, VIC_INT_TYPE1);
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writel(0, VIC_CONFIG);
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writel(1, VIC_INT_MASTEREN);
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}
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enum handler_return platform_irq(struct arm_iframe *frame)
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{
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unsigned num;
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enum handler_return ret;
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num = readl(VIC_IRQ_VEC_RD);
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num = readl(VIC_IRQ_VEC_PEND_RD);
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if (num > NR_IRQS)
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return 0;
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writel(1 << (num & 31), (num > 31) ? VIC_INT_CLEAR1 : VIC_INT_CLEAR0);
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ret = handler[num].func(handler[num].arg);
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writel(0, VIC_IRQ_VEC_WR);
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return ret;
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}
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void platform_fiq(struct arm_iframe *frame)
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{
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PANIC_UNIMPLEMENTED;
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}
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status_t mask_interrupt(unsigned int vector)
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{
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unsigned reg = (vector > 31) ? VIC_INT_ENCLEAR1 : VIC_INT_ENCLEAR0;
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unsigned bit = 1 << (vector & 31);
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writel(bit, reg);
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return 0;
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}
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status_t unmask_interrupt(unsigned int vector)
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{
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unsigned reg = (vector > 31) ? VIC_INT_ENSET1 : VIC_INT_ENSET0;
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unsigned bit = 1 << (vector & 31);
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writel(bit, reg);
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return 0;
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}
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void register_int_handler(unsigned int vector, int_handler func, void *arg)
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{
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if (vector >= NR_IRQS)
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return;
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enter_critical_section();
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handler[vector].func = func;
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handler[vector].arg = arg;
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exit_critical_section();
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}
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