105 lines
3.1 KiB
C
105 lines
3.1 KiB
C
/*
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* Copyright (c) 2008 Travis Geiselbrecht
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files
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* (the "Software"), to deal in the Software without restriction,
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* including without limitation the rights to use, copy, modify, merge,
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* publish, distribute, sublicense, and/or sell copies of the Software,
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* and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <debug.h>
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#include <arch.h>
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#include <arch/ops.h>
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#include <arch/arm.h>
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#include <arch/arm/mmu.h>
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#include <platform.h>
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#if ARM_CPU_CORTEX_A8
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static void set_vector_base(addr_t addr)
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{
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__asm__ volatile("mcr p15, 0, %0, c12, c0, 0" :: "r" (addr));
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}
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#endif
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void arch_early_init(void)
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{
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/* turn off the cache */
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arch_disable_cache(UCACHE);
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/* set the vector base to our exception vectors so we dont need to double map at 0 */
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#if ARM_CPU_CORTEX_A8
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set_vector_base(MEMBASE);
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#endif
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#if ARM_WITH_MMU
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arm_mmu_init();
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platform_init_mmu_mappings();
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#endif
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/* turn the cache back on */
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arch_enable_cache(UCACHE);
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#if ARM_WITH_NEON
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/* enable cp10 and cp11 */
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uint32_t val;
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__asm__ volatile("mrc p15, 0, %0, c1, c0, 2" : "=r" (val));
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val |= (3<<22)|(3<<20);
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__asm__ volatile("mcr p15, 0, %0, c1, c0, 2" :: "r" (val));
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/* set enable bit in fpexc */
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val = (1<<30);
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__asm__ volatile("mcr p10, 7, %0, c8, c0, 0" :: "r" (val));
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#endif
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#if ARM_CPU_CORTEX_A8
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/* enable the cycle count register */
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uint32_t en;
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__asm__ volatile("mrc p15, 0, %0, c9, c12, 0" : "=r" (en));
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en &= ~(1<<3); /* cycle count every cycle */
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en |= 1; /* enable all performance counters */
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__asm__ volatile("mcr p15, 0, %0, c9, c12, 0" :: "r" (en));
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/* enable cycle counter */
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en = (1<<31);
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__asm__ volatile("mcr p15, 0, %0, c9, c12, 1" :: "r" (en));
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#endif
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}
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void arch_quiesce(void)
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{
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#if ARM_CPU_CORTEX_A8
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/* disable the cycle count and performance counters */
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uint32_t en;
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__asm__ volatile("mrc p15, 0, %0, c9, c12, 0" : "=r" (en));
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en &= ~1; /* disable all performance counters */
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__asm__ volatile("mcr p15, 0, %0, c9, c12, 0" :: "r" (en));
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/* disable cycle counter */
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en = 0;
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__asm__ volatile("mcr p15, 0, %0, c9, c12, 1" :: "r" (en));
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#endif
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#if ARM_CPU_ARM1136
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/* disable the cycle count and performance counters */
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uint32_t en;
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__asm__ volatile("mrc p15, 0, %0, c15, c12, 0" : "=r" (en));
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en &= ~1; /* disable all performance counters */
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__asm__ volatile("mcr p15, 0, %0, c15, c12, 0" :: "r" (en));
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#endif
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}
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void arch_init(void)
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{
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}
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