87 lines
2.5 KiB
ArmAsm
87 lines
2.5 KiB
ArmAsm
.text
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.code 32
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.globl htcleo_boot_s
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htcleo_boot_s:
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// save registers
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MOV r9, r0
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//cedesmith:
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// cotulla's code so kernel will not crash. aux control register
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// found more info here: http://www.spinics.net/lists/linux-arm-msm/msg00492.html
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// it looks it is Martijn Stolk's code
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MRC p15, 0, r0, c1, c0, 1
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BIC r0, r0, #0x40 //; (1<<6) IBE (0 = executes the CP15 Invalidate All and Invalidate by MVA instructions as a NOP instruction, reset value)
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BIC r0, r0, #0x200000 //; (1<<21) undocumented bit
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MCR p15, 0, r0, c1, c0, 1
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//; Disable VFP
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MOV R0, #0
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FMXR FPEXC, r0
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//; ICIALL to invalidate entire I-Cache
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MCR p15, 0, r0, c7, c5, 0 //; ICIALLU
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// disable dcache and i cache
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MRC p15, 0, r0, c1, c0, 0
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BIC r0, r0, #(1<<0) // disable mmu ( already disabled )
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BIC r0, r0, #(1<<2) // disable data cache
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BIC r0, r0, #(1<<12) // disable instruction cache
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MCR p15, 0, r0, c1, c0, 0
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ISB
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//; DCIALL to invalidate L2 cache bank (needs to be run 4 times, once per bank)
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//; This must be done early in code (prior to enabling the caches)
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MOV r0, #0x2
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MCR p15, 0, r0, c9, c0, 6 //; DCIALL bank D ([15:14] == 2'b00)
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ORR r0, r0, #0x00004000
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MCR p15, 0, r0, c9, c0, 6 //; DCIALL bank C ([15:14] == 2'b01)
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ADD r0, r0, #0x00004000
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MCR p15, 0, r0, c9, c0, 6 //; DCIALL bank B ([15:14] == 2'b10)
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ADD r0, r0, #0x00004000
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MCR p15, 0, r0, c9, c0, 6 //; DCIALL bank A ([15:14] == 2'b11)
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//; DCIALL to invalidate entire D-Cache
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MOV r0, #0
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MCR p15, 0, r0, c9, c0, 6 //; DCIALL r0
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DSB
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ISB
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//; Invalidate the UTLB
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MOV r0, #0
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MCR p15, 0, r0, c8, c7, 0 //; UTLBIALL
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ISB
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//flashlight to see we get here
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//ldr r4, =0xa9000864 @ bank6_in (phys)
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//ldr r5, =0xa9000814 @ bank6_out (phys)
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//orr r6, r4, #0x200000 @ 22nd bit for flash
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//str r6, [r5, #0] @ store in out (enables bright for 500ms, limited by hardware)
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MOV R0, #0
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BLX R9
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.ltorg
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.global htcleo_flash
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htcleo_flash:
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ldr r4, =0xa9000864
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ldr r5, =0xa9000814
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orr r6, r4, #0x200000
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str r6, [r5, #0]
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bx lr
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.ltorg
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// code to put at 0, get opcode from debug.lst
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.global pc_reset_vector
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.global pc_reset_vector_end
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pc_reset_vector:
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mov r0, #0x11800000
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ldr pc, [r0, #4]
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//mov pc, #MEMBASE
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#ldr pc, #MEMBASE
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BX LR
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pc_reset_vector_end:
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.ltorg
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