96 lines
4.0 KiB
C
96 lines
4.0 KiB
C
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/*
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* Copyright (c) 2008, Google Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef __PLATFORM_MSM_SHARED_NAND_H
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#define __PLATFORM_MSM_SHARED_NAND_H
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#define MSM_NAND_BASE 0xA0A00000
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/* see 80-VA736-2 C pp 354-414 */
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#define NAND_REG(off) (MSM_NAND_BASE + (off))
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#define NAND_FLASH_CMD NAND_REG(0x0000)
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#define NAND_ADDR0 NAND_REG(0x0004)
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#define NAND_ADDR1 NAND_REG(0x0008)
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#define NAND_FLASH_CHIP_SELECT NAND_REG(0x000C)
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#define NAND_EXEC_CMD NAND_REG(0x0010)
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#define NAND_FLASH_STATUS NAND_REG(0x0014)
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#define NAND_BUFFER_STATUS NAND_REG(0x0018)
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#define NAND_DEV0_CFG0 NAND_REG(0x0020)
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#define NAND_DEV0_CFG1 NAND_REG(0x0024)
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#define NAND_DEV1_CFG0 NAND_REG(0x0030)
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#define NAND_DEV1_CFG1 NAND_REG(0x0034)
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#define NAND_READ_ID NAND_REG(0x0040)
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#define NAND_READ_STATUS NAND_REG(0x0044)
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#define NAND_CONFIG_DATA NAND_REG(0x0050)
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#define NAND_CONFIG NAND_REG(0x0054)
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#define NAND_CONFIG_MODE NAND_REG(0x0058)
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#define NAND_CONFIG_STATUS NAND_REG(0x0060)
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#define NAND_MACRO1_REG NAND_REG(0x0064)
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#define NAND_XFR_STEP1 NAND_REG(0x0070)
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#define NAND_XFR_STEP2 NAND_REG(0x0074)
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#define NAND_XFR_STEP3 NAND_REG(0x0078)
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#define NAND_XFR_STEP4 NAND_REG(0x007C)
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#define NAND_XFR_STEP5 NAND_REG(0x0080)
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#define NAND_XFR_STEP6 NAND_REG(0x0084)
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#define NAND_XFR_STEP7 NAND_REG(0x0088)
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#define NAND_DEV_CMD0 NAND_REG(0x00A0)
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#define NAND_DEV_CMD1 NAND_REG(0x00A4)
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#define NAND_DEV_CMD2 NAND_REG(0x00A8)
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#define NAND_DEV_CMD_VLD NAND_REG(0x00AC)
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#define NAND_EBI2_MISR_SIG_REG NAND_REG(0x00B0)
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#define NAND_SFLASHC_BURST_CFG NAND_REG(0x00E0)
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#define NAND_EBI2_ECC_BUF_CFG NAND_REG(0x00F0)
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#define NAND_FLASH_BUFFER NAND_REG(0x0100)
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/* device commands */
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#define NAND_CMD_SOFT_RESET 0x01
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#define NAND_CMD_PAGE_READ 0x32
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#define NAND_CMD_PAGE_READ_ECC 0x33
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#define NAND_CMD_PAGE_READ_ALL 0x34
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#define NAND_CMD_SEQ_PAGE_READ 0x15
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#define NAND_CMD_PRG_PAGE 0x36
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#define NAND_CMD_PRG_PAGE_ECC 0x37
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#define NAND_CMD_PRG_PAGE_ALL 0x39
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#define NAND_CMD_BLOCK_ERASE 0x3A
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#define NAND_CMD_FETCH_ID 0x0B
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#define NAND_CMD_STATUS 0x0C
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#define NAND_CMD_RESET 0x0D
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#define CLEAN_DATA_32 0xFFFFFFFF
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#define CLEAN_DATA_16 0xFFFF
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/* Flash type */
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#define FLASH_UNKNOWN_DEVICE 0x00
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#define FLASH_NAND_DEVICE 0x01
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#define FLASH_8BIT_NAND_DEVICE 0x01
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#define FLASH_16BIT_NAND_DEVICE 0x02
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#endif /* __PLATFORM_MSM_SHARED_NAND_H */
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