220 lines
5.2 KiB
ArmAsm
220 lines
5.2 KiB
ArmAsm
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/*
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* Copyright (c) 2008 Travis Geiselbrecht
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files
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* (the "Software"), to deal in the Software without restriction,
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* including without limitation the rights to use, copy, modify, merge,
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* publish, distribute, sublicense, and/or sell copies of the Software,
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* and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#define DSB .byte 0x4f, 0xf0, 0x7f, 0xf5
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#define ISB .byte 0x6f, 0xf0, 0x7f, 0xf5
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.text
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.globl _start
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_start:
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b reset
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b arm_undefined
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b arm_syscall
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b arm_prefetch_abort
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b arm_data_abort
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b arm_reserved
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b arm_irq
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b arm_fiq
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#ifdef WSPL_VADDR
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//if LK is loaded by wince spl add romhdr
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.org 0x40
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.word 0x43454345
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.word (romhdr-_start)+WSPL_VADDR // virtual address of romhdr
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//.word romhdr+0x96C00000 // virtual address of romhdr
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.word romhdr-_start // file address of romhdr
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.org 0x00000900
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romhdr:
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.word 0x2000000 // dllfirst
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.word 0x2000000 // dlllast
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.word WSPL_VADDR // physfirst
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.word WSPL_VADDR+(_end-_start) // physlast
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.word 0 // nummods (no TOCentry after ROMHDR)
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.word WSPL_VADDR+(_end-_start) // ulRAMStart
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.word WSPL_VADDR+(_end-_start) // ulRAMFree
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.word WSPL_VADDR+MEMSIZE // ulRAMEnd
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.word 0 // ulCopyEntries
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.word 0 // ulCopyOffset
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.word 0 // ulProfileLen
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.word 0 // ulProfileOffset
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.word 0 // numfiles
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.word 0 // ulKernelFlags
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.word 0x80808080 // ulFSRamPercent
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.word 0 // ulDrivglobStart
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.word 0 // ulDrivglobLen
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.hword 0x1C2 // usCPUType
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.hword 0x2 // usMiscFlags
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.word 0 // pExtensions
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.word 0 // ulTrackingStart
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.word 0 // ulTrackingLen
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.org 0x00001000
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#endif
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reset:
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/* do some cpu setup */
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#if ARM_WITH_CP15
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mrc p15, 0, r0, c1, c0, 0
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/* XXX this is currently for arm926, revist with armv6 cores */
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/* new thumb behavior, low exception vectors, i/d cache disable, mmu disabled */
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bic r0, r0, #(1<<15| 1<<13 | 1<<12)
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bic r0, r0, #(1<<2 | 1<<0)
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/* enable alignment faults */
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orr r0, r0, #(1<<1)
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mcr p15, 0, r0, c1, c0, 0
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#endif
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#if WITH_CPU_EARLY_INIT
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/* call platform/arch/etc specific init code */
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bl __cpu_early_init
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/* declare return address as global to avoid using stack */
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.globl _cpu_early_init_complete
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_cpu_early_init_complete:
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#endif
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#if (!ENABLE_NANDWRITE)
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#if WITH_CPU_WARM_BOOT
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ldr r0, warm_boot_tag
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cmp r0, #1
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/* if set, warm boot */
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ldreq pc, =BASE_ADDR
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mov r0, #1
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str r0, warm_boot_tag
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#endif
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#endif
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/* see if we need to relocate */
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ldr r1, = .Laddr
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ldr r0, = _start
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sub r1, r1, r0
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mov r0, pc
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sub r0, r0, r1 //#(.Laddr - _start)
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.Laddr:
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str r0, load_address
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ldr r1, =_start
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cmp r0, r1
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beq .Lstack_setup
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/* we need to relocate ourselves to the proper spot */
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ldr r2, =__data_end
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.Lrelocate_loop:
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ldr r3, [r0], #4
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str r3, [r1], #4
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cmp r1, r2
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bne .Lrelocate_loop
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/* we're relocated, jump to the right address */
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ldr r0, =.Lstack_setup
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bx r0
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.ltorg
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#if WITH_CPU_WARM_BOOT
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warm_boot_tag:
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.word 0
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#endif
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.global load_address
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load_address:
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.word 0
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.Lstack_setup:
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/* set up the stack for irq, fiq, abort, undefined, system/user, and lastly supervisor mode */
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mrs r0, cpsr
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bic r0, r0, #0x1f
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ldr r2, =abort_stack_top
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orr r1, r0, #0x12 // irq
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msr cpsr_c, r1
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ldr r13, =irq_save_spot /* save a pointer to a temporary dumping spot used during irq delivery */
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orr r1, r0, #0x11 // fiq
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msr cpsr_c, r1
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mov sp, r2
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orr r1, r0, #0x17 // abort
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msr cpsr_c, r1
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mov sp, r2
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orr r1, r0, #0x1b // undefined
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msr cpsr_c, r1
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mov sp, r2
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orr r1, r0, #0x1f // system
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msr cpsr_c, r1
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mov sp, r2
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orr r1, r0, #0x13 // supervisor
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msr cpsr_c, r1
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mov sp, r2
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/* copy the initialized data segment out of rom if necessary */
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ldr r0, =__data_start_rom
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ldr r1, =__data_start
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ldr r2, =__data_end
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cmp r0, r1
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beq .L__do_bss
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.L__copy_loop:
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cmp r1, r2
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ldrlt r3, [r0], #4
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strlt r3, [r1], #4
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blt .L__copy_loop
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.L__do_bss:
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/* clear out the bss */
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ldr r0, =__bss_start
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ldr r1, =_end
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mov r2, #0
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.L__bss_loop:
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cmp r0, r1
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strlt r2, [r0], #4
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blt .L__bss_loop
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#ifdef ARM_CPU_CORTEX_A8
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DSB
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ISB
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#endif
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bl kmain
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b .
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.ltorg
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.bss
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.align 2
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/* the abort stack is for unrecoverable errors.
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* also note the initial working stack is set to here.
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* when the threading system starts up it'll switch to a new
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* dynamically allocated stack, so we don't need it for very long
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*/
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abort_stack:
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.skip 1024
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abort_stack_top:
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