208 lines
6.1 KiB
C
208 lines
6.1 KiB
C
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/*
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* Copyright (c) 2008, Google Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Google, Inc. nor the names of its contributors
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* may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <debug.h>
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#include <platform/iomap.h>
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#include <dev/uart.h>
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#include <reg.h>
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#define UART_MR1 0x0000
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#define UART_MR1_AUTO_RFR_LEVEL0(n) (((n) & 0x3f) << 8)
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#define UART_MR1_RX_RDY_CTL (1 << 7)
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#define UART_MR1_CTS_CTL (1 << 6)
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#define UART_MR1_AUTO_RFR_LEVEL1(n) ((n) & 0x3f)
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#define UART_MR2 0x0004
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#define UART_MR2_ERROR_MODE (1 << 6)
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#define UART_MR2_BITS_PER_CHAR_5 (0 << 4)
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#define UART_MR2_BITS_PER_CHAR_6 (1 << 4)
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#define UART_MR2_BITS_PER_CHAR_7 (2 << 4)
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#define UART_MR2_BITS_PER_CHAR_8 (3 << 4)
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#define UART_MR2_STOP_BIT_LEN_0563 (0 << 2)
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#define UART_MR2_STOP_BIT_LEN_1000 (1 << 2)
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#define UART_MR2_STOP_BIT_LEN_1563 (2 << 2)
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#define UART_MR2_STOP_BIT_LEN_2000 (3 << 2)
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#define UART_MR2_PARITY_MODE_NONE (0)
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#define UART_MR2_PARITY_MODE_ODD (1)
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#define UART_MR2_PARITY_MODE_EVEN (2)
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#define UART_MR2_PARITY_MODE_SPACE (3)
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#define UART_CSR 0x0008
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#define UART_CSR_115200 0xFF
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#define UART_CSR_57600 0xEE
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#define UART_CSR_38400 0xDD
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#define UART_CSR_19200 0xBB
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#define UART_TF 0x000C
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#define UART_CR 0x0010
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#define UART_CR_CMD_NULL (0 << 4)
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#define UART_CR_CMD_RESET_RX (1 << 4)
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#define UART_CR_CMD_RESET_TX (2 << 4)
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#define UART_CR_CMD_RESET_ERR (3 << 4)
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#define UART_CR_CMD_RESET_BCI (4 << 4)
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#define UART_CR_CMD_START_BREAK (5 << 4)
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#define UART_CR_CMD_STOP_BREAK (6 << 4)
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#define UART_CR_CMD_RESET_CTS_N (7 << 4)
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#define UART_CR_CMD_PACKET_MODE (9 << 4)
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#define UART_CR_CMD_MODE_RESET (12<< 4)
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#define UART_CR_CMD_SET_RFR_N (13<< 4)
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#define UART_CR_CMD_RESET_RFR_ND (14<< 4)
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#define UART_CR_TX_DISABLE (1 << 3)
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#define UART_CR_TX_ENABLE (1 << 3)
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#define UART_CR_RX_DISABLE (1 << 3)
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#define UART_CR_RX_ENABLE (1 << 3)
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#define UART_IMR 0x0014
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#define UART_IMR_RXLEV (1 << 4)
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#define UART_IMR_TXLEV (1 << 0)
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#define UART_IPR 0x0018
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#define UART_TFWR 0x001C
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#define UART_RFWR 0x0020
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#define UART_HCR 0x0024
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#define UART_MREG 0x0028
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#define UART_NREG 0x002C
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#define UART_DREG 0x0030
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#define UART_MNDREG 0x0034
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#define UART_IRDA 0x0038
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#define UART_MISR_MODE 0x0040
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#define UART_MISR_RESET 0x0044
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#define UART_MISR_EXPORT 0x0048
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#define UART_MISR_VAL 0x004C
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#define UART_TEST_CTRL 0x0050
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#define UART_SR 0x0008
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#define UART_SR_HUNT_CHAR (1 << 7)
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#define UART_SR_RX_BREAK (1 << 6)
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#define UART_SR_PAR_FRAME_ERR (1 << 5)
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#define UART_SR_OVERRUN (1 << 4)
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#define UART_SR_TX_EMPTY (1 << 3)
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#define UART_SR_TX_READY (1 << 2)
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#define UART_SR_RX_FULL (1 << 1)
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#define UART_SR_RX_READY (1 << 0)
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#define UART_RF 0x000C
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#define UART_MISR 0x0010
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#define UART_ISR 0x0014
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static unsigned uart_ready = 0;
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#if PLATFORM_MSM7X30
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static unsigned uart_base = MSM_UART2_BASE;
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#else
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static unsigned uart_base = MSM_UART3_BASE;
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#endif
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#define uwr(v,a) writel(v, uart_base + (a))
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#define urd(a) readl(uart_base + (a))
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void uart_init(void)
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{
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uwr(0x0A, UART_CR); /* disable TX and RX */
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uwr(0x30, UART_CR); /* reset error status */
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uwr(0x10, UART_CR); /* reset receiver */
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uwr(0x20, UART_CR); /* reset transmitter */
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#if PLATFORM_QSD8K || PLATFORM_MSM7X30
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/* TCXO */
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uwr(0x06, UART_MREG);
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uwr(0xF1, UART_NREG);
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uwr(0x0F, UART_DREG);
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uwr(0x1A, UART_MNDREG);
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#else
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/* TCXO/4 */
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uwr(0xC0, UART_MREG);
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uwr(0xAF, UART_NREG);
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uwr(0x80, UART_DREG);
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uwr(0x19, UART_MNDREG);
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#endif
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uwr(0x10, UART_CR); /* reset RX */
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uwr(0x20, UART_CR); /* reset TX */
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uwr(0x30, UART_CR); /* reset error status */
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uwr(0x40, UART_CR); /* reset RX break */
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uwr(0x70, UART_CR); /* rest? */
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uwr(0xD0, UART_CR); /* reset */
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uwr(0x7BF, UART_IPR); /* stale timeout = 630 * bitrate */
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uwr(0, UART_IMR);
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uwr(115, UART_RFWR); /* RX watermark = 58 * 2 - 1 */
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uwr(10, UART_TFWR); /* TX watermark */
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uwr(0, UART_RFWR);
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uwr(UART_CSR_115200, UART_CSR);
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uwr(0, UART_IRDA);
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uwr(0x1E, UART_HCR);
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// uwr(0x7F4, UART_MR1); /* RFS/ CTS/ 500chr RFR */
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uwr(16, UART_MR1);
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uwr(0x34, UART_MR2); /* 8N1 */
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uwr(0x05, UART_CR); /* enable TX & RX */
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uart_ready = 1;
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}
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static int _uart_putc(int port, char c)
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{
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if (!uart_ready)
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return -1;
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while (!(urd(UART_SR) & UART_SR_TX_READY)) ;
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uwr(c, UART_TF);
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return 0;
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}
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int uart_putc (int port, char c)
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{
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if(c == '\n')
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{
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_uart_putc(0, '\r');
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}
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_uart_putc(0, c);
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}
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int uart_getc(int port, bool wait)
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{
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if (!uart_ready)
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return -1;
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while (!(urd(UART_SR) & UART_SR_RX_READY))
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if (!wait)
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return -1;
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return urd(UART_RF);
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}
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