274 lines
12 KiB
C
274 lines
12 KiB
C
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/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of Code Aurora Forum, Inc. nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __UART_DM_H__
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#define __UART_DM_H__
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#define MSM_BOOT_UART_DM_EXTR_BITS(value, start_pos, end_pos) \
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((value << (32 - end_pos))\
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>> (32 - (end_pos - start_pos)))
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/* GPIO pins - 2 wire using UART2 */
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#define MSM_BOOT_UART_DM_RX_GPIO 117
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#define MSM_BOOT_UART_DM_TX_GPIO 118
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/* UART Parity Mode */
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enum MSM_BOOT_UART_DM_PARITY_MODE
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{
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MSM_BOOT_UART_DM_NO_PARITY,
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MSM_BOOT_UART_DM_ODD_PARITY,
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MSM_BOOT_UART_DM_EVEN_PARITY,
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MSM_BOOT_UART_DM_SPACE_PARITY
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};
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/* UART Stop Bit Length */
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enum MSM_BOOT_UART_DM_STOP_BIT_LEN
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{
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MSM_BOOT_UART_DM_SBL_9_16,
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MSM_BOOT_UART_DM_SBL_1,
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MSM_BOOT_UART_DM_SBL_1_9_16,
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MSM_BOOT_UART_DM_SBL_2
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};
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/* UART Bits per Char */
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enum MSM_BOOT_UART_DM_BITS_PER_CHAR
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{
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MSM_BOOT_UART_DM_5_BPS,
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MSM_BOOT_UART_DM_6_BPS,
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MSM_BOOT_UART_DM_7_BPS,
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MSM_BOOT_UART_DM_8_BPS
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};
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/* 8-N-1 Configuration */
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#define MSM_BOOT_UART_DM_8_N_1_MODE (MSM_BOOT_UART_DM_NO_PARITY | \
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(MSM_BOOT_UART_DM_SBL_1 << 2) | \
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(MSM_BOOT_UART_DM_8_BPS << 4))
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/* CSR is used to further divide fundamental frequency.
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* Using EE we are dividing gsbi_uart_clk by 2 so as to get
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* 115.2k bit rate for fundamental frequency of 3.6864 MHz */
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#define MSM_BOOT_UART_DM_RX_TX_BIT_RATE 0xEE
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/*
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* Define Macros for GSBI and UARTDM Registers
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*/
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/* Clocks */
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#define MSM_BOOT_CLK_CTL_BASE 0x00900000
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#define MSM_BOOT_PLL_ENABLE_SC0 (MSM_BOOT_CLK_CTL_BASE + 0x34C0)
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#define MSM_BOOT_PLL8_STATUS (MSM_BOOT_CLK_CTL_BASE + 0x3158)
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#define MSM_BOOT_GSBIn_HCLK_CTL(n) (MSM_BOOT_CLK_CTL_BASE + 0x29A0 +\
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( 32 * n ))
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#define MSM_BOOT_GSBIn_UART_APPS_MD(n) (MSM_BOOT_CLK_CTL_BASE + 0x29B0 +\
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( 32 * n))
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#define MSM_BOOT_GSBIn_UART_APPS_NS(n) (MSM_BOOT_CLK_CTL_BASE + 0x29B4 +\
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(32 * n))
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#define MSM_BOOT_UART_DM_GSBI_HCLK_CTL MSM_BOOT_GSBIn_HCLK_CTL(12)
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#define MSM_BOOT_UART_DM_APPS_MD MSM_BOOT_GSBIn_UART_APPS_MD(12)
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#define MSM_BOOT_UART_DM_APPS_NS MSM_BOOT_GSBIn_UART_APPS_NS(12)
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/* Using GSBI12 for UART */
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#define MSM_BOOT_GSBI_BASE 0x19C00000
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#define MSM_BOOT_GSBI_CTRL_REG MSM_BOOT_GSBI_BASE
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#define MSM_BOOT_UART_DM_BASE (MSM_BOOT_GSBI_BASE+0x40000)
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#define MSM_BOOT_UART_DM_REG(offset) (MSM_BOOT_UART_DM_BASE + offset)
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/* UART Operational Mode Register */
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#define MSM_BOOT_UART_DM_MR1 MSM_BOOT_UART_DM_REG(0x0000)
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#define MSM_BOOT_UART_DM_MR2 MSM_BOOT_UART_DM_REG(0x0004)
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#define MSM_BOOT_UART_DM_RXBRK_ZERO_CHAR_OFF (1 << 8)
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#define MSM_BOOT_UART_DM_LOOPBACK (1 << 7)
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/* UART Clock Selection Register */
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#define MSM_BOOT_UART_DM_CSR MSM_BOOT_UART_DM_REG(0x0008)
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/* UART DM TX FIFO Registers - 4 */
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#define MSM_BOOT_UART_DM_TF(x) MSM_BOOT_UART_DM_REG(0x0070+(4*x))
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/* UART Command Register */
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#define MSM_BOOT_UART_DM_CR MSM_BOOT_UART_DM_REG(0x0010)
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#define MSM_BOOT_UART_DM_CR_RX_ENABLE (1 << 0)
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#define MSM_BOOT_UART_DM_CR_RX_DISABLE (1 << 1)
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#define MSM_BOOT_UART_DM_CR_TX_ENABLE (1 << 2)
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#define MSM_BOOT_UART_DM_CR_TX_DISABLE (1 << 3)
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/* UART Channel Command */
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#define MSM_BOOT_UART_DM_CR_CH_CMD_LSB(x) ((x & 0x0f) << 4)
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#define MSM_BOOT_UART_DM_CR_CH_CMD_MSB(x) ((x >> 4 ) << 11 )
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#define MSM_BOOT_UART_DM_CR_CH_CMD(x) (MSM_BOOT_UART_DM_CR_CH_CMD_LSB(x) | \
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MSM_BOOT_UART_DM_CR_CH_CMD_MSB(x))
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#define MSM_BOOT_UART_DM_CMD_NULL MSM_BOOT_UART_DM_CR_CH_CMD(0)
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#define MSM_BOOT_UART_DM_CMD_RESET_RX MSM_BOOT_UART_DM_CR_CH_CMD(1)
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#define MSM_BOOT_UART_DM_CMD_RESET_TX MSM_BOOT_UART_DM_CR_CH_CMD(2)
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#define MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT MSM_BOOT_UART_DM_CR_CH_CMD(3)
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#define MSM_BOOT_UART_DM_CMD_RES_BRK_CHG_INT MSM_BOOT_UART_DM_CR_CH_CMD(4)
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#define MSM_BOOT_UART_DM_CMD_START_BRK MSM_BOOT_UART_DM_CR_CH_CMD(5)
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#define MSM_BOOT_UART_DM_CMD_STOP_BRK MSM_BOOT_UART_DM_CR_CH_CMD(6)
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#define MSM_BOOT_UART_DM_CMD_RES_CTS_N MSM_BOOT_UART_DM_CR_CH_CMD(7)
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#define MSM_BOOT_UART_DM_CMD_RES_STALE_INT MSM_BOOT_UART_DM_CR_CH_CMD(8)
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#define MSM_BOOT_UART_DM_CMD_PACKET_MODE MSM_BOOT_UART_DM_CR_CH_CMD(9)
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#define MSM_BOOT_UART_DM_CMD_MODE_RESET MSM_BOOT_UART_DM_CR_CH_CMD(C)
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#define MSM_BOOT_UART_DM_CMD_SET_RFR_N MSM_BOOT_UART_DM_CR_CH_CMD(D)
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#define MSM_BOOT_UART_DM_CMD_RES_RFR_N MSM_BOOT_UART_DM_CR_CH_CMD(E)
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#define MSM_BOOT_UART_DM_CMD_RES_TX_ERR MSM_BOOT_UART_DM_CR_CH_CMD(10)
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#define MSM_BOOT_UART_DM_CMD_CLR_TX_DONE MSM_BOOT_UART_DM_CR_CH_CMD(11)
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#define MSM_BOOT_UART_DM_CMD_RES_BRKSTRT_INT MSM_BOOT_UART_DM_CR_CH_CMD(12)
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#define MSM_BOOT_UART_DM_CMD_RES_BRKEND_INT MSM_BOOT_UART_DM_CR_CH_CMD(13)
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#define MSM_BOOT_UART_DM_CMD_RES_PER_FRM_INT MSM_BOOT_UART_DM_CR_CH_CMD(14)
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/*UART General Command */
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#define MSM_BOOT_UART_DM_CR_GENERAL_CMD(x) ((x) << 8)
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#define MSM_BOOT_UART_DM_GCMD_NULL MSM_BOOT_UART_DM_CR_GENERAL_CMD(0)
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#define MSM_BOOT_UART_DM_GCMD_CR_PROT_EN MSM_BOOT_UART_DM_CR_GENERAL_CMD(1)
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#define MSM_BOOT_UART_DM_GCMD_CR_PROT_DIS MSM_BOOT_UART_DM_CR_GENERAL_CMD(2)
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#define MSM_BOOT_UART_DM_GCMD_RES_TX_RDY_INT MSM_BOOT_UART_DM_CR_GENERAL_CMD(3)
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#define MSM_BOOT_UART_DM_GCMD_SW_FORCE_STALE MSM_BOOT_UART_DM_CR_GENERAL_CMD(4)
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#define MSM_BOOT_UART_DM_GCMD_ENA_STALE_EVT MSM_BOOT_UART_DM_CR_GENERAL_CMD(5)
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#define MSM_BOOT_UART_DM_GCMD_DIS_STALE_EVT MSM_BOOT_UART_DM_CR_GENERAL_CMD(6)
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/* UART Interrupt Mask Register */
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#define MSM_BOOT_UART_DM_IMR MSM_BOOT_UART_DM_REG(0x0014)
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#define MSM_BOOT_UART_DM_TXLEV (1 << 0)
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#define MSM_BOOT_UART_DM_RXHUNT (1 << 1)
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#define MSM_BOOT_UART_DM_RXBRK_CHNG (1 << 2)
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#define MSM_BOOT_UART_DM_RXSTALE (1 << 3)
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#define MSM_BOOT_UART_DM_RXLEV (1 << 4)
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#define MSM_BOOT_UART_DM_DELTA_CTS (1 << 5)
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#define MSM_BOOT_UART_DM_CURRENT_CTS (1 << 6)
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#define MSM_BOOT_UART_DM_TX_READY (1 << 7)
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#define MSM_BOOT_UART_DM_TX_ERROR (1 << 8)
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#define MSM_BOOT_UART_DM_TX_DONE (1 << 9)
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#define MSM_BOOT_UART_DM_RXBREAK_START (1 << 10)
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#define MSM_BOOT_UART_DM_RXBREAK_END (1 << 11)
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#define MSM_BOOT_UART_DM_PAR_FRAME_ERR_IRQ (1 << 12)
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#define MSM_BOOT_UART_DM_IMR_ENABLED (MSM_BOOT_UART_DM_TX_READY | \
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MSM_BOOT_UART_DM_TXLEV | \
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MSM_BOOT_UART_DM_RXLEV | \
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MSM_BOOT_UART_DM_RXSTALE)
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/* UART Interrupt Programming Register */
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#define MSM_BOOT_UART_DM_IPR MSM_BOOT_UART_DM_REG(0x0018)
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#define MSM_BOOT_UART_DM_STALE_TIMEOUT_LSB 0x0f
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#define MSM_BOOT_UART_DM_STALE_TIMEOUT_MSB 0 /* Not used currently */
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/* UART Transmit/Receive FIFO Watermark Register */
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#define MSM_BOOT_UART_DM_TFWR MSM_BOOT_UART_DM_REG(0x001C)
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/* Interrupt is generated when FIFO level is less than or equal to this value */
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#define MSM_BOOT_UART_DM_TFW_VALUE 0
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#define MSM_BOOT_UART_DM_RFWR MSM_BOOT_UART_DM_REG(0x0020)
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/*Interrupt generated when no of words in RX FIFO is greater than this value */
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#define MSM_BOOT_UART_DM_RFW_VALUE 0
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/* UART Hunt Character Register */
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#define MSM_BOOT_UART_DM_HCR MSM_BOOT_UART_DM_REG(0x0024)
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/* Used for RX transfer initialization */
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#define MSM_BOOT_UART_DM_DMRX MSM_BOOT_UART_DM_REG(0x0034)
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/* Default DMRX value - any value bigger than FIFO size would be fine */
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#define MSM_BOOT_UART_DM_DMRX_DEF_VALUE 0x220
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/* Register to enable IRDA function */
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#define MSM_BOOT_UART_DM_IRDA MSM_BOOT_UART_DM_REG(0x0038)
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/* UART Data Mover Enable Register */
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#define MSM_BOOT_UART_DM_DMEN MSM_BOOT_UART_DM_REG(0x003C)
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/* Number of characters for Transmission */
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#define MSM_BOOT_UART_DM_NO_CHARS_FOR_TX MSM_BOOT_UART_DM_REG(0x0040)
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/* UART RX FIFO Base Address */
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#define MSM_BOOT_UART_DM_BADR MSM_BOOT_UART_DM_REG(0x0044)
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/* UART Status Register */
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#define MSM_BOOT_UART_DM_SR MSM_BOOT_UART_DM_REG(0x0008)
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#define MSM_BOOT_UART_DM_SR_RXRDY (1 << 0)
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#define MSM_BOOT_UART_DM_SR_RXFULL (1 << 1)
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#define MSM_BOOT_UART_DM_SR_TXRDY (1 << 2)
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#define MSM_BOOT_UART_DM_SR_TXEMT (1 << 3)
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#define MSM_BOOT_UART_DM_SR_UART_OVERRUN (1 << 4)
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#define MSM_BOOT_UART_DM_SR_PAR_FRAME_ERR (1 << 5)
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#define MSM_BOOT_UART_DM_RX_BREAK (1 << 6)
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#define MSM_BOOT_UART_DM_HUNT_CHAR (1 << 7)
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#define MSM_BOOT_UART_DM_RX_BRK_START_LAST (1 << 8)
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/* UART Receive FIFO Registers - 4 in numbers */
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#define MSM_BOOT_UART_DM_RF(x) MSM_BOOT_UART_DM_REG(0x0070+(4*x))
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/* UART Masked Interrupt Status Register */
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#define MSM_BOOT_UART_DM_MISR MSM_BOOT_UART_DM_REG(0x0010)
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/* UART Interrupt Status Register */
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#define MSM_BOOT_UART_DM_ISR MSM_BOOT_UART_DM_REG(0x0014)
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/* Number of characters received since the end of last RX transfer */
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#define MSM_BOOT_UART_DM_RX_TOTAL_SNAP MSM_BOOT_UART_DM_REG(0x0038)
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/* UART TX FIFO Status Register */
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#define MSM_BOOT_UART_DM_TXFS MSM_BOOT_UART_DM_REG(0x004C)
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#define MSM_BOOT_UART_DM_TXFS_STATE_LSB(x) MSM_BOOT_UART_DM_EXTR_BITS(x,0,6)
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#define MSM_BOOT_UART_DM_TXFS_STATE_MSB(x) MSM_BOOT_UART_DM_EXTR_BITS(x,14,31)
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#define MSM_BOOT_UART_DM_TXFS_BUF_STATE(x) MSM_BOOT_UART_DM_EXTR_BITS(x,7,9)
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#define MSM_BOOT_UART_DM_TXFS_ASYNC_STATE(x) MSM_BOOT_UART_DM_EXTR_BITS(x,10,13)
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/* UART RX FIFO Status Register */
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#define MSM_BOOT_UART_DM_RXFS MSM_BOOT_UART_DM_REG(0x0050)
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#define MSM_BOOT_UART_DM_RXFS_STATE_LSB(x) MSM_BOOT_UART_DM_EXTR_BITS(x,0,6)
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#define MSM_BOOT_UART_DM_RXFS_STATE_MSB(x) MSM_BOOT_UART_DM_EXTR_BITS(x,14,31)
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#define MSM_BOOT_UART_DM_RXFS_BUF_STATE(x) MSM_BOOT_UART_DM_EXTR_BITS(x,7,9)
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#define MSM_BOOT_UART_DM_RXFS_ASYNC_STATE(x) MSM_BOOT_UART_DM_EXTR_BITS(x,10,13)
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/* Macros for Common Errors */
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#define MSM_BOOT_UART_DM_E_SUCCESS 0
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#define MSM_BOOT_UART_DM_E_FAILURE 1
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#define MSM_BOOT_UART_DM_E_TIMEOUT 2
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#define MSM_BOOT_UART_DM_E_INVAL 3
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#define MSM_BOOT_UART_DM_E_MALLOC_FAIL 4
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#define MSM_BOOT_UART_DM_E_RX_NOT_READY 5
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#endif /* __UART_DM_H__*/
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