255 lines
10 KiB
C
255 lines
10 KiB
C
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/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of Code Aurora Forum, Inc. nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __I2C_QUP__
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#define __I2C_QUP__
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/**
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* struct i2c_msg - an I2C transaction segment beginning with START
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* @addr: Slave address, either seven or ten bits. When this is a ten
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* bit address, I2C_M_TEN must be set in @flags and the adapter
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* must support I2C_FUNC_10BIT_ADDR.
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* @flags: I2C_M_RD is handled by all adapters. No other flags may be
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* provided unless the adapter exported the relevant I2C_FUNC_*
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* flags through i2c_check_functionality().
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* @len: Number of data bytes in @buf being read from or written to the
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* I2C slave address. For read transactions where I2C_M_RECV_LEN
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* is set, the caller guarantees that this buffer can hold up to
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* 32 bytes in addition to the initial length byte sent by the
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* slave (plus, if used, the SMBus PEC); and this value will be
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* incremented by the number of block data bytes received.
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* @buf: The buffer into which data is read, or from which it's written.
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*
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* An i2c_msg is the low level representation of one segment of an I2C
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* transaction. It is visible to drivers in the @i2c_transfer() procedure,
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* to userspace from i2c-dev, and to I2C adapter drivers through the
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* @i2c_adapter.@master_xfer() method.
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*
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* Except when I2C "protocol mangling" is used, all I2C adapters implement
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* the standard rules for I2C transactions. Each transaction begins with a
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* START. That is followed by the slave address, and a bit encoding read
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* versus write. Then follow all the data bytes, possibly including a byte
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* with SMBus PEC. The transfer terminates with a NAK, or when all those
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* bytes have been transferred and ACKed. If this is the last message in a
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* group, it is followed by a STOP. Otherwise it is followed by the next
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* @i2c_msg transaction segment, beginning with a (repeated) START.
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*
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* Alternatively, when the adapter supports I2C_FUNC_PROTOCOL_MANGLING then
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* passing certain @flags may have changed those standard protocol behaviors.
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* Those flags are only for use with broken/nonconforming slaves, and with
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* adapters which are known to support the specific mangling options they
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* need (one or more of IGNORE_NAK, NO_RD_ACK, NOSTART, and REV_DIR_ADDR).
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*/
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struct i2c_msg {
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unsigned short addr; /* slave address */
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unsigned short flags;
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#define I2C_M_TEN 0x0010 /* this is a ten bit chip address */
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#define I2C_M_WR 0x0000 /* write data, from master to slave */
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#define I2C_M_RD 0x0001 /* read data, from slave to master */
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#define I2C_M_NOSTART 0x4000 /* if I2C_FUNC_PROTOCOL_MANGLING */
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#define I2C_M_REV_DIR_ADDR 0x2000 /* if I2C_FUNC_PROTOCOL_MANGLING */
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#define I2C_M_IGNORE_NAK 0x1000 /* if I2C_FUNC_PROTOCOL_MANGLING */
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#define I2C_M_NO_RD_ACK 0x0800 /* if I2C_FUNC_PROTOCOL_MANGLING */
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#define I2C_M_RECV_LEN 0x0400 /* length will be first received byte */
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unsigned short len; /* msg length */
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unsigned char *buf; /* pointer to msg data */
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};
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struct qup_i2c_dev {
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unsigned int base;
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unsigned int gsbi_number;
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int qup_irq;
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int num_irqs;
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struct i2c_msg *msg;
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int pos;
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int cnt;
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int err;
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int mode;
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int clk_ctl;
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int clk_freq;
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int src_clk_freq;
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int one_bit_t;
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int out_fifo_sz;
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int in_fifo_sz;
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int out_blk_sz;
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int in_blk_sz;
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int wr_sz;
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int suspended;
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int clk_state;
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};
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/* Function Definitions */
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struct qup_i2c_dev *qup_i2c_init(unsigned base,
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unsigned clk_freq, unsigned src_clk_freq);
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int qup_i2c_deinit(struct qup_i2c_dev *dev);
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int qup_i2c_xfer(struct qup_i2c_dev *dev, struct i2c_msg msgs[], int num);
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struct device {
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struct device *parent;
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const char *init_name; /* initial name of the device */
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void (*release) (struct device * dev);
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};
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/**
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* enum irqreturn
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* @IRQ_NONE interrupt was not from this device
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* @IRQ_HANDLED interrupt was handled by this device
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* @IRQ_WAKE_THREAD handler requests to wake the handler thread
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*/
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enum irqreturn {
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IRQ_NONE,
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IRQ_HANDLED,
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IRQ_WAKE_THREAD,
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IRQ_FAIL,
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};
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typedef enum irqreturn irqreturn_t;
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#define I2C_SMBUS_BLOCK_MAX 32
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union i2c_smbus_data {
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unsigned char byte;
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unsigned short word;
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unsigned char block[I2C_SMBUS_BLOCK_MAX + 2];
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};
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/*
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* i2c_adapter is the structure used to identify a physical i2c bus along
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* with the access algorithms necessary to access it.
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*/
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struct i2c_adapter {
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struct module *owner;
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unsigned int id;
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unsigned int class; /* classes to allow probing for */
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const struct i2c_algorithm *algo; /* the algorithm to access the bus */
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void *algo_data;
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/* data fields that are valid for all devices */
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unsigned int level; /* nesting level for lockdep */
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int timeout; /* in jiffies */
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int retries;
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struct device dev; /* the adapter device */
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int nr;
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char name[48];
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};
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/*
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* The following structs are for those who like to implement new bus drivers:
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* i2c_algorithm is the interface to a class of hardware solutions which can
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* be addressed using the same bus algorithms - i.e. bit-banging or the PCF8584
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* to name two of the most common.
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*/
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struct i2c_algorithm {
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/* If an adapter algorithm can't do I2C-level access, set master_xfer to
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NULL. If an adapter algorithm can do SMBus access, set smbus_xfer. If
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set to NULL, the SMBus protocol is simulated using common I2C messages */
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/* master_xfer should return the number of messages successfully processed,
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or a negative value on error */
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int (*master_xfer) (struct i2c_adapter * adap, struct i2c_msg * msgs,
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int num);
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int (*smbus_xfer) (struct i2c_adapter * adap, unsigned short addr,
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unsigned short flags, char read_write,
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unsigned char command, int size,
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union i2c_smbus_data * data);
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/* To determine what the adapter supports */
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unsigned int (*functionality) (struct i2c_adapter *);
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};
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#define EIO 5
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#define ENOMEM 12
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#define EBUSY 16
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#define ENODEV 19
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#define ENOSYS 38
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#define EPROTONOSUPPORT 93
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#define ETIMEDOUT 110
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#define FALSE 0
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#define TRUE 1
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#define USEC_PER_SEC 1000000L
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#define IRQF_TRIGGER_NONE 0x00000000
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#define IRQF_TRIGGER_RISING 0x00000001
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#define IRQF_TRIGGER_FALLING 0x00000002
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#define IRQF_TRIGGER_HIGH 0x00000004
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#define IRQF_TRIGGER_LOW 0x00000008
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#define IRQF_TRIGGER_MASK (IRQF_TRIGGER_HIGH | IRQF_TRIGGER_LOW | \
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IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)
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#define IRQF_TRIGGER_PROBE 0x00000010
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/* To determine what functionality is present */
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#define I2C_FUNC_I2C 0x00000001
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#define I2C_FUNC_10BIT_ADDR 0x00000002
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#define I2C_FUNC_PROTOCOL_MANGLING 0x00000004 /* I2C_M_NOSTART etc. */
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#define I2C_FUNC_SMBUS_PEC 0x00000008
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#define I2C_FUNC_SMBUS_BLOCK_PROC_CALL 0x00008000 /* SMBus 2.0 */
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#define I2C_FUNC_SMBUS_QUICK 0x00010000
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#define I2C_FUNC_SMBUS_READ_BYTE 0x00020000
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#define I2C_FUNC_SMBUS_WRITE_BYTE 0x00040000
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#define I2C_FUNC_SMBUS_READ_BYTE_DATA 0x00080000
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#define I2C_FUNC_SMBUS_WRITE_BYTE_DATA 0x00100000
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#define I2C_FUNC_SMBUS_READ_WORD_DATA 0x00200000
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#define I2C_FUNC_SMBUS_WRITE_WORD_DATA 0x00400000
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#define I2C_FUNC_SMBUS_PROC_CALL 0x00800000
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#define I2C_FUNC_SMBUS_READ_BLOCK_DATA 0x01000000
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#define I2C_FUNC_SMBUS_WRITE_BLOCK_DATA 0x02000000
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#define I2C_FUNC_SMBUS_READ_I2C_BLOCK 0x04000000 /* I2C-like block xfer */
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#define I2C_FUNC_SMBUS_WRITE_I2C_BLOCK 0x08000000 /* w/ 1-byte reg. addr. */
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#define I2C_FUNC_SMBUS_BYTE (I2C_FUNC_SMBUS_READ_BYTE | \
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I2C_FUNC_SMBUS_WRITE_BYTE)
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#define I2C_FUNC_SMBUS_BYTE_DATA (I2C_FUNC_SMBUS_READ_BYTE_DATA | \
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I2C_FUNC_SMBUS_WRITE_BYTE_DATA)
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#define I2C_FUNC_SMBUS_WORD_DATA (I2C_FUNC_SMBUS_READ_WORD_DATA | \
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I2C_FUNC_SMBUS_WRITE_WORD_DATA)
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#define I2C_FUNC_SMBUS_BLOCK_DATA (I2C_FUNC_SMBUS_READ_BLOCK_DATA | \
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I2C_FUNC_SMBUS_WRITE_BLOCK_DATA)
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#define I2C_FUNC_SMBUS_I2C_BLOCK (I2C_FUNC_SMBUS_READ_I2C_BLOCK | \
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I2C_FUNC_SMBUS_WRITE_I2C_BLOCK)
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#define I2C_FUNC_SMBUS_EMUL (I2C_FUNC_SMBUS_QUICK | \
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I2C_FUNC_SMBUS_BYTE | \
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I2C_FUNC_SMBUS_BYTE_DATA | \
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I2C_FUNC_SMBUS_WORD_DATA | \
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I2C_FUNC_SMBUS_PROC_CALL | \
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I2C_FUNC_SMBUS_WRITE_BLOCK_DATA | \
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I2C_FUNC_SMBUS_I2C_BLOCK | \
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I2C_FUNC_SMBUS_PEC)
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/* GSBI/I2C QUP APPS CLK definitions */
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#define I2C_APPS_CLK_MD_24MHz 0x000100FB
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#define I2C_APPS_CLK_NS_24MHz 0x00FC005B
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#define GSBI8_HCLK_CTL_S (4)
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#define GSBI8_HCLK_CTL_CLK_ENA (0x1)
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#define GSBI_CTRL_REG_PROTOCOL_CODE_S (4)
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#define GSBI_PROTOCOL_CODE_I2C (0x2)
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#endif /* __I2C_QUP__ */
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