94 lines
4.9 KiB
C
94 lines
4.9 KiB
C
/* Copyright (c) 2002,2007-2011, Code Aurora Forum. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of Code Aurora Forum, Inc. nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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#ifndef __Z80_REG_H
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#define __Z80_REG_H
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#define REG_VGC_IRQSTATUS__MH_MASK 0x00000001L
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#define REG_VGC_IRQSTATUS__G2D_MASK 0x00000002L
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#define REG_VGC_IRQSTATUS__FIFO_MASK 0x00000004L
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#define MH_ARBITER_CONFIG__SAME_PAGE_GRANULARITY__SHIFT 0x00000006
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#define MH_ARBITER_CONFIG__L1_ARB_ENABLE__SHIFT 0x00000007
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#define MH_ARBITER_CONFIG__L1_ARB_HOLD_ENABLE__SHIFT 0x00000008
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#define MH_ARBITER_CONFIG__L2_ARB_CONTROL__SHIFT 0x00000009
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#define MH_ARBITER_CONFIG__PAGE_SIZE__SHIFT 0x0000000a
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#define MH_ARBITER_CONFIG__TC_REORDER_ENABLE__SHIFT 0x0000000d
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#define MH_ARBITER_CONFIG__TC_ARB_HOLD_ENABLE__SHIFT 0x0000000e
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#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT_ENABLE__SHIFT 0x0000000f
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#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT__SHIFT 0x00000010
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#define MH_ARBITER_CONFIG__CP_CLNT_ENABLE__SHIFT 0x00000016
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#define MH_ARBITER_CONFIG__VGT_CLNT_ENABLE__SHIFT 0x00000017
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#define MH_ARBITER_CONFIG__TC_CLNT_ENABLE__SHIFT 0x00000018
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#define MH_ARBITER_CONFIG__RB_CLNT_ENABLE__SHIFT 0x00000019
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#define MH_ARBITER_CONFIG__PA_CLNT_ENABLE__SHIFT 0x0000001a
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#define MH_MMU_CONFIG__RB_W_CLNT_BEHAVIOR__SHIFT 0x00000004
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#define MH_MMU_CONFIG__CP_W_CLNT_BEHAVIOR__SHIFT 0x00000006
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#define MH_MMU_CONFIG__CP_R0_CLNT_BEHAVIOR__SHIFT 0x00000008
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#define MH_MMU_CONFIG__CP_R1_CLNT_BEHAVIOR__SHIFT 0x0000000a
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#define MH_MMU_CONFIG__CP_R2_CLNT_BEHAVIOR__SHIFT 0x0000000c
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#define MH_MMU_CONFIG__CP_R3_CLNT_BEHAVIOR__SHIFT 0x0000000e
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#define MH_MMU_CONFIG__CP_R4_CLNT_BEHAVIOR__SHIFT 0x00000010
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#define MH_MMU_CONFIG__VGT_R0_CLNT_BEHAVIOR__SHIFT 0x00000012
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#define MH_MMU_CONFIG__VGT_R1_CLNT_BEHAVIOR__SHIFT 0x00000014
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#define MH_MMU_CONFIG__TC_R_CLNT_BEHAVIOR__SHIFT 0x00000016
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#define MH_MMU_CONFIG__PA_W_CLNT_BEHAVIOR__SHIFT 0x00000018
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#define ADDR_MH_ARBITER_CONFIG 0x0A40
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#define ADDR_MH_INTERRUPT_CLEAR 0x0A44
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#define ADDR_MH_INTERRUPT_MASK 0x0A42
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#define ADDR_MH_INTERRUPT_STATUS 0x0A43
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#define ADDR_MH_AXI_ERROR 0x0A45
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#define ADDR_MH_AXI_HALT_CONTROL 0x0A50
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#define ADDR_MH_CLNT_INTF_CTRL_CONFIG1 0x0A54
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#define ADDR_MH_CLNT_INTF_CTRL_CONFIG2 0x0A55
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#define ADDR_MH_MMU_CONFIG 0x0040
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#define ADDR_MH_MMU_INVALIDATE 0x0045
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#define ADDR_MH_MMU_MPU_BASE 0x0046
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#define ADDR_MH_MMU_MPU_END 0x0047
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#define ADDR_MH_MMU_PT_BASE 0x0042
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#define ADDR_MH_MMU_TRAN_ERROR 0x0044
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#define ADDR_MH_MMU_VA_RANGE 0x0041
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#define ADDR_VGC_MH_READ_ADDR 0x0510
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#define ADDR_VGC_MH_DATA_ADDR 0x0518
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#define ADDR_MH_MMU_PAGE_FAULT 0x0043
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#define ADDR_VGC_COMMANDSTREAM 0x0000
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#define ADDR_VGC_IRQENABLE 0x0438
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#define ADDR_VGC_IRQSTATUS 0x0418
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#define ADDR_VGC_IRQ_ACTIVE_CNT 0x04E0
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#define ADDR_VGC_MMUCOMMANDSTREAM 0x03FC
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#define ADDR_VGV3_CONTROL 0x0070
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#define ADDR_VGV3_LAST 0x007F
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#define ADDR_VGV3_MODE 0x0071
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#define ADDR_VGV3_NEXTADDR 0x0075
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#define ADDR_VGV3_NEXTCMD 0x0076
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#define ADDR_VGV3_WRITEADDR 0x0072
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#endif /* __Z180_REG_H */
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