568 lines
14 KiB
C
568 lines
14 KiB
C
/*
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* arch/arm/mach-ixp4xx/include/mach/io.h
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*
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* Author: Deepak Saxena <dsaxena@plexity.net>
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*
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* Copyright (C) 2002-2005 MontaVista Software, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARM_ARCH_IO_H
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#define __ASM_ARM_ARCH_IO_H
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#include <linux/bitops.h>
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#include <mach/hardware.h>
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#define IO_SPACE_LIMIT 0x0000ffff
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extern int (*ixp4xx_pci_read)(u32 addr, u32 cmd, u32* data);
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extern int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data);
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/*
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* IXP4xx provides two methods of accessing PCI memory space:
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*
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* 1) A direct mapped window from 0x48000000 to 0x4bffffff (64MB).
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* To access PCI via this space, we simply ioremap() the BAR
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* into the kernel and we can use the standard read[bwl]/write[bwl]
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* macros. This is the preffered method due to speed but it
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* limits the system to just 64MB of PCI memory. This can be
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* problamatic if using video cards and other memory-heavy
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* targets.
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*
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* 2) If > 64MB of memory space is required, the IXP4xx can be configured
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* to use indirect registers to access PCI (as we do below for I/O
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* transactions). This allows for up to 128MB (0x48000000 to 0x4fffffff)
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* of memory on the bus. The disadvantage of this is that every
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* PCI access requires three local register accesses plus a spinlock,
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* but in some cases the performance hit is acceptable. In addition,
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* you cannot mmap() PCI devices in this case.
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*
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*/
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#ifndef CONFIG_IXP4XX_INDIRECT_PCI
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#define __mem_pci(a) (a)
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#else
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/*
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* In the case of using indirect PCI, we simply return the actual PCI
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* address and our read/write implementation use that to drive the
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* access registers. If something outside of PCI is ioremap'd, we
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* fallback to the default.
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*/
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static inline void __iomem *
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__ixp4xx_ioremap(unsigned long addr, size_t size, unsigned int mtype)
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{
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if((addr < PCIBIOS_MIN_MEM) || (addr > 0x4fffffff))
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return __arm_ioremap(addr, size, mtype);
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return (void __iomem *)addr;
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}
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static inline void
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__ixp4xx_iounmap(void __iomem *addr)
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{
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if ((__force u32)addr >= VMALLOC_START)
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__iounmap(addr);
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}
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#define __arch_ioremap(a, s, f) __ixp4xx_ioremap(a, s, f)
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#define __arch_iounmap(a) __ixp4xx_iounmap(a)
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#define writeb(v, p) __ixp4xx_writeb(v, p)
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#define writew(v, p) __ixp4xx_writew(v, p)
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#define writel(v, p) __ixp4xx_writel(v, p)
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#define writesb(p, v, l) __ixp4xx_writesb(p, v, l)
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#define writesw(p, v, l) __ixp4xx_writesw(p, v, l)
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#define writesl(p, v, l) __ixp4xx_writesl(p, v, l)
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#define readb(p) __ixp4xx_readb(p)
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#define readw(p) __ixp4xx_readw(p)
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#define readl(p) __ixp4xx_readl(p)
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#define readsb(p, v, l) __ixp4xx_readsb(p, v, l)
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#define readsw(p, v, l) __ixp4xx_readsw(p, v, l)
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#define readsl(p, v, l) __ixp4xx_readsl(p, v, l)
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static inline void
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__ixp4xx_writeb(u8 value, volatile void __iomem *p)
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{
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u32 addr = (u32)p;
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u32 n, byte_enables, data;
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if (addr >= VMALLOC_START) {
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__raw_writeb(value, addr);
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return;
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}
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n = addr % 4;
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byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL;
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data = value << (8*n);
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ixp4xx_pci_write(addr, byte_enables | NP_CMD_MEMWRITE, data);
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}
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static inline void
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__ixp4xx_writesb(volatile void __iomem *bus_addr, const u8 *vaddr, int count)
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{
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while (count--)
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writeb(*vaddr++, bus_addr);
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}
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static inline void
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__ixp4xx_writew(u16 value, volatile void __iomem *p)
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{
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u32 addr = (u32)p;
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u32 n, byte_enables, data;
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if (addr >= VMALLOC_START) {
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__raw_writew(value, addr);
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return;
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}
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n = addr % 4;
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byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL;
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data = value << (8*n);
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ixp4xx_pci_write(addr, byte_enables | NP_CMD_MEMWRITE, data);
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}
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static inline void
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__ixp4xx_writesw(volatile void __iomem *bus_addr, const u16 *vaddr, int count)
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{
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while (count--)
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writew(*vaddr++, bus_addr);
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}
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static inline void
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__ixp4xx_writel(u32 value, volatile void __iomem *p)
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{
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u32 addr = (__force u32)p;
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if (addr >= VMALLOC_START) {
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__raw_writel(value, p);
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return;
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}
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ixp4xx_pci_write(addr, NP_CMD_MEMWRITE, value);
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}
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static inline void
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__ixp4xx_writesl(volatile void __iomem *bus_addr, const u32 *vaddr, int count)
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{
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while (count--)
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writel(*vaddr++, bus_addr);
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}
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static inline unsigned char
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__ixp4xx_readb(const volatile void __iomem *p)
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{
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u32 addr = (u32)p;
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u32 n, byte_enables, data;
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if (addr >= VMALLOC_START)
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return __raw_readb(addr);
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n = addr % 4;
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byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL;
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if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_MEMREAD, &data))
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return 0xff;
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return data >> (8*n);
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}
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static inline void
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__ixp4xx_readsb(const volatile void __iomem *bus_addr, u8 *vaddr, u32 count)
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{
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while (count--)
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*vaddr++ = readb(bus_addr);
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}
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static inline unsigned short
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__ixp4xx_readw(const volatile void __iomem *p)
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{
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u32 addr = (u32)p;
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u32 n, byte_enables, data;
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if (addr >= VMALLOC_START)
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return __raw_readw(addr);
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n = addr % 4;
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byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL;
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if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_MEMREAD, &data))
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return 0xffff;
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return data>>(8*n);
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}
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static inline void
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__ixp4xx_readsw(const volatile void __iomem *bus_addr, u16 *vaddr, u32 count)
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{
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while (count--)
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*vaddr++ = readw(bus_addr);
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}
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static inline unsigned long
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__ixp4xx_readl(const volatile void __iomem *p)
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{
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u32 addr = (__force u32)p;
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u32 data;
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if (addr >= VMALLOC_START)
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return __raw_readl(p);
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if (ixp4xx_pci_read(addr, NP_CMD_MEMREAD, &data))
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return 0xffffffff;
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return data;
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}
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static inline void
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__ixp4xx_readsl(const volatile void __iomem *bus_addr, u32 *vaddr, u32 count)
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{
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while (count--)
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*vaddr++ = readl(bus_addr);
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}
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/*
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* We can use the built-in functions b/c they end up calling writeb/readb
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*/
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#define memset_io(c,v,l) _memset_io((c),(v),(l))
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#define memcpy_fromio(a,c,l) _memcpy_fromio((a),(c),(l))
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#define memcpy_toio(c,a,l) _memcpy_toio((c),(a),(l))
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#endif
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#ifndef CONFIG_PCI
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#define __io(v) __typesafe_io(v)
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#else
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/*
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* IXP4xx does not have a transparent cpu -> PCI I/O translation
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* window. Instead, it has a set of registers that must be tweaked
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* with the proper byte lanes, command types, and address for the
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* transaction. This means that we need to override the default
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* I/O functions.
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*/
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#define outb(p, v) __ixp4xx_outb(p, v)
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#define outw(p, v) __ixp4xx_outw(p, v)
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#define outl(p, v) __ixp4xx_outl(p, v)
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#define outsb(p, v, l) __ixp4xx_outsb(p, v, l)
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#define outsw(p, v, l) __ixp4xx_outsw(p, v, l)
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#define outsl(p, v, l) __ixp4xx_outsl(p, v, l)
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#define inb(p) __ixp4xx_inb(p)
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#define inw(p) __ixp4xx_inw(p)
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#define inl(p) __ixp4xx_inl(p)
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#define insb(p, v, l) __ixp4xx_insb(p, v, l)
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#define insw(p, v, l) __ixp4xx_insw(p, v, l)
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#define insl(p, v, l) __ixp4xx_insl(p, v, l)
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static inline void
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__ixp4xx_outb(u8 value, u32 addr)
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{
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u32 n, byte_enables, data;
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n = addr % 4;
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byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL;
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data = value << (8*n);
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ixp4xx_pci_write(addr, byte_enables | NP_CMD_IOWRITE, data);
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}
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static inline void
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__ixp4xx_outsb(u32 io_addr, const u8 *vaddr, u32 count)
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{
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while (count--)
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outb(*vaddr++, io_addr);
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}
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static inline void
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__ixp4xx_outw(u16 value, u32 addr)
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{
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u32 n, byte_enables, data;
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n = addr % 4;
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byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL;
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data = value << (8*n);
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ixp4xx_pci_write(addr, byte_enables | NP_CMD_IOWRITE, data);
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}
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static inline void
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__ixp4xx_outsw(u32 io_addr, const u16 *vaddr, u32 count)
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{
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while (count--)
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outw(cpu_to_le16(*vaddr++), io_addr);
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}
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static inline void
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__ixp4xx_outl(u32 value, u32 addr)
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{
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ixp4xx_pci_write(addr, NP_CMD_IOWRITE, value);
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}
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static inline void
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__ixp4xx_outsl(u32 io_addr, const u32 *vaddr, u32 count)
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{
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while (count--)
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outl(*vaddr++, io_addr);
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}
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static inline u8
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__ixp4xx_inb(u32 addr)
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{
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u32 n, byte_enables, data;
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n = addr % 4;
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byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL;
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if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_IOREAD, &data))
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return 0xff;
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return data >> (8*n);
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}
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static inline void
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__ixp4xx_insb(u32 io_addr, u8 *vaddr, u32 count)
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{
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while (count--)
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*vaddr++ = inb(io_addr);
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}
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static inline u16
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__ixp4xx_inw(u32 addr)
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{
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u32 n, byte_enables, data;
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n = addr % 4;
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byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL;
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if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_IOREAD, &data))
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return 0xffff;
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return data>>(8*n);
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}
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static inline void
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__ixp4xx_insw(u32 io_addr, u16 *vaddr, u32 count)
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{
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while (count--)
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*vaddr++ = le16_to_cpu(inw(io_addr));
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}
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static inline u32
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__ixp4xx_inl(u32 addr)
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{
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u32 data;
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if (ixp4xx_pci_read(addr, NP_CMD_IOREAD, &data))
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return 0xffffffff;
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return data;
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}
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static inline void
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__ixp4xx_insl(u32 io_addr, u32 *vaddr, u32 count)
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{
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while (count--)
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*vaddr++ = inl(io_addr);
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}
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#define PIO_OFFSET 0x10000UL
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#define PIO_MASK 0x0ffffUL
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#define __is_io_address(p) (((unsigned long)p >= PIO_OFFSET) && \
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((unsigned long)p <= (PIO_MASK + PIO_OFFSET)))
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static inline unsigned int
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__ixp4xx_ioread8(const void __iomem *addr)
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{
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unsigned long port = (unsigned long __force)addr;
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if (__is_io_address(port))
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return (unsigned int)__ixp4xx_inb(port & PIO_MASK);
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else
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#ifndef CONFIG_IXP4XX_INDIRECT_PCI
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return (unsigned int)__raw_readb(port);
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#else
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return (unsigned int)__ixp4xx_readb(addr);
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#endif
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}
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static inline void
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__ixp4xx_ioread8_rep(const void __iomem *addr, void *vaddr, u32 count)
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{
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unsigned long port = (unsigned long __force)addr;
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if (__is_io_address(port))
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__ixp4xx_insb(port & PIO_MASK, vaddr, count);
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else
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#ifndef CONFIG_IXP4XX_INDIRECT_PCI
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__raw_readsb(addr, vaddr, count);
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#else
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__ixp4xx_readsb(addr, vaddr, count);
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#endif
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}
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static inline unsigned int
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__ixp4xx_ioread16(const void __iomem *addr)
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{
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unsigned long port = (unsigned long __force)addr;
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if (__is_io_address(port))
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return (unsigned int)__ixp4xx_inw(port & PIO_MASK);
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else
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#ifndef CONFIG_IXP4XX_INDIRECT_PCI
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return le16_to_cpu(__raw_readw((u32)port));
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#else
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return (unsigned int)__ixp4xx_readw(addr);
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#endif
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}
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static inline void
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__ixp4xx_ioread16_rep(const void __iomem *addr, void *vaddr, u32 count)
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{
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unsigned long port = (unsigned long __force)addr;
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if (__is_io_address(port))
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__ixp4xx_insw(port & PIO_MASK, vaddr, count);
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else
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#ifndef CONFIG_IXP4XX_INDIRECT_PCI
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__raw_readsw(addr, vaddr, count);
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#else
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__ixp4xx_readsw(addr, vaddr, count);
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#endif
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}
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static inline unsigned int
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__ixp4xx_ioread32(const void __iomem *addr)
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{
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unsigned long port = (unsigned long __force)addr;
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if (__is_io_address(port))
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return (unsigned int)__ixp4xx_inl(port & PIO_MASK);
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else {
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#ifndef CONFIG_IXP4XX_INDIRECT_PCI
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return le32_to_cpu((__force __le32)__raw_readl(addr));
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#else
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return (unsigned int)__ixp4xx_readl(addr);
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#endif
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}
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}
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static inline void
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__ixp4xx_ioread32_rep(const void __iomem *addr, void *vaddr, u32 count)
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{
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unsigned long port = (unsigned long __force)addr;
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if (__is_io_address(port))
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__ixp4xx_insl(port & PIO_MASK, vaddr, count);
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else
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#ifndef CONFIG_IXP4XX_INDIRECT_PCI
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__raw_readsl(addr, vaddr, count);
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#else
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__ixp4xx_readsl(addr, vaddr, count);
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#endif
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}
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static inline void
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__ixp4xx_iowrite8(u8 value, void __iomem *addr)
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{
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unsigned long port = (unsigned long __force)addr;
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if (__is_io_address(port))
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__ixp4xx_outb(value, port & PIO_MASK);
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else
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#ifndef CONFIG_IXP4XX_INDIRECT_PCI
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__raw_writeb(value, port);
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#else
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__ixp4xx_writeb(value, addr);
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#endif
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}
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static inline void
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__ixp4xx_iowrite8_rep(void __iomem *addr, const void *vaddr, u32 count)
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{
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unsigned long port = (unsigned long __force)addr;
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if (__is_io_address(port))
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__ixp4xx_outsb(port & PIO_MASK, vaddr, count);
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else
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#ifndef CONFIG_IXP4XX_INDIRECT_PCI
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__raw_writesb(addr, vaddr, count);
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#else
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__ixp4xx_writesb(addr, vaddr, count);
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#endif
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}
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static inline void
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__ixp4xx_iowrite16(u16 value, void __iomem *addr)
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{
|
|
unsigned long port = (unsigned long __force)addr;
|
|
if (__is_io_address(port))
|
|
__ixp4xx_outw(value, port & PIO_MASK);
|
|
else
|
|
#ifndef CONFIG_IXP4XX_INDIRECT_PCI
|
|
__raw_writew(cpu_to_le16(value), addr);
|
|
#else
|
|
__ixp4xx_writew(value, addr);
|
|
#endif
|
|
}
|
|
|
|
static inline void
|
|
__ixp4xx_iowrite16_rep(void __iomem *addr, const void *vaddr, u32 count)
|
|
{
|
|
unsigned long port = (unsigned long __force)addr;
|
|
if (__is_io_address(port))
|
|
__ixp4xx_outsw(port & PIO_MASK, vaddr, count);
|
|
else
|
|
#ifndef CONFIG_IXP4XX_INDIRECT_PCI
|
|
__raw_writesw(addr, vaddr, count);
|
|
#else
|
|
__ixp4xx_writesw(addr, vaddr, count);
|
|
#endif
|
|
}
|
|
|
|
static inline void
|
|
__ixp4xx_iowrite32(u32 value, void __iomem *addr)
|
|
{
|
|
unsigned long port = (unsigned long __force)addr;
|
|
if (__is_io_address(port))
|
|
__ixp4xx_outl(value, port & PIO_MASK);
|
|
else
|
|
#ifndef CONFIG_IXP4XX_INDIRECT_PCI
|
|
__raw_writel((u32 __force)cpu_to_le32(value), addr);
|
|
#else
|
|
__ixp4xx_writel(value, addr);
|
|
#endif
|
|
}
|
|
|
|
static inline void
|
|
__ixp4xx_iowrite32_rep(void __iomem *addr, const void *vaddr, u32 count)
|
|
{
|
|
unsigned long port = (unsigned long __force)addr;
|
|
if (__is_io_address(port))
|
|
__ixp4xx_outsl(port & PIO_MASK, vaddr, count);
|
|
else
|
|
#ifndef CONFIG_IXP4XX_INDIRECT_PCI
|
|
__raw_writesl(addr, vaddr, count);
|
|
#else
|
|
__ixp4xx_writesl(addr, vaddr, count);
|
|
#endif
|
|
}
|
|
|
|
#define ioread8(p) __ixp4xx_ioread8(p)
|
|
#define ioread16(p) __ixp4xx_ioread16(p)
|
|
#define ioread32(p) __ixp4xx_ioread32(p)
|
|
|
|
#define ioread8_rep(p, v, c) __ixp4xx_ioread8_rep(p, v, c)
|
|
#define ioread16_rep(p, v, c) __ixp4xx_ioread16_rep(p, v, c)
|
|
#define ioread32_rep(p, v, c) __ixp4xx_ioread32_rep(p, v, c)
|
|
|
|
#define iowrite8(v,p) __ixp4xx_iowrite8(v,p)
|
|
#define iowrite16(v,p) __ixp4xx_iowrite16(v,p)
|
|
#define iowrite32(v,p) __ixp4xx_iowrite32(v,p)
|
|
|
|
#define iowrite8_rep(p, v, c) __ixp4xx_iowrite8_rep(p, v, c)
|
|
#define iowrite16_rep(p, v, c) __ixp4xx_iowrite16_rep(p, v, c)
|
|
#define iowrite32_rep(p, v, c) __ixp4xx_iowrite32_rep(p, v, c)
|
|
|
|
#define ioport_map(port, nr) ((void __iomem*)(port + PIO_OFFSET))
|
|
#define ioport_unmap(addr)
|
|
#endif // !CONFIG_PCI
|
|
|
|
#endif // __ASM_ARM_ARCH_IO_H
|
|
|