782 lines
20 KiB
C
782 lines
20 KiB
C
/*
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* atmel_ssc_dai.c -- ALSA SoC ATMEL SSC Audio Layer Platform driver
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*
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* Copyright (C) 2005 SAN People
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* Copyright (C) 2008 Atmel
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*
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* Author: Sedji Gaouaou <sedji.gaouaou@atmel.com>
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* ATMEL CORP.
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*
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* Based on at91-ssc.c by
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* Frank Mandarino <fmandarino@endrelia.com>
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* Based on pxa2xx Platform drivers by
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* Liam Girdwood <lrg@slimlogic.co.uk>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/device.h>
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#include <linux/delay.h>
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#include <linux/clk.h>
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#include <linux/atmel_pdc.h>
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#include <linux/atmel-ssc.h>
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#include <sound/core.h>
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#include <sound/pcm.h>
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#include <sound/pcm_params.h>
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#include <sound/initval.h>
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#include <sound/soc.h>
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#include <mach/hardware.h>
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#include "atmel-pcm.h"
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#include "atmel_ssc_dai.h"
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#if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9G20)
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#define NUM_SSC_DEVICES 1
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#else
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#define NUM_SSC_DEVICES 3
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#endif
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/*
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* SSC PDC registers required by the PCM DMA engine.
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*/
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static struct atmel_pdc_regs pdc_tx_reg = {
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.xpr = ATMEL_PDC_TPR,
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.xcr = ATMEL_PDC_TCR,
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.xnpr = ATMEL_PDC_TNPR,
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.xncr = ATMEL_PDC_TNCR,
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};
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static struct atmel_pdc_regs pdc_rx_reg = {
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.xpr = ATMEL_PDC_RPR,
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.xcr = ATMEL_PDC_RCR,
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.xnpr = ATMEL_PDC_RNPR,
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.xncr = ATMEL_PDC_RNCR,
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};
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/*
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* SSC & PDC status bits for transmit and receive.
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*/
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static struct atmel_ssc_mask ssc_tx_mask = {
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.ssc_enable = SSC_BIT(CR_TXEN),
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.ssc_disable = SSC_BIT(CR_TXDIS),
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.ssc_endx = SSC_BIT(SR_ENDTX),
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.ssc_endbuf = SSC_BIT(SR_TXBUFE),
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.pdc_enable = ATMEL_PDC_TXTEN,
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.pdc_disable = ATMEL_PDC_TXTDIS,
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};
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static struct atmel_ssc_mask ssc_rx_mask = {
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.ssc_enable = SSC_BIT(CR_RXEN),
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.ssc_disable = SSC_BIT(CR_RXDIS),
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.ssc_endx = SSC_BIT(SR_ENDRX),
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.ssc_endbuf = SSC_BIT(SR_RXBUFF),
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.pdc_enable = ATMEL_PDC_RXTEN,
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.pdc_disable = ATMEL_PDC_RXTDIS,
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};
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/*
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* DMA parameters.
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*/
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static struct atmel_pcm_dma_params ssc_dma_params[NUM_SSC_DEVICES][2] = {
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{{
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.name = "SSC0 PCM out",
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.pdc = &pdc_tx_reg,
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.mask = &ssc_tx_mask,
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},
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{
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.name = "SSC0 PCM in",
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.pdc = &pdc_rx_reg,
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.mask = &ssc_rx_mask,
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} },
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#if NUM_SSC_DEVICES == 3
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{{
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.name = "SSC1 PCM out",
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.pdc = &pdc_tx_reg,
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.mask = &ssc_tx_mask,
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},
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{
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.name = "SSC1 PCM in",
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.pdc = &pdc_rx_reg,
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.mask = &ssc_rx_mask,
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} },
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{{
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.name = "SSC2 PCM out",
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.pdc = &pdc_tx_reg,
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.mask = &ssc_tx_mask,
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},
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{
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.name = "SSC2 PCM in",
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.pdc = &pdc_rx_reg,
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.mask = &ssc_rx_mask,
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} },
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#endif
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};
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static struct atmel_ssc_info ssc_info[NUM_SSC_DEVICES] = {
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{
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.name = "ssc0",
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.lock = __SPIN_LOCK_UNLOCKED(ssc_info[0].lock),
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.dir_mask = SSC_DIR_MASK_UNUSED,
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.initialized = 0,
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},
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#if NUM_SSC_DEVICES == 3
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{
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.name = "ssc1",
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.lock = __SPIN_LOCK_UNLOCKED(ssc_info[1].lock),
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.dir_mask = SSC_DIR_MASK_UNUSED,
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.initialized = 0,
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},
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{
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.name = "ssc2",
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.lock = __SPIN_LOCK_UNLOCKED(ssc_info[2].lock),
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.dir_mask = SSC_DIR_MASK_UNUSED,
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.initialized = 0,
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},
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#endif
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};
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/*
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* SSC interrupt handler. Passes PDC interrupts to the DMA
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* interrupt handler in the PCM driver.
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*/
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static irqreturn_t atmel_ssc_interrupt(int irq, void *dev_id)
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{
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struct atmel_ssc_info *ssc_p = dev_id;
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struct atmel_pcm_dma_params *dma_params;
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u32 ssc_sr;
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u32 ssc_substream_mask;
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int i;
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ssc_sr = (unsigned long)ssc_readl(ssc_p->ssc->regs, SR)
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& (unsigned long)ssc_readl(ssc_p->ssc->regs, IMR);
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/*
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* Loop through the substreams attached to this SSC. If
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* a DMA-related interrupt occurred on that substream, call
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* the DMA interrupt handler function, if one has been
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* registered in the dma_params structure by the PCM driver.
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*/
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for (i = 0; i < ARRAY_SIZE(ssc_p->dma_params); i++) {
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dma_params = ssc_p->dma_params[i];
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if ((dma_params != NULL) &&
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(dma_params->dma_intr_handler != NULL)) {
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ssc_substream_mask = (dma_params->mask->ssc_endx |
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dma_params->mask->ssc_endbuf);
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if (ssc_sr & ssc_substream_mask) {
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dma_params->dma_intr_handler(ssc_sr,
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dma_params->
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substream);
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}
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}
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}
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return IRQ_HANDLED;
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}
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/*-------------------------------------------------------------------------*\
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* DAI functions
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\*-------------------------------------------------------------------------*/
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/*
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* Startup. Only that one substream allowed in each direction.
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*/
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static int atmel_ssc_startup(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
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struct atmel_ssc_info *ssc_p = &ssc_info[rtd->dai->cpu_dai->id];
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int dir_mask;
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pr_debug("atmel_ssc_startup: SSC_SR=0x%u\n",
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ssc_readl(ssc_p->ssc->regs, SR));
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
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dir_mask = SSC_DIR_MASK_PLAYBACK;
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else
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dir_mask = SSC_DIR_MASK_CAPTURE;
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spin_lock_irq(&ssc_p->lock);
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if (ssc_p->dir_mask & dir_mask) {
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spin_unlock_irq(&ssc_p->lock);
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return -EBUSY;
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}
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ssc_p->dir_mask |= dir_mask;
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spin_unlock_irq(&ssc_p->lock);
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return 0;
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}
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/*
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* Shutdown. Clear DMA parameters and shutdown the SSC if there
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* are no other substreams open.
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*/
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static void atmel_ssc_shutdown(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
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struct atmel_ssc_info *ssc_p = &ssc_info[rtd->dai->cpu_dai->id];
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struct atmel_pcm_dma_params *dma_params;
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int dir, dir_mask;
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
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dir = 0;
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else
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dir = 1;
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dma_params = ssc_p->dma_params[dir];
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if (dma_params != NULL) {
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ssc_writel(ssc_p->ssc->regs, CR, dma_params->mask->ssc_disable);
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pr_debug("atmel_ssc_shutdown: %s disabled SSC_SR=0x%08x\n",
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(dir ? "receive" : "transmit"),
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ssc_readl(ssc_p->ssc->regs, SR));
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dma_params->ssc = NULL;
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dma_params->substream = NULL;
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ssc_p->dma_params[dir] = NULL;
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}
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dir_mask = 1 << dir;
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spin_lock_irq(&ssc_p->lock);
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ssc_p->dir_mask &= ~dir_mask;
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if (!ssc_p->dir_mask) {
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if (ssc_p->initialized) {
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/* Shutdown the SSC clock. */
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pr_debug("atmel_ssc_dau: Stopping clock\n");
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clk_disable(ssc_p->ssc->clk);
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free_irq(ssc_p->ssc->irq, ssc_p);
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ssc_p->initialized = 0;
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}
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/* Reset the SSC */
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ssc_writel(ssc_p->ssc->regs, CR, SSC_BIT(CR_SWRST));
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/* Clear the SSC dividers */
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ssc_p->cmr_div = ssc_p->tcmr_period = ssc_p->rcmr_period = 0;
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}
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spin_unlock_irq(&ssc_p->lock);
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}
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/*
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* Record the DAI format for use in hw_params().
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*/
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static int atmel_ssc_set_dai_fmt(struct snd_soc_dai *cpu_dai,
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unsigned int fmt)
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{
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struct atmel_ssc_info *ssc_p = &ssc_info[cpu_dai->id];
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ssc_p->daifmt = fmt;
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return 0;
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}
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/*
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* Record SSC clock dividers for use in hw_params().
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*/
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static int atmel_ssc_set_dai_clkdiv(struct snd_soc_dai *cpu_dai,
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int div_id, int div)
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{
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struct atmel_ssc_info *ssc_p = &ssc_info[cpu_dai->id];
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switch (div_id) {
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case ATMEL_SSC_CMR_DIV:
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/*
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* The same master clock divider is used for both
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* transmit and receive, so if a value has already
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* been set, it must match this value.
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*/
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if (ssc_p->cmr_div == 0)
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ssc_p->cmr_div = div;
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else
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if (div != ssc_p->cmr_div)
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return -EBUSY;
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break;
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case ATMEL_SSC_TCMR_PERIOD:
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ssc_p->tcmr_period = div;
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break;
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case ATMEL_SSC_RCMR_PERIOD:
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ssc_p->rcmr_period = div;
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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/*
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* Configure the SSC.
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*/
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static int atmel_ssc_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *dai)
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{
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struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
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int id = rtd->dai->cpu_dai->id;
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struct atmel_ssc_info *ssc_p = &ssc_info[id];
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struct atmel_pcm_dma_params *dma_params;
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int dir, channels, bits;
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u32 tfmr, rfmr, tcmr, rcmr;
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int start_event;
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int ret;
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/*
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* Currently, there is only one set of dma params for
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* each direction. If more are added, this code will
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* have to be changed to select the proper set.
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*/
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
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dir = 0;
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else
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dir = 1;
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dma_params = &ssc_dma_params[id][dir];
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dma_params->ssc = ssc_p->ssc;
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dma_params->substream = substream;
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ssc_p->dma_params[dir] = dma_params;
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/*
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* The cpu_dai->dma_data field is only used to communicate the
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* appropriate DMA parameters to the pcm driver hw_params()
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* function. It should not be used for other purposes
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* as it is common to all substreams.
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*/
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rtd->dai->cpu_dai->dma_data = dma_params;
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channels = params_channels(params);
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/*
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* Determine sample size in bits and the PDC increment.
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*/
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switch (params_format(params)) {
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case SNDRV_PCM_FORMAT_S8:
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bits = 8;
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dma_params->pdc_xfer_size = 1;
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break;
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case SNDRV_PCM_FORMAT_S16_LE:
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bits = 16;
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dma_params->pdc_xfer_size = 2;
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break;
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case SNDRV_PCM_FORMAT_S24_LE:
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bits = 24;
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dma_params->pdc_xfer_size = 4;
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break;
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case SNDRV_PCM_FORMAT_S32_LE:
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bits = 32;
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dma_params->pdc_xfer_size = 4;
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break;
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default:
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printk(KERN_WARNING "atmel_ssc_dai: unsupported PCM format");
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return -EINVAL;
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}
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/*
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* The SSC only supports up to 16-bit samples in I2S format, due
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* to the size of the Frame Mode Register FSLEN field.
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*/
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if ((ssc_p->daifmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_I2S
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&& bits > 16) {
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printk(KERN_WARNING
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"atmel_ssc_dai: sample size %d"
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"is too large for I2S\n", bits);
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return -EINVAL;
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}
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/*
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* Compute SSC register settings.
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*/
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switch (ssc_p->daifmt
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& (SND_SOC_DAIFMT_FORMAT_MASK | SND_SOC_DAIFMT_MASTER_MASK)) {
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case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS:
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/*
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* I2S format, SSC provides BCLK and LRC clocks.
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*
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* The SSC transmit and receive clocks are generated
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* from the MCK divider, and the BCLK signal
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* is output on the SSC TK line.
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*/
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rcmr = SSC_BF(RCMR_PERIOD, ssc_p->rcmr_period)
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| SSC_BF(RCMR_STTDLY, START_DELAY)
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| SSC_BF(RCMR_START, SSC_START_FALLING_RF)
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| SSC_BF(RCMR_CKI, SSC_CKI_RISING)
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| SSC_BF(RCMR_CKO, SSC_CKO_NONE)
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| SSC_BF(RCMR_CKS, SSC_CKS_DIV);
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rfmr = SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
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| SSC_BF(RFMR_FSOS, SSC_FSOS_NEGATIVE)
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| SSC_BF(RFMR_FSLEN, (bits - 1))
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| SSC_BF(RFMR_DATNB, (channels - 1))
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| SSC_BIT(RFMR_MSBF)
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| SSC_BF(RFMR_LOOP, 0)
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| SSC_BF(RFMR_DATLEN, (bits - 1));
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tcmr = SSC_BF(TCMR_PERIOD, ssc_p->tcmr_period)
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| SSC_BF(TCMR_STTDLY, START_DELAY)
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| SSC_BF(TCMR_START, SSC_START_FALLING_RF)
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| SSC_BF(TCMR_CKI, SSC_CKI_FALLING)
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| SSC_BF(TCMR_CKO, SSC_CKO_CONTINUOUS)
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| SSC_BF(TCMR_CKS, SSC_CKS_DIV);
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tfmr = SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
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| SSC_BF(TFMR_FSDEN, 0)
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| SSC_BF(TFMR_FSOS, SSC_FSOS_NEGATIVE)
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| SSC_BF(TFMR_FSLEN, (bits - 1))
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| SSC_BF(TFMR_DATNB, (channels - 1))
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| SSC_BIT(TFMR_MSBF)
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| SSC_BF(TFMR_DATDEF, 0)
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| SSC_BF(TFMR_DATLEN, (bits - 1));
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break;
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case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM:
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/*
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* I2S format, CODEC supplies BCLK and LRC clocks.
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*
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* The SSC transmit clock is obtained from the BCLK signal on
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* on the TK line, and the SSC receive clock is
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* generated from the transmit clock.
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*
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* For single channel data, one sample is transferred
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* on the falling edge of the LRC clock.
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* For two channel data, one sample is
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* transferred on both edges of the LRC clock.
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*/
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start_event = ((channels == 1)
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? SSC_START_FALLING_RF
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: SSC_START_EDGE_RF);
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rcmr = SSC_BF(RCMR_PERIOD, 0)
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| SSC_BF(RCMR_STTDLY, START_DELAY)
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| SSC_BF(RCMR_START, start_event)
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| SSC_BF(RCMR_CKI, SSC_CKI_RISING)
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| SSC_BF(RCMR_CKO, SSC_CKO_NONE)
|
|
| SSC_BF(RCMR_CKS, SSC_CKS_CLOCK);
|
|
|
|
rfmr = SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
|
|
| SSC_BF(RFMR_FSOS, SSC_FSOS_NONE)
|
|
| SSC_BF(RFMR_FSLEN, 0)
|
|
| SSC_BF(RFMR_DATNB, 0)
|
|
| SSC_BIT(RFMR_MSBF)
|
|
| SSC_BF(RFMR_LOOP, 0)
|
|
| SSC_BF(RFMR_DATLEN, (bits - 1));
|
|
|
|
tcmr = SSC_BF(TCMR_PERIOD, 0)
|
|
| SSC_BF(TCMR_STTDLY, START_DELAY)
|
|
| SSC_BF(TCMR_START, start_event)
|
|
| SSC_BF(TCMR_CKI, SSC_CKI_FALLING)
|
|
| SSC_BF(TCMR_CKO, SSC_CKO_NONE)
|
|
| SSC_BF(TCMR_CKS, SSC_CKS_PIN);
|
|
|
|
tfmr = SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
|
|
| SSC_BF(TFMR_FSDEN, 0)
|
|
| SSC_BF(TFMR_FSOS, SSC_FSOS_NONE)
|
|
| SSC_BF(TFMR_FSLEN, 0)
|
|
| SSC_BF(TFMR_DATNB, 0)
|
|
| SSC_BIT(TFMR_MSBF)
|
|
| SSC_BF(TFMR_DATDEF, 0)
|
|
| SSC_BF(TFMR_DATLEN, (bits - 1));
|
|
break;
|
|
|
|
case SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_CBS_CFS:
|
|
/*
|
|
* DSP/PCM Mode A format, SSC provides BCLK and LRC clocks.
|
|
*
|
|
* The SSC transmit and receive clocks are generated from the
|
|
* MCK divider, and the BCLK signal is output
|
|
* on the SSC TK line.
|
|
*/
|
|
rcmr = SSC_BF(RCMR_PERIOD, ssc_p->rcmr_period)
|
|
| SSC_BF(RCMR_STTDLY, 1)
|
|
| SSC_BF(RCMR_START, SSC_START_RISING_RF)
|
|
| SSC_BF(RCMR_CKI, SSC_CKI_RISING)
|
|
| SSC_BF(RCMR_CKO, SSC_CKO_NONE)
|
|
| SSC_BF(RCMR_CKS, SSC_CKS_DIV);
|
|
|
|
rfmr = SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
|
|
| SSC_BF(RFMR_FSOS, SSC_FSOS_POSITIVE)
|
|
| SSC_BF(RFMR_FSLEN, 0)
|
|
| SSC_BF(RFMR_DATNB, (channels - 1))
|
|
| SSC_BIT(RFMR_MSBF)
|
|
| SSC_BF(RFMR_LOOP, 0)
|
|
| SSC_BF(RFMR_DATLEN, (bits - 1));
|
|
|
|
tcmr = SSC_BF(TCMR_PERIOD, ssc_p->tcmr_period)
|
|
| SSC_BF(TCMR_STTDLY, 1)
|
|
| SSC_BF(TCMR_START, SSC_START_RISING_RF)
|
|
| SSC_BF(TCMR_CKI, SSC_CKI_RISING)
|
|
| SSC_BF(TCMR_CKO, SSC_CKO_CONTINUOUS)
|
|
| SSC_BF(TCMR_CKS, SSC_CKS_DIV);
|
|
|
|
tfmr = SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
|
|
| SSC_BF(TFMR_FSDEN, 0)
|
|
| SSC_BF(TFMR_FSOS, SSC_FSOS_POSITIVE)
|
|
| SSC_BF(TFMR_FSLEN, 0)
|
|
| SSC_BF(TFMR_DATNB, (channels - 1))
|
|
| SSC_BIT(TFMR_MSBF)
|
|
| SSC_BF(TFMR_DATDEF, 0)
|
|
| SSC_BF(TFMR_DATLEN, (bits - 1));
|
|
break;
|
|
|
|
case SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_CBM_CFM:
|
|
default:
|
|
printk(KERN_WARNING "atmel_ssc_dai: unsupported DAI format 0x%x\n",
|
|
ssc_p->daifmt);
|
|
return -EINVAL;
|
|
break;
|
|
}
|
|
pr_debug("atmel_ssc_hw_params: "
|
|
"RCMR=%08x RFMR=%08x TCMR=%08x TFMR=%08x\n",
|
|
rcmr, rfmr, tcmr, tfmr);
|
|
|
|
if (!ssc_p->initialized) {
|
|
|
|
/* Enable PMC peripheral clock for this SSC */
|
|
pr_debug("atmel_ssc_dai: Starting clock\n");
|
|
clk_enable(ssc_p->ssc->clk);
|
|
|
|
/* Reset the SSC and its PDC registers */
|
|
ssc_writel(ssc_p->ssc->regs, CR, SSC_BIT(CR_SWRST));
|
|
|
|
ssc_writel(ssc_p->ssc->regs, PDC_RPR, 0);
|
|
ssc_writel(ssc_p->ssc->regs, PDC_RCR, 0);
|
|
ssc_writel(ssc_p->ssc->regs, PDC_RNPR, 0);
|
|
ssc_writel(ssc_p->ssc->regs, PDC_RNCR, 0);
|
|
|
|
ssc_writel(ssc_p->ssc->regs, PDC_TPR, 0);
|
|
ssc_writel(ssc_p->ssc->regs, PDC_TCR, 0);
|
|
ssc_writel(ssc_p->ssc->regs, PDC_TNPR, 0);
|
|
ssc_writel(ssc_p->ssc->regs, PDC_TNCR, 0);
|
|
|
|
ret = request_irq(ssc_p->ssc->irq, atmel_ssc_interrupt, 0,
|
|
ssc_p->name, ssc_p);
|
|
if (ret < 0) {
|
|
printk(KERN_WARNING
|
|
"atmel_ssc_dai: request_irq failure\n");
|
|
pr_debug("Atmel_ssc_dai: Stoping clock\n");
|
|
clk_disable(ssc_p->ssc->clk);
|
|
return ret;
|
|
}
|
|
|
|
ssc_p->initialized = 1;
|
|
}
|
|
|
|
/* set SSC clock mode register */
|
|
ssc_writel(ssc_p->ssc->regs, CMR, ssc_p->cmr_div);
|
|
|
|
/* set receive clock mode and format */
|
|
ssc_writel(ssc_p->ssc->regs, RCMR, rcmr);
|
|
ssc_writel(ssc_p->ssc->regs, RFMR, rfmr);
|
|
|
|
/* set transmit clock mode and format */
|
|
ssc_writel(ssc_p->ssc->regs, TCMR, tcmr);
|
|
ssc_writel(ssc_p->ssc->regs, TFMR, tfmr);
|
|
|
|
pr_debug("atmel_ssc_dai,hw_params: SSC initialized\n");
|
|
return 0;
|
|
}
|
|
|
|
|
|
static int atmel_ssc_prepare(struct snd_pcm_substream *substream,
|
|
struct snd_soc_dai *dai)
|
|
{
|
|
struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
|
|
struct atmel_ssc_info *ssc_p = &ssc_info[rtd->dai->cpu_dai->id];
|
|
struct atmel_pcm_dma_params *dma_params;
|
|
int dir;
|
|
|
|
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
|
|
dir = 0;
|
|
else
|
|
dir = 1;
|
|
|
|
dma_params = ssc_p->dma_params[dir];
|
|
|
|
ssc_writel(ssc_p->ssc->regs, CR, dma_params->mask->ssc_enable);
|
|
|
|
pr_debug("%s enabled SSC_SR=0x%08x\n",
|
|
dir ? "receive" : "transmit",
|
|
ssc_readl(ssc_p->ssc->regs, SR));
|
|
return 0;
|
|
}
|
|
|
|
|
|
#ifdef CONFIG_PM
|
|
static int atmel_ssc_suspend(struct snd_soc_dai *cpu_dai)
|
|
{
|
|
struct atmel_ssc_info *ssc_p;
|
|
|
|
if (!cpu_dai->active)
|
|
return 0;
|
|
|
|
ssc_p = &ssc_info[cpu_dai->id];
|
|
|
|
/* Save the status register before disabling transmit and receive */
|
|
ssc_p->ssc_state.ssc_sr = ssc_readl(ssc_p->ssc->regs, SR);
|
|
ssc_writel(ssc_p->ssc->regs, CR, SSC_BIT(CR_TXDIS) | SSC_BIT(CR_RXDIS));
|
|
|
|
/* Save the current interrupt mask, then disable unmasked interrupts */
|
|
ssc_p->ssc_state.ssc_imr = ssc_readl(ssc_p->ssc->regs, IMR);
|
|
ssc_writel(ssc_p->ssc->regs, IDR, ssc_p->ssc_state.ssc_imr);
|
|
|
|
ssc_p->ssc_state.ssc_cmr = ssc_readl(ssc_p->ssc->regs, CMR);
|
|
ssc_p->ssc_state.ssc_rcmr = ssc_readl(ssc_p->ssc->regs, RCMR);
|
|
ssc_p->ssc_state.ssc_rfmr = ssc_readl(ssc_p->ssc->regs, RFMR);
|
|
ssc_p->ssc_state.ssc_tcmr = ssc_readl(ssc_p->ssc->regs, TCMR);
|
|
ssc_p->ssc_state.ssc_tfmr = ssc_readl(ssc_p->ssc->regs, TFMR);
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
|
|
static int atmel_ssc_resume(struct snd_soc_dai *cpu_dai)
|
|
{
|
|
struct atmel_ssc_info *ssc_p;
|
|
u32 cr;
|
|
|
|
if (!cpu_dai->active)
|
|
return 0;
|
|
|
|
ssc_p = &ssc_info[cpu_dai->id];
|
|
|
|
/* restore SSC register settings */
|
|
ssc_writel(ssc_p->ssc->regs, TFMR, ssc_p->ssc_state.ssc_tfmr);
|
|
ssc_writel(ssc_p->ssc->regs, TCMR, ssc_p->ssc_state.ssc_tcmr);
|
|
ssc_writel(ssc_p->ssc->regs, RFMR, ssc_p->ssc_state.ssc_rfmr);
|
|
ssc_writel(ssc_p->ssc->regs, RCMR, ssc_p->ssc_state.ssc_rcmr);
|
|
ssc_writel(ssc_p->ssc->regs, CMR, ssc_p->ssc_state.ssc_cmr);
|
|
|
|
/* re-enable interrupts */
|
|
ssc_writel(ssc_p->ssc->regs, IER, ssc_p->ssc_state.ssc_imr);
|
|
|
|
/* Re-enable recieve and transmit as appropriate */
|
|
cr = 0;
|
|
cr |=
|
|
(ssc_p->ssc_state.ssc_sr & SSC_BIT(SR_RXEN)) ? SSC_BIT(CR_RXEN) : 0;
|
|
cr |=
|
|
(ssc_p->ssc_state.ssc_sr & SSC_BIT(SR_TXEN)) ? SSC_BIT(CR_TXEN) : 0;
|
|
ssc_writel(ssc_p->ssc->regs, CR, cr);
|
|
|
|
return 0;
|
|
}
|
|
#else /* CONFIG_PM */
|
|
# define atmel_ssc_suspend NULL
|
|
# define atmel_ssc_resume NULL
|
|
#endif /* CONFIG_PM */
|
|
|
|
|
|
#define ATMEL_SSC_RATES (SNDRV_PCM_RATE_8000_96000)
|
|
|
|
#define ATMEL_SSC_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |\
|
|
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
|
|
|
|
static struct snd_soc_dai_ops atmel_ssc_dai_ops = {
|
|
.startup = atmel_ssc_startup,
|
|
.shutdown = atmel_ssc_shutdown,
|
|
.prepare = atmel_ssc_prepare,
|
|
.hw_params = atmel_ssc_hw_params,
|
|
.set_fmt = atmel_ssc_set_dai_fmt,
|
|
.set_clkdiv = atmel_ssc_set_dai_clkdiv,
|
|
};
|
|
|
|
struct snd_soc_dai atmel_ssc_dai[NUM_SSC_DEVICES] = {
|
|
{ .name = "atmel-ssc0",
|
|
.id = 0,
|
|
.suspend = atmel_ssc_suspend,
|
|
.resume = atmel_ssc_resume,
|
|
.playback = {
|
|
.channels_min = 1,
|
|
.channels_max = 2,
|
|
.rates = ATMEL_SSC_RATES,
|
|
.formats = ATMEL_SSC_FORMATS,},
|
|
.capture = {
|
|
.channels_min = 1,
|
|
.channels_max = 2,
|
|
.rates = ATMEL_SSC_RATES,
|
|
.formats = ATMEL_SSC_FORMATS,},
|
|
.ops = &atmel_ssc_dai_ops,
|
|
.private_data = &ssc_info[0],
|
|
},
|
|
#if NUM_SSC_DEVICES == 3
|
|
{ .name = "atmel-ssc1",
|
|
.id = 1,
|
|
.suspend = atmel_ssc_suspend,
|
|
.resume = atmel_ssc_resume,
|
|
.playback = {
|
|
.channels_min = 1,
|
|
.channels_max = 2,
|
|
.rates = ATMEL_SSC_RATES,
|
|
.formats = ATMEL_SSC_FORMATS,},
|
|
.capture = {
|
|
.channels_min = 1,
|
|
.channels_max = 2,
|
|
.rates = ATMEL_SSC_RATES,
|
|
.formats = ATMEL_SSC_FORMATS,},
|
|
.ops = &atmel_ssc_dai_ops,
|
|
.private_data = &ssc_info[1],
|
|
},
|
|
{ .name = "atmel-ssc2",
|
|
.id = 2,
|
|
.suspend = atmel_ssc_suspend,
|
|
.resume = atmel_ssc_resume,
|
|
.playback = {
|
|
.channels_min = 1,
|
|
.channels_max = 2,
|
|
.rates = ATMEL_SSC_RATES,
|
|
.formats = ATMEL_SSC_FORMATS,},
|
|
.capture = {
|
|
.channels_min = 1,
|
|
.channels_max = 2,
|
|
.rates = ATMEL_SSC_RATES,
|
|
.formats = ATMEL_SSC_FORMATS,},
|
|
.ops = &atmel_ssc_dai_ops,
|
|
.private_data = &ssc_info[2],
|
|
},
|
|
#endif
|
|
};
|
|
EXPORT_SYMBOL_GPL(atmel_ssc_dai);
|
|
|
|
static int __init atmel_ssc_modinit(void)
|
|
{
|
|
return snd_soc_register_dais(atmel_ssc_dai, ARRAY_SIZE(atmel_ssc_dai));
|
|
}
|
|
module_init(atmel_ssc_modinit);
|
|
|
|
static void __exit atmel_ssc_modexit(void)
|
|
{
|
|
snd_soc_unregister_dais(atmel_ssc_dai, ARRAY_SIZE(atmel_ssc_dai));
|
|
}
|
|
module_exit(atmel_ssc_modexit);
|
|
|
|
/* Module information */
|
|
MODULE_AUTHOR("Sedji Gaouaou, sedji.gaouaou@atmel.com, www.atmel.com");
|
|
MODULE_DESCRIPTION("ATMEL SSC ASoC Interface");
|
|
MODULE_LICENSE("GPL");
|