140 lines
3.2 KiB
C
140 lines
3.2 KiB
C
/*
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* linux/arch/sh/boards/se/7724/irq.c
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*
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* Copyright (C) 2009 Renesas Solutions Corp.
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*
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* Kuninori Morimoto <morimoto.kuninori@renesas.com>
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*
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* Based on linux/arch/sh/boards/se/7722/irq.c
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* Copyright (C) 2007 Nobuhiro Iwamatsu
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*
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* Hitachi UL SolutionEngine 7724 Support.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <asm/irq.h>
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#include <asm/io.h>
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#include <mach-se/mach/se7724.h>
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struct fpga_irq {
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unsigned long sraddr;
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unsigned long mraddr;
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unsigned short mask;
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unsigned int base;
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};
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static unsigned int fpga2irq(unsigned int irq)
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{
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if (irq >= IRQ0_BASE &&
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irq <= IRQ0_END)
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return IRQ0_IRQ;
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else if (irq >= IRQ1_BASE &&
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irq <= IRQ1_END)
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return IRQ1_IRQ;
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else
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return IRQ2_IRQ;
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}
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static struct fpga_irq get_fpga_irq(unsigned int irq)
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{
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struct fpga_irq set;
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switch (irq) {
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case IRQ0_IRQ:
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set.sraddr = IRQ0_SR;
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set.mraddr = IRQ0_MR;
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set.mask = IRQ0_MASK;
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set.base = IRQ0_BASE;
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break;
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case IRQ1_IRQ:
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set.sraddr = IRQ1_SR;
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set.mraddr = IRQ1_MR;
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set.mask = IRQ1_MASK;
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set.base = IRQ1_BASE;
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break;
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default:
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set.sraddr = IRQ2_SR;
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set.mraddr = IRQ2_MR;
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set.mask = IRQ2_MASK;
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set.base = IRQ2_BASE;
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break;
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}
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return set;
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}
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static void disable_se7724_irq(unsigned int irq)
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{
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struct fpga_irq set = get_fpga_irq(fpga2irq(irq));
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unsigned int bit = irq - set.base;
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ctrl_outw(ctrl_inw(set.mraddr) | 0x0001 << bit, set.mraddr);
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}
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static void enable_se7724_irq(unsigned int irq)
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{
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struct fpga_irq set = get_fpga_irq(fpga2irq(irq));
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unsigned int bit = irq - set.base;
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ctrl_outw(ctrl_inw(set.mraddr) & ~(0x0001 << bit), set.mraddr);
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}
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static struct irq_chip se7724_irq_chip __read_mostly = {
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.name = "SE7724-FPGA",
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.mask = disable_se7724_irq,
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.unmask = enable_se7724_irq,
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.mask_ack = disable_se7724_irq,
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};
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static void se7724_irq_demux(unsigned int irq, struct irq_desc *desc)
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{
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struct fpga_irq set = get_fpga_irq(irq);
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unsigned short intv = ctrl_inw(set.sraddr);
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struct irq_desc *ext_desc;
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unsigned int ext_irq = set.base;
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intv &= set.mask;
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while (intv) {
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if (intv & 0x0001) {
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ext_desc = irq_desc + ext_irq;
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handle_level_irq(ext_irq, ext_desc);
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}
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intv >>= 1;
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ext_irq++;
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}
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}
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/*
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* Initialize IRQ setting
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*/
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void __init init_se7724_IRQ(void)
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{
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int i;
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ctrl_outw(0xffff, IRQ0_MR); /* mask all */
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ctrl_outw(0xffff, IRQ1_MR); /* mask all */
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ctrl_outw(0xffff, IRQ2_MR); /* mask all */
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ctrl_outw(0x0000, IRQ0_SR); /* clear irq */
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ctrl_outw(0x0000, IRQ1_SR); /* clear irq */
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ctrl_outw(0x0000, IRQ2_SR); /* clear irq */
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ctrl_outw(0x002a, IRQ_MODE); /* set irq type */
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for (i = 0; i < SE7724_FPGA_IRQ_NR; i++)
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set_irq_chip_and_handler_name(SE7724_FPGA_IRQ_BASE + i,
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&se7724_irq_chip,
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handle_level_irq, "level");
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set_irq_chained_handler(IRQ0_IRQ, se7724_irq_demux);
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set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW);
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set_irq_chained_handler(IRQ1_IRQ, se7724_irq_demux);
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set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW);
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set_irq_chained_handler(IRQ2_IRQ, se7724_irq_demux);
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set_irq_type(IRQ2_IRQ, IRQ_TYPE_LEVEL_LOW);
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}
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