687 lines
16 KiB
C
687 lines
16 KiB
C
/*
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* Misc utility routines for accessing chip-specific features
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* of the SiliconBackplane-based Broadcom chips.
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*
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* Copyright (C) 1999-2010, Broadcom Corporation
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*
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* Unless you and Broadcom execute a separate written software license
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* agreement governing use of this software, this software is licensed to you
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* under the terms of the GNU General Public License version 2 (the "GPL"),
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* available at http://www.broadcom.com/licenses/GPLv2.php, with the
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* following added to such license:
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*
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* As a special exception, the copyright holders of this software give you
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* permission to link this software with independent modules, and to copy and
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* distribute the resulting executable under terms of your choice, provided that
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* you also meet, for each linked independent module, the terms and conditions of
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* the license of that module. An independent module is a module which is not
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* derived from this software. The special exception does not apply to any
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* modifications of the software.
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*
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* Notwithstanding the above, under no circumstances may you combine this
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* software in any way with any other Broadcom software provided under a license
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* other than the GPL, without Broadcom's express prior written consent.
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*
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* $Id: aiutils.c,v 1.6.4.7.4.6 2010/04/21 20:43:47 Exp $
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*/
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#include <typedefs.h>
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#include <bcmdefs.h>
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#include <osl.h>
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#include <bcmutils.h>
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#include <siutils.h>
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#include <hndsoc.h>
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#include <sbchipc.h>
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#include <pcicfg.h>
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#include "siutils_priv.h"
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STATIC uint32
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get_asd(si_t *sih, uint32 *eromptr, uint sp, uint ad, uint st,
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uint32 *addrl, uint32 *addrh, uint32 *sizel, uint32 *sizeh);
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/* EROM parsing */
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static uint32
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get_erom_ent(si_t *sih, uint32 *eromptr, uint32 mask, uint32 match)
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{
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uint32 ent;
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uint inv = 0, nom = 0;
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while (TRUE) {
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ent = R_REG(si_osh(sih), (uint32 *)(uintptr)(*eromptr));
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*eromptr += sizeof(uint32);
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if (mask == 0)
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break;
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if ((ent & ER_VALID) == 0) {
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inv++;
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continue;
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}
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if (ent == (ER_END | ER_VALID))
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break;
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if ((ent & mask) == match)
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break;
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nom++;
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}
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SI_MSG(("%s: Returning ent 0x%08x\n", __FUNCTION__, ent));
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if (inv + nom)
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SI_MSG((" after %d invalid and %d non-matching entries\n", inv, nom));
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return ent;
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}
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STATIC uint32
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get_asd(si_t *sih, uint32 *eromptr, uint sp, uint ad, uint st,
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uint32 *addrl, uint32 *addrh, uint32 *sizel, uint32 *sizeh)
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{
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uint32 asd, sz, szd;
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asd = get_erom_ent(sih, eromptr, ER_VALID, ER_VALID);
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if (((asd & ER_TAG1) != ER_ADD) ||
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(((asd & AD_SP_MASK) >> AD_SP_SHIFT) != sp) ||
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((asd & AD_ST_MASK) != st)) {
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/* This is not what we want, "push" it back */
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*eromptr -= sizeof(uint32);
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return 0;
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}
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*addrl = asd & AD_ADDR_MASK;
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if (asd & AD_AG32)
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*addrh = get_erom_ent(sih, eromptr, 0, 0);
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else
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*addrh = 0;
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*sizeh = 0;
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sz = asd & AD_SZ_MASK;
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if (sz == AD_SZ_SZD) {
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szd = get_erom_ent(sih, eromptr, 0, 0);
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*sizel = szd & SD_SZ_MASK;
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if (szd & SD_SG32)
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*sizeh = get_erom_ent(sih, eromptr, 0, 0);
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} else
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*sizel = AD_SZ_BASE << (sz >> AD_SZ_SHIFT);
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SI_MSG((" SP %d, ad %d: st = %d, 0x%08x_0x%08x @ 0x%08x_0x%08x\n",
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sp, ad, st, *sizeh, *sizel, *addrh, *addrl));
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return asd;
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}
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/* parse the enumeration rom to identify all cores */
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void
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ai_scan(si_t *sih, void *regs, uint devid)
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{
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si_info_t *sii = SI_INFO(sih);
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chipcregs_t *cc = (chipcregs_t *)regs;
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uint32 erombase, eromptr, eromlim;
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erombase = R_REG(sii->osh, &cc->eromptr);
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switch (BUSTYPE(sih->bustype)) {
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case SI_BUS:
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eromptr = (uintptr)REG_MAP(erombase, SI_CORE_SIZE);
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break;
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case PCI_BUS:
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/* Set wrappers address */
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sii->curwrap = (void *)((uintptr)regs + SI_CORE_SIZE);
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/* Now point the window at the erom */
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OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN, 4, erombase);
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eromptr = (uint32)(uintptr)regs;
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break;
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case SPI_BUS:
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case SDIO_BUS:
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eromptr = erombase;
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break;
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case PCMCIA_BUS:
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default:
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SI_ERROR(("Don't know how to do AXI enumertion on bus %d\n", sih->bustype));
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ASSERT(0);
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return;
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}
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eromlim = eromptr + ER_REMAPCONTROL;
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SI_MSG(("ai_scan: regs = 0x%p, erombase = 0x%08x, eromptr = 0x%08x, eromlim = 0x%08x\n",
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regs, erombase, eromptr, eromlim));
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while (eromptr < eromlim) {
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uint32 cia, cib, base, cid, mfg, crev, nmw, nsw, nmp, nsp;
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uint32 mpd, asd, addrl, addrh, sizel, sizeh;
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uint i, j, idx;
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bool br;
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br = FALSE;
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/* Grok a component */
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cia = get_erom_ent(sih, &eromptr, ER_TAG, ER_CI);
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if (cia == (ER_END | ER_VALID)) {
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SI_MSG(("Found END of erom after %d cores\n", sii->numcores));
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return;
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}
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base = eromptr - sizeof(uint32);
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cib = get_erom_ent(sih, &eromptr, 0, 0);
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if ((cib & ER_TAG) != ER_CI) {
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SI_ERROR(("CIA not followed by CIB\n"));
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goto error;
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}
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cid = (cia & CIA_CID_MASK) >> CIA_CID_SHIFT;
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mfg = (cia & CIA_MFG_MASK) >> CIA_MFG_SHIFT;
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crev = (cib & CIB_REV_MASK) >> CIB_REV_SHIFT;
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nmw = (cib & CIB_NMW_MASK) >> CIB_NMW_SHIFT;
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nsw = (cib & CIB_NSW_MASK) >> CIB_NSW_SHIFT;
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nmp = (cib & CIB_NMP_MASK) >> CIB_NMP_SHIFT;
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nsp = (cib & CIB_NSP_MASK) >> CIB_NSP_SHIFT;
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SI_MSG(("Found component 0x%04x/0x%4x rev %d at erom addr 0x%08x, with nmw = %d, "
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"nsw = %d, nmp = %d & nsp = %d\n",
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mfg, cid, crev, base, nmw, nsw, nmp, nsp));
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if (((mfg == MFGID_ARM) && (cid == DEF_AI_COMP)) || (nsp == 0))
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continue;
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if ((nmw + nsw == 0)) {
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/* A component which is not a core */
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if (cid == OOB_ROUTER_CORE_ID) {
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asd = get_asd(sih, &eromptr, 0, 0, AD_ST_SLAVE,
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&addrl, &addrh, &sizel, &sizeh);
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if (asd != 0) {
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sii->common_info->oob_router = addrl;
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}
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}
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continue;
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}
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idx = sii->numcores;
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/* sii->eromptr[idx] = base; */
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sii->common_info->cia[idx] = cia;
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sii->common_info->cib[idx] = cib;
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sii->common_info->coreid[idx] = cid;
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for (i = 0; i < nmp; i++) {
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mpd = get_erom_ent(sih, &eromptr, ER_VALID, ER_VALID);
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if ((mpd & ER_TAG) != ER_MP) {
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SI_ERROR(("Not enough MP entries for component 0x%x\n", cid));
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goto error;
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}
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SI_MSG((" Master port %d, mp: %d id: %d\n", i,
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(mpd & MPD_MP_MASK) >> MPD_MP_SHIFT,
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(mpd & MPD_MUI_MASK) >> MPD_MUI_SHIFT));
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}
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/* First Slave Address Descriptor should be port 0:
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* the main register space for the core
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*/
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asd = get_asd(sih, &eromptr, 0, 0, AD_ST_SLAVE, &addrl, &addrh, &sizel, &sizeh);
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if (asd == 0) {
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/* Try again to see if it is a bridge */
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asd = get_asd(sih, &eromptr, 0, 0, AD_ST_BRIDGE, &addrl, &addrh,
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&sizel, &sizeh);
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if (asd != 0)
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br = TRUE;
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else
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if ((addrh != 0) || (sizeh != 0) || (sizel != SI_CORE_SIZE)) {
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SI_ERROR(("First Slave ASD for core 0x%04x malformed "
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"(0x%08x)\n", cid, asd));
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goto error;
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}
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}
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sii->common_info->coresba[idx] = addrl;
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sii->common_info->coresba_size[idx] = sizel;
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/* Get any more ASDs in port 0 */
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j = 1;
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do {
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asd = get_asd(sih, &eromptr, 0, j, AD_ST_SLAVE, &addrl, &addrh,
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&sizel, &sizeh);
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if ((asd != 0) && (j == 1) && (sizel == SI_CORE_SIZE))
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sii->common_info->coresba2[idx] = addrl;
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sii->common_info->coresba2_size[idx] = sizel;
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j++;
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} while (asd != 0);
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/* Go through the ASDs for other slave ports */
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for (i = 1; i < nsp; i++) {
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j = 0;
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do {
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asd = get_asd(sih, &eromptr, i, j++, AD_ST_SLAVE, &addrl, &addrh,
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&sizel, &sizeh);
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} while (asd != 0);
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if (j == 0) {
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SI_ERROR((" SP %d has no address descriptors\n", i));
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goto error;
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}
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}
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/* Now get master wrappers */
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for (i = 0; i < nmw; i++) {
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asd = get_asd(sih, &eromptr, i, 0, AD_ST_MWRAP, &addrl, &addrh,
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&sizel, &sizeh);
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if (asd == 0) {
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SI_ERROR(("Missing descriptor for MW %d\n", i));
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goto error;
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}
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if ((sizeh != 0) || (sizel != SI_CORE_SIZE)) {
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SI_ERROR(("Master wrapper %d is not 4KB\n", i));
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goto error;
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}
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if (i == 0)
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sii->common_info->wrapba[idx] = addrl;
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}
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/* And finally slave wrappers */
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for (i = 0; i < nsw; i++) {
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uint fwp = (nsp == 1) ? 0 : 1;
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asd = get_asd(sih, &eromptr, fwp + i, 0, AD_ST_SWRAP, &addrl, &addrh,
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&sizel, &sizeh);
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if (asd == 0) {
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SI_ERROR(("Missing descriptor for SW %d\n", i));
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goto error;
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}
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if ((sizeh != 0) || (sizel != SI_CORE_SIZE)) {
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SI_ERROR(("Slave wrapper %d is not 4KB\n", i));
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goto error;
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}
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if ((nmw == 0) && (i == 0))
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sii->common_info->wrapba[idx] = addrl;
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}
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/* Don't record bridges */
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if (br)
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continue;
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/* Done with core */
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sii->numcores++;
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}
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SI_ERROR(("Reached end of erom without finding END"));
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error:
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sii->numcores = 0;
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return;
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}
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/* This function changes the logical "focus" to the indicated core.
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* Return the current core's virtual address.
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*/
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void *
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ai_setcoreidx(si_t *sih, uint coreidx)
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{
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si_info_t *sii = SI_INFO(sih);
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uint32 addr = sii->common_info->coresba[coreidx];
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uint32 wrap = sii->common_info->wrapba[coreidx];
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void *regs;
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if (coreidx >= sii->numcores)
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return (NULL);
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/*
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* If the user has provided an interrupt mask enabled function,
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* then assert interrupts are disabled before switching the core.
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*/
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ASSERT((sii->intrsenabled_fn == NULL) || !(*(sii)->intrsenabled_fn)((sii)->intr_arg));
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switch (BUSTYPE(sih->bustype)) {
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case SI_BUS:
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/* map new one */
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if (!sii->common_info->regs[coreidx]) {
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sii->common_info->regs[coreidx] = REG_MAP(addr, SI_CORE_SIZE);
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ASSERT(GOODREGS(sii->common_info->regs[coreidx]));
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}
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sii->curmap = regs = sii->common_info->regs[coreidx];
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if (!sii->common_info->wrappers[coreidx]) {
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sii->common_info->wrappers[coreidx] = REG_MAP(wrap, SI_CORE_SIZE);
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ASSERT(GOODREGS(sii->common_info->wrappers[coreidx]));
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}
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sii->curwrap = sii->common_info->wrappers[coreidx];
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break;
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case SPI_BUS:
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case SDIO_BUS:
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sii->curmap = regs = (void *)((uintptr)addr);
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sii->curwrap = (void *)((uintptr)wrap);
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break;
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case PCMCIA_BUS:
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default:
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ASSERT(0);
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regs = NULL;
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break;
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}
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sii->curmap = regs;
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sii->curidx = coreidx;
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return regs;
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}
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/* Return the number of address spaces in current core */
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int
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ai_numaddrspaces(si_t *sih)
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{
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return 2;
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}
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/* Return the address of the nth address space in the current core */
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uint32
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ai_addrspace(si_t *sih, uint asidx)
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{
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si_info_t *sii;
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uint cidx;
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sii = SI_INFO(sih);
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cidx = sii->curidx;
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if (asidx == 0)
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return sii->common_info->coresba[cidx];
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else if (asidx == 1)
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return sii->common_info->coresba2[cidx];
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else {
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SI_ERROR(("%s: Need to parse the erom again to find addr space %d\n",
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__FUNCTION__, asidx));
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return 0;
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}
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}
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/* Return the size of the nth address space in the current core */
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uint32
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ai_addrspacesize(si_t *sih, uint asidx)
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{
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si_info_t *sii;
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uint cidx;
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sii = SI_INFO(sih);
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cidx = sii->curidx;
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if (asidx == 0)
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return sii->common_info->coresba_size[cidx];
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else if (asidx == 1)
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return sii->common_info->coresba2_size[cidx];
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else {
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SI_ERROR(("%s: Need to parse the erom again to find addr space %d\n",
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__FUNCTION__, asidx));
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return 0;
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}
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}
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uint
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ai_flag(si_t *sih)
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{
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si_info_t *sii;
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aidmp_t *ai;
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sii = SI_INFO(sih);
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ai = sii->curwrap;
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return (R_REG(sii->osh, &ai->oobselouta30) & 0x1f);
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}
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void
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ai_setint(si_t *sih, int siflag)
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{
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}
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void
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ai_write_wrap_reg(si_t *sih, uint32 offset, uint32 val)
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{
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si_info_t *sii = SI_INFO(sih);
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aidmp_t *ai = sii->curwrap;
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W_REG(sii->osh, (uint32 *)((uint8 *)ai+offset), val);
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return;
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}
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uint
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ai_corevendor(si_t *sih)
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{
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si_info_t *sii;
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uint32 cia;
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sii = SI_INFO(sih);
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cia = sii->common_info->cia[sii->curidx];
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return ((cia & CIA_MFG_MASK) >> CIA_MFG_SHIFT);
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}
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uint
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ai_corerev(si_t *sih)
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{
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si_info_t *sii;
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uint32 cib;
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sii = SI_INFO(sih);
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cib = sii->common_info->cib[sii->curidx];
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return ((cib & CIB_REV_MASK) >> CIB_REV_SHIFT);
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}
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bool
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ai_iscoreup(si_t *sih)
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{
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si_info_t *sii;
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aidmp_t *ai;
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sii = SI_INFO(sih);
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ai = sii->curwrap;
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return (((R_REG(sii->osh, &ai->ioctrl) & (SICF_FGC | SICF_CLOCK_EN)) == SICF_CLOCK_EN) &&
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((R_REG(sii->osh, &ai->resetctrl) & AIRC_RESET) == 0));
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}
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/*
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* Switch to 'coreidx', issue a single arbitrary 32bit register mask&set operation,
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* switch back to the original core, and return the new value.
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*
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* When using the silicon backplane, no fidleing with interrupts or core switches are needed.
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*
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* Also, when using pci/pcie, we can optimize away the core switching for pci registers
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* and (on newer pci cores) chipcommon registers.
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*/
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uint
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ai_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val)
|
|
{
|
|
uint origidx = 0;
|
|
uint32 *r = NULL;
|
|
uint w;
|
|
uint intr_val = 0;
|
|
bool fast = FALSE;
|
|
si_info_t *sii;
|
|
|
|
sii = SI_INFO(sih);
|
|
|
|
ASSERT(GOODIDX(coreidx));
|
|
ASSERT(regoff < SI_CORE_SIZE);
|
|
ASSERT((val & ~mask) == 0);
|
|
|
|
if (coreidx >= SI_MAXCORES)
|
|
return 0;
|
|
|
|
if (BUSTYPE(sih->bustype) == SI_BUS) {
|
|
/* If internal bus, we can always get at everything */
|
|
fast = TRUE;
|
|
/* map if does not exist */
|
|
if (!sii->common_info->wrappers[coreidx]) {
|
|
sii->common_info->regs[coreidx] =
|
|
REG_MAP(sii->common_info->coresba[coreidx], SI_CORE_SIZE);
|
|
ASSERT(GOODREGS(sii->common_info->regs[coreidx]));
|
|
}
|
|
r = (uint32 *)((uchar *)sii->common_info->regs[coreidx] + regoff);
|
|
} else if (BUSTYPE(sih->bustype) == PCI_BUS) {
|
|
/* If pci/pcie, we can get at pci/pcie regs and on newer cores to chipc */
|
|
|
|
if ((sii->common_info->coreid[coreidx] == CC_CORE_ID) && SI_FAST(sii)) {
|
|
/* Chipc registers are mapped at 12KB */
|
|
|
|
fast = TRUE;
|
|
r = (uint32 *)((char *)sii->curmap + PCI_16KB0_CCREGS_OFFSET + regoff);
|
|
} else if (sii->pub.buscoreidx == coreidx) {
|
|
/* pci registers are at either in the last 2KB of an 8KB window
|
|
* or, in pcie and pci rev 13 at 8KB
|
|
*/
|
|
fast = TRUE;
|
|
if (SI_FAST(sii))
|
|
r = (uint32 *)((char *)sii->curmap +
|
|
PCI_16KB0_PCIREGS_OFFSET + regoff);
|
|
else
|
|
r = (uint32 *)((char *)sii->curmap +
|
|
((regoff >= SBCONFIGOFF) ?
|
|
PCI_BAR0_PCISBR_OFFSET : PCI_BAR0_PCIREGS_OFFSET) +
|
|
regoff);
|
|
}
|
|
}
|
|
|
|
if (!fast) {
|
|
INTR_OFF(sii, intr_val);
|
|
|
|
/* save current core index */
|
|
origidx = si_coreidx(&sii->pub);
|
|
|
|
/* switch core */
|
|
r = (uint32*) ((uchar*) ai_setcoreidx(&sii->pub, coreidx) + regoff);
|
|
}
|
|
ASSERT(r != NULL);
|
|
|
|
/* mask and set */
|
|
if (mask || val) {
|
|
w = (R_REG(sii->osh, r) & ~mask) | val;
|
|
W_REG(sii->osh, r, w);
|
|
}
|
|
|
|
/* readback */
|
|
w = R_REG(sii->osh, r);
|
|
|
|
if (!fast) {
|
|
/* restore core index */
|
|
if (origidx != coreidx)
|
|
ai_setcoreidx(&sii->pub, origidx);
|
|
|
|
INTR_RESTORE(sii, intr_val);
|
|
}
|
|
|
|
return (w);
|
|
}
|
|
|
|
void
|
|
ai_core_disable(si_t *sih, uint32 bits)
|
|
{
|
|
si_info_t *sii;
|
|
volatile uint32 dummy;
|
|
aidmp_t *ai;
|
|
|
|
sii = SI_INFO(sih);
|
|
|
|
ASSERT(GOODREGS(sii->curwrap));
|
|
ai = sii->curwrap;
|
|
|
|
/* if core is already in reset, just return */
|
|
if (R_REG(sii->osh, &ai->resetctrl) & AIRC_RESET)
|
|
return;
|
|
|
|
W_REG(sii->osh, &ai->ioctrl, bits);
|
|
dummy = R_REG(sii->osh, &ai->ioctrl);
|
|
OSL_DELAY(10);
|
|
|
|
W_REG(sii->osh, &ai->resetctrl, AIRC_RESET);
|
|
OSL_DELAY(1);
|
|
}
|
|
|
|
/* reset and re-enable a core
|
|
* inputs:
|
|
* bits - core specific bits that are set during and after reset sequence
|
|
* resetbits - core specific bits that are set only during reset sequence
|
|
*/
|
|
void
|
|
ai_core_reset(si_t *sih, uint32 bits, uint32 resetbits)
|
|
{
|
|
si_info_t *sii;
|
|
aidmp_t *ai;
|
|
volatile uint32 dummy;
|
|
|
|
sii = SI_INFO(sih);
|
|
ASSERT(GOODREGS(sii->curwrap));
|
|
ai = sii->curwrap;
|
|
|
|
/*
|
|
* Must do the disable sequence first to work for arbitrary current core state.
|
|
*/
|
|
ai_core_disable(sih, (bits | resetbits));
|
|
|
|
/*
|
|
* Now do the initialization sequence.
|
|
*/
|
|
W_REG(sii->osh, &ai->ioctrl, (bits | SICF_FGC | SICF_CLOCK_EN));
|
|
dummy = R_REG(sii->osh, &ai->ioctrl);
|
|
W_REG(sii->osh, &ai->resetctrl, 0);
|
|
OSL_DELAY(1);
|
|
|
|
W_REG(sii->osh, &ai->ioctrl, (bits | SICF_CLOCK_EN));
|
|
dummy = R_REG(sii->osh, &ai->ioctrl);
|
|
OSL_DELAY(1);
|
|
}
|
|
|
|
|
|
void
|
|
ai_core_cflags_wo(si_t *sih, uint32 mask, uint32 val)
|
|
{
|
|
si_info_t *sii;
|
|
aidmp_t *ai;
|
|
uint32 w;
|
|
|
|
sii = SI_INFO(sih);
|
|
ASSERT(GOODREGS(sii->curwrap));
|
|
ai = sii->curwrap;
|
|
|
|
ASSERT((val & ~mask) == 0);
|
|
|
|
if (mask || val) {
|
|
w = ((R_REG(sii->osh, &ai->ioctrl) & ~mask) | val);
|
|
W_REG(sii->osh, &ai->ioctrl, w);
|
|
}
|
|
}
|
|
|
|
uint32
|
|
ai_core_cflags(si_t *sih, uint32 mask, uint32 val)
|
|
{
|
|
si_info_t *sii;
|
|
aidmp_t *ai;
|
|
uint32 w;
|
|
|
|
sii = SI_INFO(sih);
|
|
ASSERT(GOODREGS(sii->curwrap));
|
|
ai = sii->curwrap;
|
|
|
|
ASSERT((val & ~mask) == 0);
|
|
|
|
if (mask || val) {
|
|
w = ((R_REG(sii->osh, &ai->ioctrl) & ~mask) | val);
|
|
W_REG(sii->osh, &ai->ioctrl, w);
|
|
}
|
|
|
|
return R_REG(sii->osh, &ai->ioctrl);
|
|
}
|
|
|
|
uint32
|
|
ai_core_sflags(si_t *sih, uint32 mask, uint32 val)
|
|
{
|
|
si_info_t *sii;
|
|
aidmp_t *ai;
|
|
uint32 w;
|
|
|
|
sii = SI_INFO(sih);
|
|
ASSERT(GOODREGS(sii->curwrap));
|
|
ai = sii->curwrap;
|
|
|
|
ASSERT((val & ~mask) == 0);
|
|
ASSERT((mask & ~SISF_CORE_BITS) == 0);
|
|
|
|
if (mask || val) {
|
|
w = ((R_REG(sii->osh, &ai->iostatus) & ~mask) | val);
|
|
W_REG(sii->osh, &ai->iostatus, w);
|
|
}
|
|
|
|
return R_REG(sii->osh, &ai->iostatus);
|
|
}
|