87 lines
2.8 KiB
C
87 lines
2.8 KiB
C
/* linux/arch/arm/mach-s3c24a0/include/mach/map.h
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*
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* Copyright 2003,2007 Simtec Electronics
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* http://armlinux.simtec.co.uk/
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* Ben Dooks <ben@simtec.co.uk>
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*
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* S3C24A0 - Memory map definitions
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARCH_24A0_MAP_H
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#define __ASM_ARCH_24A0_MAP_H __FILE__
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#include <plat/map-base.h>
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#include <plat/map.h>
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#define S3C24A0_PA_IO_BASE (0x40000000)
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#define S3C24A0_PA_CLKPWR (0x40000000)
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#define S3C24A0_PA_IRQ (0x40200000)
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#define S3C24A0_PA_DMA (0x40400000)
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#define S3C24A0_PA_MEMCTRL (0x40C00000)
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#define S3C24A0_PA_NAND (0x40C00000)
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#define S3C24A0_PA_SROM (0x40C20000)
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#define S3C24A0_PA_SDRAM (0x40C40000)
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#define S3C24A0_PA_BUSM (0x40CE0000)
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#define S3C24A0_PA_USBHOST (0x41000000)
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#define S3C24A0_PA_MODEMIF (0x41180000)
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#define S3C24A0_PA_IRDA (0x41800000)
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#define S3C24A0_PA_TIMER (0x44000000)
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#define S3C24A0_PA_WATCHDOG (0x44100000)
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#define S3C24A0_PA_RTC (0x44200000)
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#define S3C24A0_PA_UART (0x44400000)
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#define S3C24A0_PA_UART0 (S3C24A0_PA_UART)
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#define S3C24A0_PA_UART1 (S3C24A0_PA_UART + 0x4000)
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#define S3C24A0_PA_SPI (0x44500000)
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#define S3C24A0_PA_IIC (0x44600000)
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#define S3C24A0_PA_IIS (0x44700000)
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#define S3C24A0_PA_GPIO (0x44800000)
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#define S3C24A0_PA_KEYIF (0x44900000)
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#define S3C24A0_PA_USBDEV (0x44A00000)
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#define S3C24A0_PA_AC97 (0x45000000)
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#define S3C24A0_PA_ADC (0x45800000)
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#define S3C24A0_PA_SDI (0x46000000)
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#define S3C24A0_PA_MS (0x46100000)
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#define S3C24A0_PA_LCD (0x4A000000)
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#define S3C24A0_PA_VPOST (0x4A100000)
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/* physical addresses of all the chip-select areas */
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#define S3C24A0_CS0 (0x00000000)
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#define S3C24A0_CS1 (0x04000000)
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#define S3C24A0_CS2 (0x08000000)
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#define S3C24A0_CS3 (0x0C000000)
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#define S3C24A0_CS4 (0x10000000)
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#define S3C24A0_CS5 (0x40000000)
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#define S3C24A0_SDRAM_PA (S3C24A0_CS4)
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/* Use a single interface for common resources between S3C24XX cpus */
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#define S3C24XX_PA_IRQ S3C24A0_PA_IRQ
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#define S3C24XX_PA_MEMCTRL S3C24A0_PA_MEMCTRL
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#define S3C24XX_PA_USBHOST S3C24A0_PA_USBHOST
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#define S3C24XX_PA_DMA S3C24A0_PA_DMA
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#define S3C24XX_PA_CLKPWR S3C24A0_PA_CLKPWR
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#define S3C24XX_PA_LCD S3C24A0_PA_LCD
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#define S3C24XX_PA_UART S3C24A0_PA_UART
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#define S3C24XX_PA_TIMER S3C24A0_PA_TIMER
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#define S3C24XX_PA_USBDEV S3C24A0_PA_USBDEV
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#define S3C24XX_PA_WATCHDOG S3C24A0_PA_WATCHDOG
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#define S3C24XX_PA_IIS S3C24A0_PA_IIS
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#define S3C24XX_PA_GPIO S3C24A0_PA_GPIO
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#define S3C24XX_PA_RTC S3C24A0_PA_RTC
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#define S3C24XX_PA_ADC S3C24A0_PA_ADC
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#define S3C24XX_PA_SPI S3C24A0_PA_SPI
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#define S3C24XX_PA_SDI S3C24A0_PA_SDI
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#define S3C24XX_PA_NAND S3C24A0_PA_NAND
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#define S3C_PA_UART S3C24A0_PA_UART
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#define S3C_PA_IIC S3C24A0_PA_IIC
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#define S3C_PA_NAND S3C24XX_PA_NAND
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#endif /* __ASM_ARCH_24A0_MAP_H */
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