681 lines
19 KiB
C
681 lines
19 KiB
C
/* linux/arch/arm/mach-msm/irq.c
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*
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* Copyright (C) 2007 Google, Inc.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/sched.h>
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#include <linux/interrupt.h>
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#include <linux/ptrace.h>
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#include <linux/timer.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <asm/cacheflush.h>
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#include <mach/hardware.h>
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#include <mach/msm_iomap.h>
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#include <mach/fiq.h>
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#include "sirc.h"
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#include "smd_private.h"
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enum {
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IRQ_DEBUG_SLEEP_INT_TRIGGER = 1U << 0,
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IRQ_DEBUG_SLEEP_INT = 1U << 1,
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IRQ_DEBUG_SLEEP_ABORT = 1U << 2,
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IRQ_DEBUG_SLEEP = 1U << 3,
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IRQ_DEBUG_SLEEP_REQUEST = 1U << 4,
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};
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static int msm_irq_debug_mask;
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module_param_named(debug_mask, msm_irq_debug_mask, int, S_IRUGO | S_IWUSR | S_IWGRP);
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#define VIC_REG(off) (MSM_VIC_BASE + (off))
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#if defined(CONFIG_ARCH_MSM7X30)
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#define VIC_INT_TO_REG_ADDR(base, irq) (base + (irq / 32) * 4)
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#define VIC_INT_TO_REG_INDEX(irq) ((irq >> 5) & 3)
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#else
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#define VIC_INT_TO_REG_ADDR(base, irq) (base + ((irq & 32) ? 4 : 0))
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#define VIC_INT_TO_REG_INDEX(irq) ((irq >> 5) & 1)
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#endif
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#define VIC_INT_SELECT0 VIC_REG(0x0000) /* 1: FIQ, 0: IRQ */
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#define VIC_INT_SELECT1 VIC_REG(0x0004) /* 1: FIQ, 0: IRQ */
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#define VIC_INT_SELECT2 VIC_REG(0x0008) /* 1: FIQ, 0: IRQ */
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#define VIC_INT_SELECT3 VIC_REG(0x000C) /* 1: FIQ, 0: IRQ */
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#define VIC_INT_EN0 VIC_REG(0x0010)
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#define VIC_INT_EN1 VIC_REG(0x0014)
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#define VIC_INT_EN2 VIC_REG(0x0018)
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#define VIC_INT_EN3 VIC_REG(0x001C)
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#define VIC_INT_ENCLEAR0 VIC_REG(0x0020)
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#define VIC_INT_ENCLEAR1 VIC_REG(0x0024)
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#define VIC_INT_ENCLEAR2 VIC_REG(0x0028)
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#define VIC_INT_ENCLEAR3 VIC_REG(0x002C)
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#define VIC_INT_ENSET0 VIC_REG(0x0030)
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#define VIC_INT_ENSET1 VIC_REG(0x0034)
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#define VIC_INT_ENSET2 VIC_REG(0x0038)
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#define VIC_INT_ENSET3 VIC_REG(0x003C)
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#define VIC_INT_TYPE0 VIC_REG(0x0040) /* 1: EDGE, 0: LEVEL */
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#define VIC_INT_TYPE1 VIC_REG(0x0044) /* 1: EDGE, 0: LEVEL */
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#define VIC_INT_TYPE2 VIC_REG(0x0048) /* 1: EDGE, 0: LEVEL */
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#define VIC_INT_TYPE3 VIC_REG(0x004C) /* 1: EDGE, 0: LEVEL */
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#define VIC_INT_POLARITY0 VIC_REG(0x0050) /* 1: NEG, 0: POS */
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#define VIC_INT_POLARITY1 VIC_REG(0x0054) /* 1: NEG, 0: POS */
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#define VIC_INT_POLARITY2 VIC_REG(0x0058) /* 1: NEG, 0: POS */
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#define VIC_INT_POLARITY3 VIC_REG(0x005C) /* 1: NEG, 0: POS */
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#define VIC_NO_PEND_VAL VIC_REG(0x0060)
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#if defined(CONFIG_ARCH_MSM_SCORPION)
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#define VIC_NO_PEND_VAL_FIQ VIC_REG(0x0064)
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#define VIC_INT_MASTEREN VIC_REG(0x0068) /* 1: IRQ, 2: FIQ */
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#define VIC_CONFIG VIC_REG(0x006C) /* 1: USE SC VIC */
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#else
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#define VIC_INT_MASTEREN VIC_REG(0x0064) /* 1: IRQ, 2: FIQ */
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#define VIC_CONFIG VIC_REG(0x0068) /* 1: USE ARM1136 VIC */
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#define VIC_PROTECTION VIC_REG(0x006C) /* 1: ENABLE */
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#endif
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#define VIC_IRQ_STATUS0 VIC_REG(0x0080)
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#define VIC_IRQ_STATUS1 VIC_REG(0x0084)
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#define VIC_IRQ_STATUS2 VIC_REG(0x0088)
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#define VIC_IRQ_STATUS3 VIC_REG(0x008C)
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#define VIC_FIQ_STATUS0 VIC_REG(0x0090)
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#define VIC_FIQ_STATUS1 VIC_REG(0x0094)
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#define VIC_FIQ_STATUS2 VIC_REG(0x0098)
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#define VIC_FIQ_STATUS3 VIC_REG(0x009C)
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#define VIC_RAW_STATUS0 VIC_REG(0x00A0)
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#define VIC_RAW_STATUS1 VIC_REG(0x00A4)
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#define VIC_RAW_STATUS2 VIC_REG(0x00A8)
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#define VIC_RAW_STATUS3 VIC_REG(0x00AC)
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#define VIC_INT_CLEAR0 VIC_REG(0x00B0)
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#define VIC_INT_CLEAR1 VIC_REG(0x00B4)
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#define VIC_INT_CLEAR2 VIC_REG(0x00B8)
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#define VIC_INT_CLEAR3 VIC_REG(0x00BC)
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#define VIC_SOFTINT0 VIC_REG(0x00C0)
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#define VIC_SOFTINT1 VIC_REG(0x00C4)
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#define VIC_SOFTINT2 VIC_REG(0x00C8)
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#define VIC_SOFTINT3 VIC_REG(0x00CC)
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#define VIC_IRQ_VEC_RD VIC_REG(0x00D0) /* pending int # */
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#define VIC_IRQ_VEC_PEND_RD VIC_REG(0x00D4) /* pending vector addr */
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#define VIC_IRQ_VEC_WR VIC_REG(0x00D8)
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#if defined(CONFIG_ARCH_MSM_SCORPION)
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#define VIC_FIQ_VEC_RD VIC_REG(0x00DC)
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#define VIC_FIQ_VEC_PEND_RD VIC_REG(0x00E0)
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#define VIC_FIQ_VEC_WR VIC_REG(0x00E4)
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#define VIC_IRQ_IN_SERVICE VIC_REG(0x00E8)
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#define VIC_IRQ_IN_STACK VIC_REG(0x00EC)
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#define VIC_FIQ_IN_SERVICE VIC_REG(0x00F0)
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#define VIC_FIQ_IN_STACK VIC_REG(0x00F4)
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#define VIC_TEST_BUS_SEL VIC_REG(0x00F8)
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#define VIC_IRQ_CTRL_CONFIG VIC_REG(0x00FC)
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#else
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#define VIC_IRQ_IN_SERVICE VIC_REG(0x00E0)
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#define VIC_IRQ_IN_STACK VIC_REG(0x00E4)
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#define VIC_TEST_BUS_SEL VIC_REG(0x00E8)
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#endif
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#define VIC_VECTPRIORITY(n) VIC_REG(0x0200+((n) * 4))
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#define VIC_VECTADDR(n) VIC_REG(0x0400+((n) * 4))
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#if defined(CONFIG_ARCH_MSM7X30)
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#define VIC_NUM_REGS 4
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#else
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#define VIC_NUM_REGS 2
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#endif
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#if VIC_NUM_REGS == 2
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#define DPRINT_REGS(base_reg, format, ...) \
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printk(KERN_INFO format " %x %x\n", ##__VA_ARGS__, \
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readl(base_reg ## 0), readl(base_reg ## 1))
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#define DPRINT_ARRAY(array, format, ...) \
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printk(KERN_INFO format " %x %x\n", ##__VA_ARGS__, \
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array[0], array[1])
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#elif VIC_NUM_REGS == 4
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#define DPRINT_REGS(base_reg, format, ...) \
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printk(KERN_INFO format " %x %x %x %x\n", ##__VA_ARGS__, \
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readl(base_reg ## 0), readl(base_reg ## 1), \
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readl(base_reg ## 2), readl(base_reg ## 3))
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#define DPRINT_ARRAY(array, format, ...) \
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printk(KERN_INFO format " %x %x %x %x\n", ##__VA_ARGS__, \
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array[0], array[1], \
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array[2], array[3])
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#else
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#error "VIC_NUM_REGS set to illegal value"
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#endif
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static uint32_t msm_irq_smsm_wake_enable[2];
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static struct {
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uint32_t int_en[2];
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uint32_t int_type;
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uint32_t int_polarity;
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uint32_t int_select;
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} msm_irq_shadow_reg[VIC_NUM_REGS];
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static uint32_t msm_irq_idle_disable[VIC_NUM_REGS];
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#if defined(CONFIG_MSM_N_WAY_SMD)
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#define INT_INFO_SMSM_ID SMEM_APPS_DEM_SLAVE_DATA
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struct msm_dem_slave_data *smsm_int_info;
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#else
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#define INT_INFO_SMSM_ID SMEM_SMSM_INT_INFO
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struct smsm_interrupt_info *smsm_int_info;
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#endif
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#define SMSM_FAKE_IRQ (0xff)
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static uint8_t msm_irq_to_smsm[NR_MSM_IRQS + NR_SIRC_IRQS] = {
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[INT_MDDI_EXT] = 1,
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[INT_MDDI_PRI] = 2,
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[INT_MDDI_CLIENT] = 3,
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[INT_USB_OTG] = 4,
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/* [INT_PWB_I2C] = 5 -- not usable */
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[INT_SDC1_0] = 6,
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[INT_SDC1_1] = 7,
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[INT_SDC2_0] = 8,
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[INT_SDC2_1] = 9,
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[INT_ADSP_A9_A11] = 10,
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[INT_UART1] = 11,
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[INT_UART2] = 12,
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[INT_UART3] = 13,
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[INT_UART1_RX] = 14,
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[INT_UART2_RX] = 15,
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[INT_UART3_RX] = 16,
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[INT_UART1DM_IRQ] = 17,
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[INT_UART1DM_RX] = 18,
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[INT_KEYSENSE] = 19,
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#if !defined(CONFIG_ARCH_MSM7X30)
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[INT_AD_HSSD] = 20,
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#endif
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[INT_NAND_WR_ER_DONE] = 21,
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[INT_NAND_OP_DONE] = 22,
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[INT_TCHSCRN1] = 23,
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[INT_TCHSCRN2] = 24,
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[INT_TCHSCRN_SSBI] = 25,
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[INT_USB_HS] = 26,
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[INT_UART2DM_RX] = 27,
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[INT_UART2DM_IRQ] = 28,
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[INT_SDC4_1] = 29,
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[INT_SDC4_0] = 30,
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[INT_SDC3_1] = 31,
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[INT_SDC3_0] = 32,
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/* fake wakeup interrupts */
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[INT_GPIO_GROUP1] = SMSM_FAKE_IRQ,
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[INT_GPIO_GROUP2] = SMSM_FAKE_IRQ,
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[INT_A9_M2A_0] = SMSM_FAKE_IRQ,
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[INT_A9_M2A_1] = SMSM_FAKE_IRQ,
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[INT_A9_M2A_5] = SMSM_FAKE_IRQ,
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[INT_GP_TIMER_EXP] = SMSM_FAKE_IRQ,
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[INT_DEBUG_TIMER_EXP] = SMSM_FAKE_IRQ,
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[INT_ADSP_A11] = SMSM_FAKE_IRQ,
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#ifdef CONFIG_ARCH_QSD8X50
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[INT_SIRC_0] = SMSM_FAKE_IRQ,
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[INT_SIRC_1] = SMSM_FAKE_IRQ,
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#endif
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};
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static inline void msm_irq_write_all_regs(void __iomem *base, unsigned int val)
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{
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int i;
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/* the address must be continue */
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for (i = 0; i < VIC_NUM_REGS; i++)
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writel(val, base + (i * 4));
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}
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static void msm_irq_ack(unsigned int irq)
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{
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void __iomem *reg = VIC_INT_TO_REG_ADDR(VIC_INT_CLEAR0, irq);
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irq = 1 << (irq & 31);
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writel(irq, reg);
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}
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static void msm_irq_mask(unsigned int irq)
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{
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void __iomem *reg = VIC_INT_TO_REG_ADDR(VIC_INT_ENCLEAR0, irq);
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unsigned index = VIC_INT_TO_REG_INDEX(irq);
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uint32_t mask = 1UL << (irq & 31);
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int smsm_irq = msm_irq_to_smsm[irq];
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msm_irq_shadow_reg[index].int_en[0] &= ~mask;
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writel(mask, reg);
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if (smsm_irq == 0)
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msm_irq_idle_disable[index] &= ~mask;
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else {
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mask = 1UL << (smsm_irq - 1);
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msm_irq_smsm_wake_enable[0] &= ~mask;
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}
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}
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static void msm_irq_unmask(unsigned int irq)
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{
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void __iomem *reg = VIC_INT_TO_REG_ADDR(VIC_INT_ENSET0, irq);
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unsigned index = VIC_INT_TO_REG_INDEX(irq);
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uint32_t mask = 1UL << (irq & 31);
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int smsm_irq = msm_irq_to_smsm[irq];
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msm_irq_shadow_reg[index].int_en[0] |= mask;
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writel(mask, reg);
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if (smsm_irq == 0)
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msm_irq_idle_disable[index] |= mask;
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else {
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mask = 1UL << (smsm_irq - 1);
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msm_irq_smsm_wake_enable[0] |= mask;
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}
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}
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static int msm_irq_set_wake(unsigned int irq, unsigned int on)
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{
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unsigned index = VIC_INT_TO_REG_INDEX(irq);
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uint32_t mask = 1UL << (irq & 31);
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int smsm_irq = msm_irq_to_smsm[irq];
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if (smsm_irq == 0) {
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printk(KERN_ERR "msm_irq_set_wake: bad wakeup irq %d\n", irq);
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return -EINVAL;
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}
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if (on)
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msm_irq_shadow_reg[index].int_en[1] |= mask;
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else
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msm_irq_shadow_reg[index].int_en[1] &= ~mask;
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if (smsm_irq == SMSM_FAKE_IRQ)
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return 0;
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mask = 1UL << (smsm_irq - 1);
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if (on)
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msm_irq_smsm_wake_enable[1] |= mask;
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else
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msm_irq_smsm_wake_enable[1] &= ~mask;
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return 0;
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}
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static int msm_irq_set_type(unsigned int irq, unsigned int flow_type)
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{
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void __iomem *treg = VIC_INT_TO_REG_ADDR(VIC_INT_TYPE0, irq);
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void __iomem *preg = VIC_INT_TO_REG_ADDR(VIC_INT_POLARITY0, irq);
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unsigned index = VIC_INT_TO_REG_INDEX(irq);
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int b = 1 << (irq & 31);
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uint32_t polarity;
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uint32_t type;
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polarity = msm_irq_shadow_reg[index].int_polarity;
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if (flow_type & (IRQF_TRIGGER_FALLING | IRQF_TRIGGER_LOW))
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polarity |= b;
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if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_HIGH))
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polarity &= ~b;
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writel(polarity, preg);
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msm_irq_shadow_reg[index].int_polarity = polarity;
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type = msm_irq_shadow_reg[index].int_type;
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if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
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type |= b;
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irq_desc[irq].handle_irq = handle_edge_irq;
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}
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if (flow_type & (IRQF_TRIGGER_HIGH | IRQF_TRIGGER_LOW)) {
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type &= ~b;
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irq_desc[irq].handle_irq = handle_level_irq;
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}
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writel(type, treg);
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msm_irq_shadow_reg[index].int_type = type;
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return 0;
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}
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int msm_irq_pending(void)
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{
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int i, pending = 0;
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/* the address must be continue */
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for (i = 0; (i < VIC_NUM_REGS) && !pending; i++)
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pending |= readl(VIC_IRQ_STATUS0 + (i * 4));
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return pending;
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}
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int msm_irq_idle_sleep_allowed(void)
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{
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int i, disable = 0;
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if (msm_irq_debug_mask & IRQ_DEBUG_SLEEP_REQUEST)
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DPRINT_ARRAY(msm_irq_idle_disable,
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"msm_irq_idle_sleep_allowed: disable");
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for (i = 0; i < VIC_NUM_REGS; i++)
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disable |= msm_irq_idle_disable[i];
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return !(disable || !smsm_int_info);
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}
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/* If arm9_wake is set: pass control to the other core.
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* If from_idle is not set: disable non-wakeup interrupts.
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*/
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void msm_irq_enter_sleep1(bool arm9_wake, int from_idle)
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{
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if (!arm9_wake || !smsm_int_info)
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return;
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smsm_int_info->interrupt_mask = msm_irq_smsm_wake_enable[!from_idle];
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smsm_int_info->pending_interrupts = 0;
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}
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int msm_irq_enter_sleep2(bool arm9_wake, int from_idle)
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{
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int i, limit = 10;
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uint32_t pending[VIC_NUM_REGS];
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if (from_idle && !arm9_wake)
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return 0;
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/* edge triggered interrupt may get lost if this mode is used */
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WARN_ON_ONCE(!arm9_wake && !from_idle);
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if (msm_irq_debug_mask & IRQ_DEBUG_SLEEP)
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DPRINT_REGS(VIC_IRQ_STATUS, "%s change irq, pend", __func__);
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for (i = 0; i < VIC_NUM_REGS; i++) {
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pending[i] = readl(VIC_IRQ_STATUS0 + (i * 4));
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pending[i] &= msm_irq_shadow_reg[i].int_en[!from_idle];
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}
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/* Clear INT_A9_M2A_5 since requesting sleep triggers it */
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pending[0] &= ~(1U << INT_A9_M2A_5);
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for (i = 0; i < VIC_NUM_REGS; i++) {
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if (pending[i]) {
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if (msm_irq_debug_mask & IRQ_DEBUG_SLEEP_ABORT)
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DPRINT_ARRAY(pending, "%s abort",
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__func__);
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return -EAGAIN;
|
|
}
|
|
}
|
|
|
|
msm_irq_write_all_regs(VIC_INT_EN0, 0);
|
|
|
|
while (limit-- > 0) {
|
|
int pend_irq;
|
|
int irq = readl(VIC_IRQ_VEC_RD);
|
|
if (irq == -1)
|
|
break;
|
|
pend_irq = readl(VIC_IRQ_VEC_PEND_RD);
|
|
if (msm_irq_debug_mask & IRQ_DEBUG_SLEEP_INT)
|
|
printk(KERN_INFO "msm_irq_enter_sleep cleared "
|
|
"int %d (%d)\n", irq, pend_irq);
|
|
}
|
|
|
|
if (arm9_wake) {
|
|
msm_irq_set_type(INT_A9_M2A_6, IRQF_TRIGGER_RISING);
|
|
msm_irq_ack(INT_A9_M2A_6);
|
|
writel(1U << INT_A9_M2A_6, VIC_INT_ENSET0);
|
|
} else {
|
|
for (i = 0; i < VIC_NUM_REGS; i++)
|
|
writel(msm_irq_shadow_reg[i].int_en[1],
|
|
VIC_INT_ENSET0 + (i * 4));
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
void msm_irq_exit_sleep1(void)
|
|
{
|
|
int i;
|
|
|
|
msm_irq_ack(INT_A9_M2A_6);
|
|
msm_irq_ack(INT_PWB_I2C);
|
|
for (i = 0; i < VIC_NUM_REGS; i++) {
|
|
writel(msm_irq_shadow_reg[i].int_type, VIC_INT_TYPE0 + i * 4);
|
|
writel(msm_irq_shadow_reg[i].int_polarity, VIC_INT_POLARITY0 + i * 4);
|
|
writel(msm_irq_shadow_reg[i].int_en[0], VIC_INT_EN0 + i * 4);
|
|
writel(msm_irq_shadow_reg[i].int_select, VIC_INT_SELECT0 + i * 4);
|
|
}
|
|
writel(3, VIC_INT_MASTEREN);
|
|
if (!smsm_int_info) {
|
|
printk(KERN_ERR "msm_irq_exit_sleep <SM NO INT_INFO>\n");
|
|
return;
|
|
}
|
|
if (msm_irq_debug_mask & IRQ_DEBUG_SLEEP)
|
|
printk(KERN_INFO "msm_irq_exit_sleep1 %x %x %x now %x %x\n",
|
|
smsm_int_info->interrupt_mask,
|
|
smsm_int_info->pending_interrupts,
|
|
smsm_int_info->wakeup_reason,
|
|
readl(VIC_IRQ_STATUS0), readl(VIC_IRQ_STATUS1));
|
|
}
|
|
|
|
void msm_irq_exit_sleep2(void)
|
|
{
|
|
int i;
|
|
uint32_t pending;
|
|
|
|
if (!smsm_int_info) {
|
|
printk(KERN_ERR "msm_irq_exit_sleep <SM NO INT_INFO>\n");
|
|
return;
|
|
}
|
|
if (msm_irq_debug_mask & IRQ_DEBUG_SLEEP)
|
|
printk(KERN_INFO "msm_irq_exit_sleep2 %x %x %x now %x %x\n",
|
|
smsm_int_info->interrupt_mask,
|
|
smsm_int_info->pending_interrupts,
|
|
smsm_int_info->wakeup_reason,
|
|
readl(VIC_IRQ_STATUS0), readl(VIC_IRQ_STATUS1));
|
|
pending = smsm_int_info->pending_interrupts;
|
|
for (i = 0; pending && i < ARRAY_SIZE(msm_irq_to_smsm); i++) {
|
|
unsigned reg_offset = (i & 32) ? 4 : 0;
|
|
uint32_t reg_mask = 1UL << (i & 31);
|
|
int smsm_irq = msm_irq_to_smsm[i];
|
|
uint32_t smsm_mask;
|
|
if (smsm_irq == 0)
|
|
continue;
|
|
smsm_mask = 1U << (smsm_irq - 1);
|
|
if (!(pending & smsm_mask))
|
|
continue;
|
|
pending &= ~smsm_mask;
|
|
if (msm_irq_debug_mask & IRQ_DEBUG_SLEEP_INT)
|
|
printk(KERN_INFO "msm_irq_exit_sleep2: irq %d "
|
|
"still pending %x now %x %x\n", i, pending,
|
|
readl(VIC_IRQ_STATUS0), readl(VIC_IRQ_STATUS1));
|
|
#if 0 /* debug intetrrupt trigger */
|
|
if (readl(VIC_IRQ_STATUS0 + reg_offset) & reg_mask)
|
|
writel(reg_mask, VIC_INT_CLEAR0 + reg_offset);
|
|
#endif
|
|
if (readl(VIC_IRQ_STATUS0 + reg_offset) & reg_mask)
|
|
continue;
|
|
writel(reg_mask, VIC_SOFTINT0 + reg_offset);
|
|
if (msm_irq_debug_mask & IRQ_DEBUG_SLEEP_INT_TRIGGER)
|
|
printk(KERN_INFO "msm_irq_exit_sleep2: irq %d need "
|
|
"trigger, now %x %x\n", i,
|
|
readl(VIC_IRQ_STATUS0), readl(VIC_IRQ_STATUS1));
|
|
}
|
|
}
|
|
|
|
void msm_irq_exit_sleep3(void)
|
|
{
|
|
if (!smsm_int_info) {
|
|
printk(KERN_ERR "msm_irq_exit_sleep <SM NO INT_INFO>\n");
|
|
return;
|
|
}
|
|
if (msm_irq_debug_mask & IRQ_DEBUG_SLEEP)
|
|
printk(KERN_INFO "msm_irq_exit_sleep3 %x %x %x now %x %x "
|
|
"state %x\n", smsm_int_info->interrupt_mask,
|
|
smsm_int_info->pending_interrupts,
|
|
smsm_int_info->wakeup_reason, readl(VIC_IRQ_STATUS0),
|
|
readl(VIC_IRQ_STATUS1),
|
|
smsm_get_state(SMSM_STATE_MODEM));
|
|
}
|
|
|
|
static struct irq_chip msm_irq_chip = {
|
|
.name = "msm",
|
|
.disable = msm_irq_mask,
|
|
.ack = msm_irq_ack,
|
|
.mask = msm_irq_mask,
|
|
.unmask = msm_irq_unmask,
|
|
.set_wake = msm_irq_set_wake,
|
|
.set_type = msm_irq_set_type,
|
|
};
|
|
|
|
void __init msm_init_irq(void)
|
|
{
|
|
unsigned n;
|
|
|
|
/* select level interrupts */
|
|
msm_irq_write_all_regs(VIC_INT_TYPE0, 0);
|
|
|
|
/* select highlevel interrupts */
|
|
msm_irq_write_all_regs(VIC_INT_POLARITY0, 0);
|
|
|
|
/* select IRQ for all INTs */
|
|
msm_irq_write_all_regs(VIC_INT_SELECT0, 0);
|
|
|
|
/* disable all INTs */
|
|
msm_irq_write_all_regs(VIC_INT_EN0, 0);
|
|
|
|
/* don't use 1136 vic */
|
|
writel(0, VIC_CONFIG);
|
|
|
|
/* enable interrupt controller */
|
|
writel(3, VIC_INT_MASTEREN);
|
|
|
|
for (n = 0; n < NR_MSM_IRQS; n++) {
|
|
set_irq_chip(n, &msm_irq_chip);
|
|
set_irq_handler(n, handle_level_irq);
|
|
set_irq_flags(n, IRQF_VALID);
|
|
}
|
|
|
|
msm_init_sirc();
|
|
}
|
|
|
|
static int __init msm_init_irq_late(void)
|
|
{
|
|
smsm_int_info = smem_alloc(INT_INFO_SMSM_ID, sizeof(*smsm_int_info));
|
|
if (!smsm_int_info)
|
|
pr_err("set_wakeup_mask NO INT_INFO (%d)\n", INT_INFO_SMSM_ID);
|
|
return 0;
|
|
}
|
|
late_initcall(msm_init_irq_late);
|
|
|
|
#if defined(CONFIG_MSM_FIQ_SUPPORT)
|
|
void msm_trigger_irq(int irq)
|
|
{
|
|
void __iomem *reg = VIC_INT_TO_REG_ADDR(VIC_SOFTINT0, irq);
|
|
uint32_t mask = 1UL << (irq & 31);
|
|
writel(mask, reg);
|
|
}
|
|
|
|
void msm_fiq_enable(int irq)
|
|
{
|
|
unsigned long flags;
|
|
local_irq_save(flags);
|
|
irq_desc[irq].chip->unmask(irq);
|
|
local_irq_restore(flags);
|
|
}
|
|
|
|
void msm_fiq_disable(int irq)
|
|
{
|
|
unsigned long flags;
|
|
local_irq_save(flags);
|
|
irq_desc[irq].chip->mask(irq);
|
|
local_irq_restore(flags);
|
|
}
|
|
|
|
static void _msm_fiq_select(int irq)
|
|
{
|
|
void __iomem *reg = VIC_INT_TO_REG_ADDR(VIC_INT_SELECT0, irq);
|
|
unsigned index = VIC_INT_TO_REG_INDEX(irq);
|
|
uint32_t mask = 1UL << (irq & 31);
|
|
unsigned long flags;
|
|
|
|
local_irq_save(flags);
|
|
msm_irq_shadow_reg[index].int_select |= mask;
|
|
writel(msm_irq_shadow_reg[index].int_select, reg);
|
|
local_irq_restore(flags);
|
|
}
|
|
|
|
static void _msm_fiq_unselect(int irq)
|
|
{
|
|
void __iomem *reg = VIC_INT_TO_REG_ADDR(VIC_INT_SELECT0, irq);
|
|
unsigned index = VIC_INT_TO_REG_INDEX(irq);
|
|
uint32_t mask = 1UL << (irq & 31);
|
|
unsigned long flags;
|
|
|
|
local_irq_save(flags);
|
|
msm_irq_shadow_reg[index].int_select &= (!mask);
|
|
writel(msm_irq_shadow_reg[index].int_select, reg);
|
|
local_irq_restore(flags);
|
|
}
|
|
|
|
void msm_fiq_select(int irq)
|
|
{
|
|
if (irq < FIRST_SIRC_IRQ)
|
|
_msm_fiq_select(irq);
|
|
else if (irq < FIRST_GPIO_IRQ)
|
|
sirc_fiq_select(irq, true);
|
|
else
|
|
pr_err("unsupported fiq %d", irq);
|
|
}
|
|
|
|
void msm_fiq_unselect(int irq)
|
|
{
|
|
if (irq < FIRST_SIRC_IRQ)
|
|
_msm_fiq_unselect(irq);
|
|
else if (irq < FIRST_GPIO_IRQ)
|
|
sirc_fiq_select(irq, false);
|
|
else
|
|
pr_err("unsupported fiq %d", irq);
|
|
}
|
|
|
|
/* set_fiq_handler originally from arch/arm/kernel/fiq.c */
|
|
static void set_fiq_handler(void *start, unsigned int length)
|
|
{
|
|
memcpy((void *)0xffff001c, start, length);
|
|
flush_icache_range(0xffff001c, 0xffff001c + length);
|
|
if (!vectors_high())
|
|
flush_icache_range(0x1c, 0x1c + length);
|
|
}
|
|
|
|
extern unsigned char fiq_glue, fiq_glue_end;
|
|
|
|
static void (*fiq_func)(void *data, void *regs, void *svc_sp);
|
|
static void *fiq_data;
|
|
static void *fiq_stack;
|
|
|
|
void fiq_glue_setup(void *func, void *data, void *sp);
|
|
|
|
int msm_fiq_set_handler(void (*func)(void *data, void *regs, void *svc_sp),
|
|
void *data)
|
|
{
|
|
unsigned long flags;
|
|
int ret = -ENOMEM;
|
|
|
|
if (!fiq_stack)
|
|
fiq_stack = kzalloc(THREAD_SIZE, GFP_KERNEL);
|
|
if (!fiq_stack)
|
|
return -ENOMEM;
|
|
|
|
local_irq_save(flags);
|
|
if (fiq_func == 0) {
|
|
fiq_func = func;
|
|
fiq_data = data;
|
|
fiq_glue_setup(func, data, fiq_stack + THREAD_START_SP);
|
|
set_fiq_handler(&fiq_glue, (&fiq_glue_end - &fiq_glue));
|
|
ret = 0;
|
|
}
|
|
local_irq_restore(flags);
|
|
return ret;
|
|
}
|
|
|
|
void msm_fiq_exit_sleep(void)
|
|
{
|
|
if (fiq_stack)
|
|
fiq_glue_setup(fiq_func, fiq_data, fiq_stack + THREAD_START_SP);
|
|
}
|
|
#endif
|