1897 lines
58 KiB
C
Executable File
1897 lines
58 KiB
C
Executable File
/* drivers/mtd/devices/board-htcleo-nand.c
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*
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* Copyright (C) 2010 Cotulla
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* Copyright (C) 2007 Google, Inc.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/partitions.h>
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#include <linux/platform_device.h>
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#include <linux/sched.h>
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#include <linux/dma-mapping.h>
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#include <linux/io.h>
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#include <linux/moduleparam.h>
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#include <linux/stat.h>
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#include <asm/dma.h>
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#include <asm/mach/flash.h>
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#include <mach/msm_iomap.h>
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#include <mach/dma.h>
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//#define ENABLE_FLASH_RW_DUMP 1
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//#define VERBOSE 1
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//#define ENABLE_ENTRY_TRACE 1
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//////////////////////////////////////////////////////////////////////////
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//
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// WARNING: This driver designed for HTC LEO (HD2) only.
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// It must not used in other devices, until you fully understand
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// what you are exactly doing...
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// Something like "Let try it and look" are not acceptable.
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// Otherwise you may brick your device.
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//
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// This driver supports only MTD_OOB_AUTO access to spare,
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// all other are not supported via lack of proper documentation
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// Basic goals was to make it support YAFFS2 only.
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//
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// YAFFS2 pass to this driver spare data amount more than 16 bytes (there unused ecc data)
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// this driver handle only first 16 bytes.
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//
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// -Cotulla
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//
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////////////////////////////////////////////////////////////////////////////
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#define MSM_NAND_BASE 0xA0A00000
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#define MSM_NAND_REG(off) (MSM_NAND_BASE + (off))
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#define MSM_NAND_FLASH_CMD MSM_NAND_REG(0x0000)
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#define MSM_NAND_ADDR0 MSM_NAND_REG(0x0004)
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#define MSM_NAND_ADDR1 MSM_NAND_REG(0x0008)
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#define MSM_NAND_FLASH_CHIP_SELECT MSM_NAND_REG(0x000C)
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#define MSM_NAND_EXEC_CMD MSM_NAND_REG(0x0010)
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#define MSM_NAND_FLASH_STATUS MSM_NAND_REG(0x0014)
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#define MSM_NAND_BUFFER_STATUS MSM_NAND_REG(0x0018)
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#define MSM_NAND_DEV0_CFG0 MSM_NAND_REG(0x0020)
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#define MSM_NAND_DEV0_CFG1 MSM_NAND_REG(0x0024)
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#define MSM_NAND_DEV1_CFG0 MSM_NAND_REG(0x0030)
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#define MSM_NAND_DEV1_CFG1 MSM_NAND_REG(0x0034)
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#define MSM_NAND_READ_ID MSM_NAND_REG(0x0040)
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#define MSM_NAND_READ_STATUS MSM_NAND_REG(0x0044)
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#define MSM_NAND_CONFIG_DATA MSM_NAND_REG(0x0050)
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#define MSM_NAND_CONFIG MSM_NAND_REG(0x0054)
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#define MSM_NAND_CONFIG_MODE MSM_NAND_REG(0x0058)
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#define MSM_NAND_CONFIG_STATUS MSM_NAND_REG(0x0060)
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#define MSM_NAND_MACRO1_REG MSM_NAND_REG(0x0064)
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#define MSM_NAND_XFR_STEP1 MSM_NAND_REG(0x0070)
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#define MSM_NAND_XFR_STEP2 MSM_NAND_REG(0x0074)
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#define MSM_NAND_XFR_STEP3 MSM_NAND_REG(0x0078)
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#define MSM_NAND_XFR_STEP4 MSM_NAND_REG(0x007C)
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#define MSM_NAND_XFR_STEP5 MSM_NAND_REG(0x0080)
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#define MSM_NAND_XFR_STEP6 MSM_NAND_REG(0x0084)
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#define MSM_NAND_XFR_STEP7 MSM_NAND_REG(0x0088)
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#define MSM_NAND_DEV_CMD0 MSM_NAND_REG(0x00A0)
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#define MSM_NAND_DEV_CMD1 MSM_NAND_REG(0x00A4)
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#define MSM_NAND_DEV_CMD2 MSM_NAND_REG(0x00A8)
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#define MSM_NAND_DEV_CMD_VLD MSM_NAND_REG(0x00AC)
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#define MSM_NAND_EBI2_MISR_SIG_REG MSM_NAND_REG(0x00B0)
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#define MSM_NAND_EBI2_ECC_BUF_CFG MSM_NAND_REG(0x00F0)
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#define MSM_NAND_FLASH_BUFFER MSM_NAND_REG(0x0100)
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/* device commands */
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#define MSM_NAND_CMD_SOFT_RESET 0x01
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#define MSM_NAND_CMD_PAGE_READ 0x32
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#define MSM_NAND_CMD_PAGE_READ_ECC 0x33
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#define MSM_NAND_CMD_PAGE_READ_ALL 0x34
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#define MSM_NAND_CMD_SEQ_PAGE_READ 0x15
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#define MSM_NAND_CMD_PRG_PAGE 0x36
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#define MSM_NAND_CMD_PRG_PAGE_ECC 0x37
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#define MSM_NAND_CMD_PRG_PAGE_ALL 0x39
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#define MSM_NAND_CMD_BLOCK_ERASE 0x3A
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#define MSM_NAND_CMD_FETCH_ID 0x0B
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#define MSM_NAND_CMD_STATUS 0x0C
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#define MSM_NAND_CMD_RESET 0x0D
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//////////////////////////////////////////////////////////////////////////
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#define MSM_NAND_DMA_BUFFER_SIZE SZ_4K
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#define MSM_NAND_DMA_BUFFER_SLOTS \
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(MSM_NAND_DMA_BUFFER_SIZE / (sizeof(((atomic_t *)0)->counter) * 8))
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#define MSM_NAND_CFG0_RAW 0xA80420C0
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#define MSM_NAND_CFG1_RAW 0x5045D
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#define SUPPORT_WRONG_ECC_CONFIG 1
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#define IGNORE_ARM9_CONFIG 0
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static struct nand_hw_info *nand_info;
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struct nand_hw_info
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{
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uint32_t flash_id;
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uint8_t maker_id;
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uint8_t maker_name[10];
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uint8_t width;
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uint32_t size;
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uint32_t block_count;
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uint32_t page_count;
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uint32_t page_size;
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};
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struct msm_nand_chip {
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struct device *dev;
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wait_queue_head_t wait_queue;
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atomic_t dma_buffer_busy;
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unsigned dma_channel;
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uint8_t *dma_buffer;
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dma_addr_t dma_addr;
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unsigned CFG0, CFG1;
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#if SUPPORT_WRONG_ECC_CONFIG
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uint32_t ecc_buf_cfg;
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uint32_t saved_ecc_buf_cfg;
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#endif
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struct nand_hw_info dev_info;
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};
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#define CFG1_WIDE_FLASH (1U << 1)
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/* TODO: move datamover code out */
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#define SRC_CRCI_NAND_CMD CMD_SRC_CRCI(DMOV_NAND_CRCI_CMD)
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#define DST_CRCI_NAND_CMD CMD_DST_CRCI(DMOV_NAND_CRCI_CMD)
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#define SRC_CRCI_NAND_DATA CMD_SRC_CRCI(DMOV_NAND_CRCI_DATA)
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#define DST_CRCI_NAND_DATA CMD_DST_CRCI(DMOV_NAND_CRCI_DATA)
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#define msm_virt_to_dma(chip, vaddr) \
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((void)(*(vaddr)), (chip)->dma_addr + \
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((uint8_t *)(vaddr) - (chip)->dma_buffer))
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/**
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* msm_nand_oob_64 - oob info for 2KB page
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*/
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// Cotulla: this table is fake, but who cares?
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// without deep msm nand understanding and deep understanding of this driver this information is nothing.
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static struct nand_ecclayout msm_nand_oob_64 =
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{
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.eccbytes = 40,
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.eccpos = {
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0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
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10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
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20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
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46, 47, 48, 49, 50, 51, 52, 53, 54, 55,
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},
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.oobavail = 16,
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.oobfree = {
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{30, 16},
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}
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};
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struct flash_identification {
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uint32_t flash_id;
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uint32_t mask;
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uint32_t density;
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uint32_t widebus;
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uint32_t pagesize;
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uint32_t blksize;
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uint32_t oobsize;
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};
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static struct flash_identification supported_flash[] =
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{
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/* Flash ID ID Mask Density(MB) Wid Pgsz Blksz oobsz Manuf */
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{0x00000000, 0xFFFFFFFF, 0, 0, 0, 0, 0, }, /*ONFI*/
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{0x1500aaec, 0xFF00FFFF, (256<<20), 0, 2048, (2048<<6), 64, }, /*Samsung 2Gbit*/
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{0x5500baec, 0xFF00FFFF, (256<<20), 1, 2048, (2048<<6), 64, }, /*Samsung 2Gbit*/
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{0x6600bcec, 0xFF00FFFF, (512<<20), 1, 4096, (4096<<6), 128,}, /*Samsung 4Gbit 4K Page*/
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{0x0000aaec, 0x0000FFFF, (256<<20), 1, 2048, (2048<<6), 64, }, /*Samsung 2Gbit*/
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{0x0000acec, 0x0000FFFF, (512<<20), 1, 2048, (2048<<6), 64, }, /*Samsung 4Gbit*/
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{0x0000bcec, 0x0000FFFF, (512<<20), 1, 2048, (2048<<6), 64, }, /*Samsung 4Gbit*/
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{0x6601b3ec, 0xFFFFFFFF, (1024<<20),1, 4096, (4096<<6), 128,}, /*Samsung 8Gbit 4Kpage*/
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{0x0000b3ec, 0x0000FFFF, (1024<<20),1, 2048, (2048<<6), 64, }, /*Samsung 8Gbit*/
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{0x1500aa98, 0xFFFFFFFF, (256<<20), 0, 2048, (2048<<6), 64, }, /*Toshiba 2Gbit*/
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{0x5500ba98, 0xFFFFFFFF, (256<<20), 1, 2048, (2048<<6), 64, }, /*Toshiba 2Gbit*/
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{0xd580b12c, 0xFFFFFFFF, (128<<20), 1, 2048, (2048<<6), 64, }, /*Micron 1Gbit*/
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{0x0000ba2c, 0x0000FFFF, (256<<20), 1, 2048, (2048<<6), 64, }, /*Micron 2Gbit*/
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{0x0000bc2c, 0x0000FFFF, (512<<20), 1, 2048, (2048<<6), 64, }, /*Micron 4Gbit*/
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{0x0000b32c, 0x0000FFFF, (1024<<20),1, 2048, (2048<<6), 64, }, /*Micron 8Gbit*/
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{0x0000baad, 0x0000FFFF, (256<<20), 1, 2048, (2048<<6), 64, }, /*Hynix 2Gbit*/
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{0x0000bcad, 0x0000FFFF, (512<<20), 1, 2048, (2048<<6), 64, }, /*Hynix 4Gbit*/
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{0x0000b3ad, 0x0000FFFF, (1024<<20),1, 2048, (2048<<6), 64, }, /*Hynix 8Gbit*/
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/* Note: Width flag is 0 for 8 bit Flash and 1 for 16 bit flash */
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/* Note: The First row will be filled at runtime during ONFI probe */
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};
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static void *msm_nand_get_dma_buffer(struct msm_nand_chip *chip, size_t size)
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{
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unsigned int bitmask, free_bitmask, old_bitmask;
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unsigned int need_mask, current_need_mask;
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int free_index;
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need_mask = (1UL << DIV_ROUND_UP(size, MSM_NAND_DMA_BUFFER_SLOTS)) - 1;
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bitmask = atomic_read(&chip->dma_buffer_busy);
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free_bitmask = ~bitmask;
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do {
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free_index = __ffs(free_bitmask);
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current_need_mask = need_mask << free_index;
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if ((bitmask & current_need_mask) == 0) {
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old_bitmask =
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atomic_cmpxchg(&chip->dma_buffer_busy,
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bitmask,
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bitmask | current_need_mask);
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if (old_bitmask == bitmask)
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return chip->dma_buffer +
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free_index * MSM_NAND_DMA_BUFFER_SLOTS;
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free_bitmask = 0; /* force return */
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}
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/* current free range was too small, clear all free bits */
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/* below the top busy bit within current_need_mask */
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free_bitmask &=
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~(~0U >> (32 - fls(bitmask & current_need_mask)));
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} while (free_bitmask);
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return NULL;
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}
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static void msm_nand_release_dma_buffer(struct msm_nand_chip *chip,
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void *buffer, size_t size)
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{
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int index;
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unsigned int used_mask;
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used_mask = (1UL << DIV_ROUND_UP(size, MSM_NAND_DMA_BUFFER_SLOTS)) - 1;
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index = ((uint8_t *)buffer - chip->dma_buffer) /
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MSM_NAND_DMA_BUFFER_SLOTS;
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atomic_sub(used_mask << index, &chip->dma_buffer_busy);
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wake_up(&chip->wait_queue);
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}
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uint32_t flash_read_id(struct msm_nand_chip *chip)
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{
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struct {
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dmov_s cmd[5];
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unsigned cmdptr;
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unsigned data[5];
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} *dma_buffer;
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uint32_t rv;
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wait_event(chip->wait_queue,
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(dma_buffer = msm_nand_get_dma_buffer(
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chip, sizeof(*dma_buffer))));
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dma_buffer->data[0] = 0 | 4;
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dma_buffer->data[1] = MSM_NAND_CMD_FETCH_ID;
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dma_buffer->data[2] = 1;
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dma_buffer->data[3] = 0xeeeeeeee;
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dma_buffer->data[4] = 0xeeeeeeee;
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BUILD_BUG_ON(4 != ARRAY_SIZE(dma_buffer->data) - 1);
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dma_buffer->cmd[0].cmd = 0 | CMD_OCB;
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dma_buffer->cmd[0].src = msm_virt_to_dma(chip, &dma_buffer->data[0]);
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dma_buffer->cmd[0].dst = MSM_NAND_FLASH_CHIP_SELECT;
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dma_buffer->cmd[0].len = 4;
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dma_buffer->cmd[1].cmd = DST_CRCI_NAND_CMD;
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dma_buffer->cmd[1].src = msm_virt_to_dma(chip, &dma_buffer->data[1]);
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dma_buffer->cmd[1].dst = MSM_NAND_FLASH_CMD;
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dma_buffer->cmd[1].len = 4;
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dma_buffer->cmd[2].cmd = 0;
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dma_buffer->cmd[2].src = msm_virt_to_dma(chip, &dma_buffer->data[2]);
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dma_buffer->cmd[2].dst = MSM_NAND_EXEC_CMD;
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dma_buffer->cmd[2].len = 4;
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dma_buffer->cmd[3].cmd = SRC_CRCI_NAND_DATA;
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dma_buffer->cmd[3].src = MSM_NAND_FLASH_STATUS;
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dma_buffer->cmd[3].dst = msm_virt_to_dma(chip, &dma_buffer->data[3]);
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dma_buffer->cmd[3].len = 4;
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dma_buffer->cmd[4].cmd = CMD_OCU | CMD_LC;
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dma_buffer->cmd[4].src = MSM_NAND_READ_ID;
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dma_buffer->cmd[4].dst = msm_virt_to_dma(chip, &dma_buffer->data[4]);
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dma_buffer->cmd[4].len = 4;
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BUILD_BUG_ON(4 != ARRAY_SIZE(dma_buffer->cmd) - 1);
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dma_buffer->cmdptr =
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(msm_virt_to_dma(chip, dma_buffer->cmd) >> 3) | CMD_PTR_LP;
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dsb();
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msm_dmov_exec_cmd(
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chip->dma_channel, DMOV_CMD_PTR_LIST |
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DMOV_CMD_ADDR(msm_virt_to_dma(chip, &dma_buffer->cmdptr)));
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dsb();
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pr_info("status: %x\n", dma_buffer->data[3]);
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pr_info("nandid: %x maker %02x device %02x\n",
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dma_buffer->data[4], dma_buffer->data[4] & 0xff,
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(dma_buffer->data[4] >> 8) & 0xff);
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rv = dma_buffer->data[4];
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msm_nand_release_dma_buffer(chip, dma_buffer, sizeof(*dma_buffer));
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return rv;
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}
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int flash_read_config(struct msm_nand_chip *chip)
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{
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struct {
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dmov_s cmd[2];
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unsigned cmdptr;
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unsigned cfg0;
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unsigned cfg1;
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} *dma_buffer;
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wait_event(chip->wait_queue,
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(dma_buffer = msm_nand_get_dma_buffer(
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chip, sizeof(*dma_buffer))));
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dma_buffer->cfg0 = 0;
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dma_buffer->cfg1 = 0;
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dma_buffer->cmd[0].cmd = CMD_OCB;
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dma_buffer->cmd[0].src = MSM_NAND_DEV0_CFG0;
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dma_buffer->cmd[0].dst = msm_virt_to_dma(chip, &dma_buffer->cfg0);
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dma_buffer->cmd[0].len = 4;
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dma_buffer->cmd[1].cmd = CMD_OCU | CMD_LC;
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dma_buffer->cmd[1].src = MSM_NAND_DEV0_CFG1;
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dma_buffer->cmd[1].dst = msm_virt_to_dma(chip, &dma_buffer->cfg1);
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dma_buffer->cmd[1].len = 4;
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BUILD_BUG_ON(1 != ARRAY_SIZE(dma_buffer->cmd) - 1);
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dma_buffer->cmdptr =
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(msm_virt_to_dma(chip, dma_buffer->cmd) >> 3) | CMD_PTR_LP;
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dsb();
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msm_dmov_exec_cmd(
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chip->dma_channel, DMOV_CMD_PTR_LIST |
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DMOV_CMD_ADDR(msm_virt_to_dma(chip, &dma_buffer->cmdptr)));
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dsb();
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chip->CFG0 = dma_buffer->cfg0;
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chip->CFG1 = dma_buffer->cfg1;
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pr_info("msm_nand: read CFG0 = %x, CFG1 = %x\n", chip->CFG0, chip->CFG1);
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msm_nand_release_dma_buffer(chip, dma_buffer, sizeof(*dma_buffer));
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if ((chip->CFG0 == 0) || (chip->CFG1 == 0))
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return -1;
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return 0;
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}
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unsigned flash_rd_reg(struct msm_nand_chip *chip, unsigned addr)
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{
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struct {
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dmov_s cmd;
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unsigned cmdptr;
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unsigned data;
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} *dma_buffer;
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unsigned rv;
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wait_event(chip->wait_queue,
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(dma_buffer = msm_nand_get_dma_buffer(
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chip, sizeof(*dma_buffer))));
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dma_buffer->cmd.cmd = CMD_LC;
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dma_buffer->cmd.src = addr;
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dma_buffer->cmd.dst = msm_virt_to_dma(chip, &dma_buffer->data);
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dma_buffer->cmd.len = 4;
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dma_buffer->cmdptr =
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(msm_virt_to_dma(chip, &dma_buffer->cmd) >> 3) | CMD_PTR_LP;
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dma_buffer->data = 0xeeeeeeee;
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dsb();
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msm_dmov_exec_cmd(
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chip->dma_channel, DMOV_CMD_PTR_LIST |
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DMOV_CMD_ADDR(msm_virt_to_dma(chip, &dma_buffer->cmdptr)));
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dsb();
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rv = dma_buffer->data;
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msm_nand_release_dma_buffer(chip, dma_buffer, sizeof(*dma_buffer));
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return rv;
|
|
}
|
|
|
|
void flash_wr_reg(struct msm_nand_chip *chip, unsigned addr, unsigned val)
|
|
{
|
|
struct {
|
|
dmov_s cmd;
|
|
unsigned cmdptr;
|
|
unsigned data;
|
|
} *dma_buffer;
|
|
|
|
wait_event(chip->wait_queue,
|
|
(dma_buffer = msm_nand_get_dma_buffer(
|
|
chip, sizeof(*dma_buffer))));
|
|
|
|
dma_buffer->cmd.cmd = CMD_LC;
|
|
dma_buffer->cmd.src = msm_virt_to_dma(chip, &dma_buffer->data);
|
|
dma_buffer->cmd.dst = addr;
|
|
dma_buffer->cmd.len = 4;
|
|
|
|
dma_buffer->cmdptr =
|
|
(msm_virt_to_dma(chip, &dma_buffer->cmd) >> 3) | CMD_PTR_LP;
|
|
dma_buffer->data = val;
|
|
|
|
dsb();
|
|
msm_dmov_exec_cmd(
|
|
chip->dma_channel, DMOV_CMD_PTR_LIST |
|
|
DMOV_CMD_ADDR(msm_virt_to_dma(chip, &dma_buffer->cmdptr)));
|
|
dsb();
|
|
|
|
msm_nand_release_dma_buffer(chip, dma_buffer, sizeof(*dma_buffer));
|
|
}
|
|
|
|
static dma_addr_t
|
|
msm_nand_dma_map(struct device *dev, void *addr, size_t size,
|
|
enum dma_data_direction dir)
|
|
{
|
|
struct page *page;
|
|
unsigned long offset = (unsigned long)addr & ~PAGE_MASK;
|
|
if (virt_addr_valid(addr))
|
|
page = virt_to_page(addr);
|
|
else {
|
|
if (WARN_ON(size + offset > PAGE_SIZE))
|
|
return ~0;
|
|
page = vmalloc_to_page(addr);
|
|
}
|
|
return dma_map_page(dev, page, offset, size, dir);
|
|
}
|
|
|
|
static int msm_nand_read_oob(struct mtd_info *mtd, loff_t from, struct mtd_oob_ops *ops)
|
|
{
|
|
struct msm_nand_chip *chip = mtd->priv;
|
|
|
|
struct
|
|
{
|
|
dmov_s cmd[8 * 5 + 3];
|
|
unsigned cmdptr;
|
|
struct {
|
|
uint32_t cmd;
|
|
uint32_t addr0;
|
|
uint32_t addr1;
|
|
uint32_t chipsel;
|
|
uint32_t cfg0;
|
|
uint32_t cfg1;
|
|
uint32_t exec;
|
|
#if SUPPORT_WRONG_ECC_CONFIG
|
|
uint32_t ecccfg;
|
|
uint32_t ecccfg_restore;
|
|
#endif
|
|
struct {
|
|
uint32_t flash_status;
|
|
uint32_t buffer_status;
|
|
} result[8];
|
|
} data;
|
|
} *dma_buffer;
|
|
dmov_s *cmd;
|
|
unsigned n;
|
|
unsigned page = 0;
|
|
uint32_t oob_len;
|
|
uint32_t sectordatasize;
|
|
uint32_t sectoroobsize;
|
|
int err, pageerr, rawerr;
|
|
dma_addr_t data_dma_addr = 0;
|
|
dma_addr_t oob_dma_addr = 0;
|
|
dma_addr_t data_dma_addr_curr = 0;
|
|
dma_addr_t oob_dma_addr_curr = 0;
|
|
uint32_t oob_col = 0;
|
|
unsigned page_count;
|
|
unsigned pages_read = 0;
|
|
unsigned start_sector = 0;
|
|
uint32_t ecc_errors;
|
|
uint32_t total_ecc_errors = 0;
|
|
unsigned cwperpage;
|
|
uint32_t oob_done_size = 0;
|
|
|
|
#ifdef ENABLE_ENTRY_TRACE
|
|
printk("+&&&nand_readoob&&&\n");
|
|
#endif
|
|
|
|
if (mtd->writesize == 2048)
|
|
page = from >> 11;
|
|
|
|
if (mtd->writesize == 4096)
|
|
page = from >> 12;
|
|
|
|
oob_len = ops->ooblen;
|
|
cwperpage = (mtd->writesize >> 9);
|
|
|
|
if (from & (mtd->writesize - 1))
|
|
{
|
|
pr_err("%s: unsupported from, 0x%llx\n", __func__, from);
|
|
return -EINVAL;
|
|
}
|
|
if (ops->datbuf != NULL && (ops->len % mtd->writesize) != 0)
|
|
{
|
|
/* when ops->datbuf is NULL, ops->len may refer to ooblen */
|
|
pr_err("%s: unsupported ops->len, %d\n", __func__, ops->len);
|
|
return -EINVAL;
|
|
}
|
|
if (ops->ooblen != 0 && ops->ooboffs != 0)
|
|
{
|
|
pr_err("%s: unsupported ops->ooboffs, %d\n", __func__, ops->ooboffs);
|
|
return -EINVAL;
|
|
}
|
|
|
|
// +Cotulla
|
|
if (ops->ooblen != 0 && ops->mode != MTD_OOB_AUTO)
|
|
{
|
|
pr_err("%s: unsupported ops->mode, %d\n", __func__, ops->mode);
|
|
return -EINVAL;
|
|
}
|
|
// -Cotulla
|
|
|
|
if (ops->oobbuf && !ops->datbuf)
|
|
{
|
|
// must be 16 or less, each cw have 4 bytes
|
|
page_count = ops->ooblen / mtd->oobavail;
|
|
if ((page_count == 0) && (ops->ooblen))
|
|
{
|
|
page_count = 1;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
page_count = ops->len / mtd->writesize;
|
|
}
|
|
|
|
#if 0 /* yaffs reads more oob data than it needs */
|
|
if (ops->ooblen >= sectoroobsize * 4)
|
|
{
|
|
pr_err("%s: unsupported ops->ooblen, %d\n", __func__, ops->ooblen);
|
|
return -EINVAL;
|
|
}
|
|
#endif
|
|
|
|
#ifdef ENABLE_ENTRY_TRACE
|
|
printk("msm_nand_read_oob [%d %08X] %08X %08X\n", (uint32_t)(from - 0x42c0000) / 0x800, (uint32_t)ops->len, (uint32_t)ops->datbuf, (uint32_t)ops
|
|
->oobbuf);
|
|
#endif
|
|
if (ops->datbuf)
|
|
{
|
|
/* memset(ops->datbuf, 0x55, ops->len); */
|
|
data_dma_addr_curr = data_dma_addr = msm_nand_dma_map(chip->dev, ops->datbuf, ops->len, DMA_FROM_DEVICE);
|
|
if (dma_mapping_error(chip->dev, data_dma_addr))
|
|
{
|
|
pr_err("msm_nand_read_oob: failed to get dma addr " "for %p\n", ops->datbuf);
|
|
return -EIO;
|
|
}
|
|
}
|
|
if (ops->oobbuf)
|
|
{
|
|
memset(ops->oobbuf, 0xff, ops->ooblen);
|
|
oob_dma_addr_curr = oob_dma_addr = msm_nand_dma_map(chip->dev, ops->oobbuf, ops->ooblen, DMA_BIDIRECTIONAL);
|
|
if (dma_mapping_error(chip->dev, oob_dma_addr))
|
|
{
|
|
pr_err("msm_nand_read_oob: failed to get dma addr for %p\n", ops->oobbuf); err = -EIO;
|
|
goto err_dma_map_oobbuf_failed;
|
|
}
|
|
}
|
|
|
|
wait_event(chip->wait_queue, (dma_buffer = msm_nand_get_dma_buffer(chip, sizeof(*dma_buffer))));
|
|
|
|
oob_col = start_sector * 0x210;
|
|
if (chip->CFG1 & CFG1_WIDE_FLASH)
|
|
oob_col >>= 1;
|
|
|
|
err = 0;
|
|
while (page_count-- > 0)
|
|
{
|
|
cmd = dma_buffer->cmd;
|
|
|
|
/* CMD / ADDR0 / ADDR1 / CHIPSEL program values */
|
|
dma_buffer->data.cmd = MSM_NAND_CMD_PAGE_READ_ALL;
|
|
dma_buffer->data.addr0 = (page << 16) | oob_col;
|
|
/* qc example is (page >> 16) && 0xff !? */
|
|
dma_buffer->data.addr1 = (page >> 16) & 0xff;
|
|
/* flash0 + undoc bit */
|
|
dma_buffer->data.chipsel = 0 | 4;
|
|
|
|
dma_buffer->data.cfg0 = (chip->CFG0 & ~(7U << 6)) | (((cwperpage-1) - start_sector) << 6);
|
|
dma_buffer->data.cfg1 = chip->CFG1;
|
|
|
|
/* GO bit for the EXEC register */
|
|
dma_buffer->data.exec = 1;
|
|
|
|
BUILD_BUG_ON(8 != ARRAY_SIZE(dma_buffer->data.result));
|
|
|
|
for (n = start_sector; n < cwperpage; n++)
|
|
{
|
|
/* flash + buffer status return words */
|
|
dma_buffer->data.result[n].flash_status = 0xeeeeeeee;
|
|
dma_buffer->data.result[n].buffer_status = 0xeeeeeeee;
|
|
|
|
/* block on cmd ready, then
|
|
* write CMD / ADDR0 / ADDR1 / CHIPSEL
|
|
* regs in a burst
|
|
*/
|
|
cmd->cmd = DST_CRCI_NAND_CMD;
|
|
cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.cmd);
|
|
cmd->dst = MSM_NAND_FLASH_CMD;
|
|
if (n == start_sector)
|
|
cmd->len = 16;
|
|
else
|
|
cmd->len = 4;
|
|
cmd++;
|
|
|
|
if (n == start_sector)
|
|
{
|
|
cmd->cmd = 0;
|
|
cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.cfg0);
|
|
cmd->dst = MSM_NAND_DEV0_CFG0;
|
|
cmd->len = 8;
|
|
cmd++;
|
|
#if SUPPORT_WRONG_ECC_CONFIG
|
|
if (chip->saved_ecc_buf_cfg != chip->ecc_buf_cfg)
|
|
{
|
|
dma_buffer->data.ecccfg = chip->ecc_buf_cfg;
|
|
cmd->cmd = 0;
|
|
cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.ecccfg);
|
|
cmd->dst = MSM_NAND_EBI2_ECC_BUF_CFG;
|
|
cmd->len = 4;
|
|
cmd++;
|
|
}
|
|
#endif
|
|
}
|
|
|
|
/* kick the execute register */
|
|
cmd->cmd = 0;
|
|
cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.exec);
|
|
cmd->dst = MSM_NAND_EXEC_CMD;
|
|
cmd->len = 4;
|
|
cmd++;
|
|
|
|
/* block on data ready, then
|
|
* read the status register
|
|
*/
|
|
cmd->cmd = SRC_CRCI_NAND_DATA;
|
|
cmd->src = MSM_NAND_FLASH_STATUS;
|
|
cmd->dst = msm_virt_to_dma(chip, &dma_buffer->data.result[n]);
|
|
/* MSM_NAND_FLASH_STATUS + MSM_NAND_BUFFER_STATUS */
|
|
cmd->len = 8;
|
|
cmd++;
|
|
|
|
/* read data block
|
|
* (only valid if status says success)
|
|
*/
|
|
if (ops->datbuf)
|
|
{
|
|
sectordatasize = 512; //(n < (cwperpage - 1)) ? 516 : (512 - ((cwperpage - 1) << 2));
|
|
cmd->cmd = 0;
|
|
cmd->src = MSM_NAND_FLASH_BUFFER;
|
|
cmd->dst = data_dma_addr_curr;
|
|
data_dma_addr_curr += sectordatasize;
|
|
cmd->len = sectordatasize;
|
|
cmd++;
|
|
}
|
|
// if (ops->oobbuf && (n == (cwperpage - 1) || ops->mode != MTD_OOB_AUTO))
|
|
if (ops->oobbuf && oob_done_size < 16)
|
|
{
|
|
cmd->cmd = 0;
|
|
|
|
cmd->src = MSM_NAND_FLASH_BUFFER + 522;
|
|
sectoroobsize = 4;
|
|
|
|
cmd->dst = oob_dma_addr_curr;
|
|
if (sectoroobsize < oob_len)
|
|
cmd->len = sectoroobsize;
|
|
else
|
|
cmd->len = oob_len;
|
|
oob_dma_addr_curr += cmd->len;
|
|
oob_done_size += cmd->len;
|
|
oob_len -= cmd->len;
|
|
if (cmd->len > 0)
|
|
cmd++;
|
|
}
|
|
}
|
|
#if SUPPORT_WRONG_ECC_CONFIG
|
|
if (chip->saved_ecc_buf_cfg != chip->ecc_buf_cfg)
|
|
{
|
|
dma_buffer->data.ecccfg_restore = chip->saved_ecc_buf_cfg;
|
|
cmd->cmd = 0;
|
|
cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.ecccfg_restore);
|
|
cmd->dst = MSM_NAND_EBI2_ECC_BUF_CFG;
|
|
cmd->len = 4;
|
|
cmd++;
|
|
}
|
|
#endif
|
|
|
|
BUILD_BUG_ON(8 * 5 + 3 != ARRAY_SIZE(dma_buffer->cmd));
|
|
BUG_ON(cmd - dma_buffer->cmd > ARRAY_SIZE(dma_buffer->cmd));
|
|
dma_buffer->cmd[0].cmd |= CMD_OCB;
|
|
cmd[-1].cmd |= CMD_OCU | CMD_LC;
|
|
|
|
dma_buffer->cmdptr = (msm_virt_to_dma(chip, dma_buffer->cmd) >> 3) | CMD_PTR_LP;
|
|
|
|
dsb();
|
|
msm_dmov_exec_cmd(
|
|
chip->dma_channel, DMOV_CMD_PTR_LIST | DMOV_CMD_ADDR(
|
|
msm_virt_to_dma(chip, &dma_buffer->cmdptr)));
|
|
dsb();
|
|
|
|
/* if any of the writes failed (0x10), or there
|
|
* was a protection violation (0x100), we lose
|
|
*/
|
|
pageerr = rawerr = 0;
|
|
|
|
for (n = start_sector; n < cwperpage; n++)
|
|
{
|
|
if (dma_buffer->data.result[n].flash_status & 0x110)
|
|
{
|
|
rawerr = -EIO;
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (rawerr)
|
|
{
|
|
if (ops->datbuf)
|
|
{
|
|
uint8_t *datbuf = ops->datbuf + pages_read * mtd->writesize;
|
|
|
|
dma_sync_single_for_cpu(chip->dev,
|
|
data_dma_addr_curr-mtd->writesize,
|
|
mtd->writesize, DMA_BIDIRECTIONAL);
|
|
|
|
for (n = 0; n < mtd->writesize; n++)
|
|
{
|
|
if ((n % 512) == 0xF3 && datbuf[n] == 0x76)
|
|
{
|
|
datbuf[n] = 0xff;
|
|
}
|
|
if (datbuf[n] != 0xff)
|
|
{
|
|
pageerr = rawerr;
|
|
break;
|
|
}
|
|
}
|
|
|
|
dma_sync_single_for_device(chip->dev,
|
|
data_dma_addr_curr-mtd->writesize,
|
|
mtd->writesize, DMA_BIDIRECTIONAL);
|
|
|
|
}
|
|
if (ops->oobbuf)
|
|
{
|
|
for (n = 0; n < ops->ooblen; n++)
|
|
{
|
|
if (ops->oobbuf[n] != 0xff)
|
|
{
|
|
pageerr = rawerr;
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
if (pageerr)
|
|
{
|
|
for (n = start_sector; n < cwperpage; n++)
|
|
{
|
|
if (dma_buffer->data.result[n].buffer_status & 0x8)
|
|
{
|
|
/* not thread safe */
|
|
mtd->ecc_stats.failed++;
|
|
pageerr = -EBADMSG;
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
if (!rawerr)
|
|
{ /* check for corretable errors */
|
|
for (n = start_sector; n < cwperpage; n++)
|
|
{
|
|
ecc_errors = dma_buffer->data.
|
|
result[n].buffer_status & 0x7;
|
|
if (ecc_errors)
|
|
{
|
|
total_ecc_errors += ecc_errors;
|
|
/* not thread safe */
|
|
mtd->ecc_stats.corrected += ecc_errors;
|
|
if (ecc_errors > 1)
|
|
pageerr = -EUCLEAN;
|
|
}
|
|
}
|
|
}
|
|
if (pageerr && (pageerr != -EUCLEAN || err == 0))
|
|
err = pageerr;
|
|
|
|
#if VERBOSE
|
|
if (rawerr && !pageerr)
|
|
{
|
|
pr_err("msm_nand_read_oob %llx %x %x empty page\n", (loff_t)page * mtd->writesize, ops->len, ops->ooblen);
|
|
}
|
|
else
|
|
{
|
|
/* pr_info("status: %x %x %x %x %x %x %x %x %x \
|
|
%x %x %x %x %x %x %x \n",
|
|
dma_buffer->data.result[0].flash_status,
|
|
dma_buffer->data.result[0].buffer_status,
|
|
dma_buffer->data.result[1].flash_status,
|
|
dma_buffer->data.result[1].buffer_status,
|
|
dma_buffer->data.result[2].flash_status,
|
|
dma_buffer->data.result[2].buffer_status,
|
|
dma_buffer->data.result[3].flash_status,
|
|
dma_buffer->data.result[3].buffer_status,
|
|
dma_buffer->data.result[4].buffer_status,
|
|
dma_buffer->data.result[4].buffer_status,
|
|
dma_buffer->data.result[5].buffer_status,
|
|
dma_buffer->data.result[5].buffer_status,
|
|
dma_buffer->data.result[6].buffer_status,
|
|
dma_buffer->data.result[6].buffer_status,
|
|
dma_buffer->data.result[7].buffer_status,
|
|
dma_buffer->data.result[7].buffer_status); */
|
|
}
|
|
#endif
|
|
if (err && err != -EUCLEAN && err != -EBADMSG)
|
|
break;
|
|
pages_read++;
|
|
page++;
|
|
}
|
|
msm_nand_release_dma_buffer(chip, dma_buffer, sizeof(*dma_buffer));
|
|
|
|
if (ops->oobbuf)
|
|
{
|
|
dma_unmap_page(chip->dev, oob_dma_addr, ops->ooblen, DMA_FROM_DEVICE);
|
|
}
|
|
err_dma_map_oobbuf_failed:
|
|
if (ops->datbuf)
|
|
{
|
|
dma_unmap_page(chip->dev, data_dma_addr, ops->len, DMA_FROM_DEVICE);
|
|
}
|
|
|
|
#ifdef ENABLE_FLASH_RW_DUMP
|
|
// dump spare
|
|
if (ops->oobbuf && oob_done_size)
|
|
{
|
|
print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, ops->oobbuf, oob_done_size);
|
|
printk("\n");
|
|
}
|
|
|
|
if (ops->datbuf && ops->len)
|
|
{
|
|
print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, ops->datbuf, ops->len);
|
|
}
|
|
#endif
|
|
|
|
ops->retlen = mtd->writesize * pages_read;
|
|
ops->oobretlen = ops->ooblen - oob_len;
|
|
if (err)
|
|
pr_err("msm_nand_read_oob %llx %x %x failed %d, corrected %d\n",
|
|
from, ops->datbuf ? ops->len : 0, ops->ooblen, err, total_ecc_errors);
|
|
#ifdef ENABLE_ENTRY_TRACE
|
|
else
|
|
printk("-&&&nand_readoob&&&\n");
|
|
#endif
|
|
return err;
|
|
}
|
|
|
|
|
|
static int
|
|
msm_nand_read(struct mtd_info *mtd, loff_t from, size_t len,
|
|
size_t *retlen, u_char *buf)
|
|
{
|
|
int ret;
|
|
struct mtd_oob_ops ops;
|
|
|
|
/* printk("msm_nand_read %llx %x\n", from, len); */
|
|
|
|
#ifdef ENABLE_ENTRY_TRACE
|
|
printk("nand_read %d\n", len);
|
|
#endif
|
|
|
|
ops.mode = MTD_OOB_PLACE;
|
|
ops.len = len;
|
|
ops.retlen = 0;
|
|
ops.ooblen = 0;
|
|
ops.datbuf = buf;
|
|
ops.oobbuf = NULL;
|
|
ret = msm_nand_read_oob(mtd, from, &ops);
|
|
*retlen = ops.retlen;
|
|
return ret;
|
|
}
|
|
|
|
static int
|
|
msm_nand_write_oob(struct mtd_info *mtd, loff_t to, struct mtd_oob_ops *ops)
|
|
{
|
|
struct msm_nand_chip *chip = mtd->priv;
|
|
struct {
|
|
dmov_s cmd[8 * 6 + 3];
|
|
unsigned cmdptr;
|
|
struct {
|
|
uint32_t cmd;
|
|
uint32_t addr0;
|
|
uint32_t addr1;
|
|
uint32_t chipsel;
|
|
uint32_t cfg0;
|
|
uint32_t cfg1;
|
|
uint32_t exec;
|
|
#if SUPPORT_WRONG_ECC_CONFIG
|
|
uint32_t ecccfg;
|
|
uint32_t ecccfg_restore;
|
|
#endif
|
|
uint32_t flash_status[8];
|
|
uint32_t zeroes;
|
|
} data;
|
|
} *dma_buffer;
|
|
dmov_s *cmd;
|
|
unsigned n;
|
|
unsigned page = 0;
|
|
uint32_t oob_len;
|
|
uint32_t sectordatawritesize;
|
|
int err;
|
|
dma_addr_t data_dma_addr = 0;
|
|
dma_addr_t oob_dma_addr = 0;
|
|
dma_addr_t data_dma_addr_curr = 0;
|
|
dma_addr_t oob_dma_addr_curr = 0;
|
|
unsigned page_count;
|
|
unsigned pages_written = 0;
|
|
unsigned cwperpage;
|
|
|
|
#ifdef ENABLE_ENTRY_TRACE
|
|
printk("+&&&nand_writeoob&&&\n");
|
|
printk("msm_nand_write_oob [%d %08X] %08X %08X\n", (uint32_t)(to - 0x42c0000) / 0x800, (uint32_t)ops->len, (uint32_t)ops->datbuf, (uint32_t)ops
|
|
->oobbuf);
|
|
#endif
|
|
|
|
if (mtd->writesize == 2048)
|
|
page = to >> 11;
|
|
|
|
if (mtd->writesize == 4096)
|
|
page = to >> 12;
|
|
|
|
oob_len = ops->ooblen;
|
|
cwperpage = (mtd->writesize >> 9);
|
|
|
|
if (to & (mtd->writesize - 1))
|
|
{
|
|
pr_err("%s: unsupported to, 0x%llx\n", __func__, to);
|
|
return -EINVAL;
|
|
}
|
|
if (ops->ooblen != 0 && ops->mode != MTD_OOB_AUTO)
|
|
{
|
|
pr_err("%s: unsupported ops->mode, %d\n", __func__, ops->mode);
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (ops->datbuf == NULL)
|
|
{
|
|
pr_err("%s: unsupported ops->datbuf == NULL\n", __func__);
|
|
return -EINVAL;
|
|
}
|
|
if ((ops->len % mtd->writesize) != 0)
|
|
{
|
|
pr_err("%s: unsupported ops->len, %d\n", __func__, ops->len);
|
|
return -EINVAL;
|
|
}
|
|
|
|
|
|
#if 0 /* yaffs writes more oob data than it needs */
|
|
if (ops->ooblen >= sectoroobsize * 4) {
|
|
pr_err("%s: unsupported ops->ooblen, %d\n",
|
|
__func__, ops->ooblen);
|
|
return -EINVAL;
|
|
}
|
|
#endif
|
|
if (ops->ooblen != 0 && ops->ooboffs != 0)
|
|
{
|
|
pr_err("%s: unsupported ops->ooboffs, %d\n", __func__, ops->ooboffs);
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (ops->datbuf)
|
|
{
|
|
data_dma_addr_curr = data_dma_addr = msm_nand_dma_map(chip->dev, ops->datbuf, ops->len, DMA_TO_DEVICE);
|
|
if (dma_mapping_error(chip->dev, data_dma_addr))
|
|
{
|
|
pr_err("msm_nand_write_oob: failed to get dma addr for %p\n", ops->datbuf);
|
|
return -EIO;
|
|
}
|
|
}
|
|
if (ops->oobbuf)
|
|
{
|
|
oob_dma_addr_curr = oob_dma_addr = msm_nand_dma_map(chip->dev, ops->oobbuf, ops->ooblen, DMA_TO_DEVICE);
|
|
if (dma_mapping_error(chip->dev, oob_dma_addr))
|
|
{
|
|
pr_err("msm_nand_write_oob: failed to get dma addr for %p\n", ops->oobbuf);
|
|
err = -EIO;
|
|
goto err_dma_map_oobbuf_failed;
|
|
}
|
|
}
|
|
|
|
page_count = ops->len / mtd->writesize;
|
|
|
|
wait_event(chip->wait_queue, (dma_buffer = msm_nand_get_dma_buffer(chip, sizeof(*dma_buffer))));
|
|
|
|
while (page_count-- > 0)
|
|
{
|
|
cmd = dma_buffer->cmd;
|
|
|
|
/* CMD / ADDR0 / ADDR1 / CHIPSEL program values */
|
|
dma_buffer->data.cmd = MSM_NAND_CMD_PRG_PAGE_ALL; // MSM_NAND_CMD_PRG_PAGE;
|
|
dma_buffer->data.addr0 = page << 16;
|
|
dma_buffer->data.addr1 = (page >> 16) & 0xff;
|
|
dma_buffer->data.chipsel = 0 | 4; /* flash0 + undoc bit */
|
|
dma_buffer->data.zeroes = 0;
|
|
|
|
dma_buffer->data.cfg0 = chip->CFG0;
|
|
dma_buffer->data.cfg1 = chip->CFG1;
|
|
|
|
/* GO bit for the EXEC register */
|
|
dma_buffer->data.exec = 1;
|
|
|
|
BUILD_BUG_ON(8 != ARRAY_SIZE(dma_buffer->data.flash_status));
|
|
|
|
for (n = 0; n < cwperpage ; n++)
|
|
{
|
|
/* status return words */
|
|
dma_buffer->data.flash_status[n] = 0xeeeeeeee;
|
|
/* block on cmd ready, then
|
|
* write CMD / ADDR0 / ADDR1 / CHIPSEL regs in a burst
|
|
*/
|
|
cmd->cmd = DST_CRCI_NAND_CMD;
|
|
cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.cmd);
|
|
cmd->dst = MSM_NAND_FLASH_CMD;
|
|
if (n == 0)
|
|
cmd->len = 16;
|
|
else
|
|
cmd->len = 4;
|
|
cmd++;
|
|
|
|
if (n == 0)
|
|
{
|
|
cmd->cmd = 0;
|
|
cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.cfg0);
|
|
cmd->dst = MSM_NAND_DEV0_CFG0;
|
|
cmd->len = 8;
|
|
cmd++;
|
|
#if SUPPORT_WRONG_ECC_CONFIG
|
|
if (chip->saved_ecc_buf_cfg != chip->ecc_buf_cfg)
|
|
{
|
|
dma_buffer->data.ecccfg = chip->ecc_buf_cfg;
|
|
cmd->cmd = 0;
|
|
cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.ecccfg);
|
|
cmd->dst = MSM_NAND_EBI2_ECC_BUF_CFG;
|
|
cmd->len = 4;
|
|
cmd++;
|
|
}
|
|
#endif
|
|
}
|
|
|
|
/* write data block */ // Cotullazing
|
|
sectordatawritesize = 512; //(n < (cwperpage - 1)) ? 516 : (512 - ((cwperpage - 1) << 2));
|
|
cmd->cmd = 0;
|
|
cmd->src = data_dma_addr_curr;
|
|
data_dma_addr_curr += sectordatawritesize;
|
|
cmd->dst = MSM_NAND_FLASH_BUFFER;
|
|
cmd->len = sectordatawritesize;
|
|
cmd++;
|
|
|
|
if (ops->oobbuf)
|
|
{
|
|
cmd->cmd = 0;
|
|
cmd->src = oob_dma_addr_curr;
|
|
cmd->dst = MSM_NAND_FLASH_BUFFER + 512;
|
|
if (oob_len > 4)
|
|
cmd->len = 4;
|
|
else
|
|
cmd->len = oob_len;
|
|
oob_dma_addr_curr += cmd->len;
|
|
oob_len -= cmd->len;
|
|
//printk("OOB: %d %d\n", cmd->len, oob_len);
|
|
if (cmd->len > 0)
|
|
cmd++;
|
|
}
|
|
|
|
/* kick the execute register */
|
|
cmd->cmd = 0;
|
|
cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.exec);
|
|
cmd->dst = MSM_NAND_EXEC_CMD;
|
|
cmd->len = 4;
|
|
cmd++;
|
|
|
|
/* block on data ready, then
|
|
* read the status register
|
|
*/
|
|
cmd->cmd = SRC_CRCI_NAND_DATA;
|
|
cmd->src = MSM_NAND_FLASH_STATUS;
|
|
cmd->dst = msm_virt_to_dma(chip, &dma_buffer->data.flash_status[n]);
|
|
cmd->len = 4;
|
|
cmd++;
|
|
|
|
/* clear the status register in case the OP_ERR is set
|
|
* due to the write, to work around a h/w bug */
|
|
cmd->cmd = 0;
|
|
cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.zeroes);
|
|
cmd->dst = MSM_NAND_FLASH_STATUS;
|
|
cmd->len = 4;
|
|
cmd++;
|
|
}
|
|
#if SUPPORT_WRONG_ECC_CONFIG
|
|
if (chip->saved_ecc_buf_cfg != chip->ecc_buf_cfg)
|
|
{
|
|
dma_buffer->data.ecccfg_restore = chip->saved_ecc_buf_cfg;
|
|
cmd->cmd = 0;
|
|
cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.ecccfg_restore);
|
|
cmd->dst = MSM_NAND_EBI2_ECC_BUF_CFG;
|
|
cmd->len = 4;
|
|
cmd++;
|
|
}
|
|
#endif
|
|
dma_buffer->cmd[0].cmd |= CMD_OCB;
|
|
cmd[-1].cmd |= CMD_OCU | CMD_LC;
|
|
BUILD_BUG_ON(8 * 6 + 3 != ARRAY_SIZE(dma_buffer->cmd));
|
|
BUG_ON(cmd - dma_buffer->cmd > ARRAY_SIZE(dma_buffer->cmd));
|
|
dma_buffer->cmdptr = (msm_virt_to_dma(chip, dma_buffer->cmd) >> 3) | CMD_PTR_LP;
|
|
|
|
dsb();
|
|
msm_dmov_exec_cmd(chip->dma_channel, DMOV_CMD_PTR_LIST | DMOV_CMD_ADDR(msm_virt_to_dma(chip, &dma_buffer->cmdptr)));
|
|
dsb();
|
|
|
|
/* if any of the writes failed (0x10), or there was a
|
|
* protection violation (0x100), or the program success
|
|
* bit (0x80) is unset, we lose
|
|
*/
|
|
err = 0;
|
|
for (n = 0; n < cwperpage; n++)
|
|
{
|
|
if (dma_buffer->data.flash_status[n] & 0x110)
|
|
{
|
|
if (dma_buffer->data.flash_status[n] & 0x10)
|
|
pr_err("msm_nand: critical write error, 0x%x(%d)\n", page, n);
|
|
err = -EIO;
|
|
break;
|
|
}
|
|
if (!(dma_buffer->data.flash_status[n] & 0x80))
|
|
{
|
|
err = -EIO;
|
|
break;
|
|
}
|
|
}
|
|
|
|
#if VERBOSE
|
|
/* pr_info("write page %d: status: %x %x %x %x %x %x %x %x\n", page,
|
|
dma_buffer->data.flash_status[0],
|
|
dma_buffer->data.flash_status[1],
|
|
dma_buffer->data.flash_status[2],
|
|
dma_buffer->data.flash_status[3],
|
|
dma_buffer->data.flash_status[4],
|
|
dma_buffer->data.flash_status[5],
|
|
dma_buffer->data.flash_status[6],
|
|
dma_buffer->data.flash_status[7]); */
|
|
#endif
|
|
if (err)
|
|
break;
|
|
pages_written++;
|
|
page++;
|
|
}
|
|
ops->retlen = mtd->writesize * pages_written;
|
|
ops->oobretlen = ops->ooblen - oob_len;
|
|
|
|
msm_nand_release_dma_buffer(chip, dma_buffer, sizeof(*dma_buffer));
|
|
|
|
if (ops->oobbuf)
|
|
dma_unmap_page(chip->dev, oob_dma_addr, ops->ooblen, DMA_TO_DEVICE);
|
|
err_dma_map_oobbuf_failed:
|
|
if (ops->datbuf)
|
|
dma_unmap_page(chip->dev, data_dma_addr, ops->len, DMA_TO_DEVICE);
|
|
|
|
#ifdef ENABLE_FLASH_RW_DUMP
|
|
// dump spare
|
|
if (ops->oobbuf && 16)
|
|
{
|
|
print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, ops->oobbuf, 16);
|
|
printk("\n");
|
|
}
|
|
|
|
if (ops->datbuf && ops->len)
|
|
{
|
|
print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, ops->datbuf, ops->len);
|
|
}
|
|
#endif
|
|
|
|
if (err)
|
|
pr_err("msm_nand_write_oob %llx %x %x failed %d\n", to, ops->len, ops->ooblen, err);
|
|
#ifdef ENABLE_ENTRY_TRACE
|
|
else
|
|
printk("-&&&nand_writeoob&&&\n");
|
|
#endif
|
|
return err;
|
|
}
|
|
|
|
static int msm_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
|
|
size_t *retlen, const u_char *buf)
|
|
{
|
|
int ret;
|
|
struct mtd_oob_ops ops;
|
|
|
|
#ifdef ENABLE_ENTRY_TRACE
|
|
printk("nand_write\n");
|
|
#endif
|
|
ops.mode = MTD_OOB_PLACE;
|
|
ops.len = len;
|
|
ops.retlen = 0;
|
|
ops.ooblen = 0;
|
|
ops.datbuf = (uint8_t *)buf;
|
|
ops.oobbuf = NULL;
|
|
ret = msm_nand_write_oob(mtd, to, &ops);
|
|
*retlen = ops.retlen;
|
|
return ret;
|
|
}
|
|
|
|
static int
|
|
msm_nand_erase(struct mtd_info *mtd, struct erase_info *instr)
|
|
{
|
|
int err;
|
|
struct msm_nand_chip *chip = mtd->priv;
|
|
struct {
|
|
dmov_s cmd[5];
|
|
unsigned cmdptr;
|
|
unsigned data[9];
|
|
} *dma_buffer;
|
|
unsigned page = 0;
|
|
|
|
|
|
if (mtd->writesize == 2048)
|
|
page = instr->addr >> 11;
|
|
|
|
if (mtd->writesize == 4096)
|
|
page = instr->addr >> 12;
|
|
|
|
printk("nand_erase(%d)\n", page);
|
|
|
|
if (instr->addr & (mtd->erasesize - 1)) {
|
|
pr_err("%s: unsupported erase address, 0x%llx\n",
|
|
__func__, instr->addr);
|
|
return -EINVAL;
|
|
}
|
|
if (instr->len != mtd->erasesize) {
|
|
pr_err("%s: unsupported erase len, %lld\n",
|
|
__func__, instr->len);
|
|
return -EINVAL;
|
|
}
|
|
|
|
wait_event(chip->wait_queue,
|
|
(dma_buffer = msm_nand_get_dma_buffer(
|
|
chip, sizeof(*dma_buffer))));
|
|
|
|
dma_buffer->data[0] = MSM_NAND_CMD_BLOCK_ERASE;
|
|
dma_buffer->data[1] = page;
|
|
dma_buffer->data[2] = 0;
|
|
dma_buffer->data[3] = 0 | 4;
|
|
dma_buffer->data[4] = 1;
|
|
dma_buffer->data[5] = 0xeeeeeeee;
|
|
dma_buffer->data[6] = chip->CFG0 & (~(7 << 6)); /* CW_PER_PAGE = 0 */
|
|
dma_buffer->data[7] = chip->CFG1;
|
|
dma_buffer->data[8] = 0;
|
|
BUILD_BUG_ON(8 != ARRAY_SIZE(dma_buffer->data) - 1);
|
|
|
|
dma_buffer->cmd[0].cmd = DST_CRCI_NAND_CMD | CMD_OCB;
|
|
dma_buffer->cmd[0].src = msm_virt_to_dma(chip, &dma_buffer->data[0]);
|
|
dma_buffer->cmd[0].dst = MSM_NAND_FLASH_CMD;
|
|
dma_buffer->cmd[0].len = 16;
|
|
|
|
dma_buffer->cmd[1].cmd = 0;
|
|
dma_buffer->cmd[1].src = msm_virt_to_dma(chip, &dma_buffer->data[6]);
|
|
dma_buffer->cmd[1].dst = MSM_NAND_DEV0_CFG0;
|
|
dma_buffer->cmd[1].len = 8;
|
|
|
|
dma_buffer->cmd[2].cmd = 0;
|
|
dma_buffer->cmd[2].src = msm_virt_to_dma(chip, &dma_buffer->data[4]);
|
|
dma_buffer->cmd[2].dst = MSM_NAND_EXEC_CMD;
|
|
dma_buffer->cmd[2].len = 4;
|
|
|
|
dma_buffer->cmd[3].cmd = SRC_CRCI_NAND_DATA;
|
|
dma_buffer->cmd[3].src = MSM_NAND_FLASH_STATUS;
|
|
dma_buffer->cmd[3].dst = msm_virt_to_dma(chip, &dma_buffer->data[5]);
|
|
dma_buffer->cmd[3].len = 4;
|
|
|
|
/* clear the status register in case the OP_ERR is set
|
|
* due to the write, to work around a h/w bug */
|
|
dma_buffer->cmd[4].cmd = CMD_OCU | CMD_LC;
|
|
dma_buffer->cmd[4].src = msm_virt_to_dma(chip, &dma_buffer->data[8]);
|
|
dma_buffer->cmd[4].dst = MSM_NAND_FLASH_STATUS;
|
|
dma_buffer->cmd[4].len = 4;
|
|
|
|
BUILD_BUG_ON(4 != ARRAY_SIZE(dma_buffer->cmd) - 1);
|
|
dma_buffer->cmdptr =
|
|
(msm_virt_to_dma(chip, dma_buffer->cmd) >> 3) | CMD_PTR_LP;
|
|
|
|
dsb();
|
|
msm_dmov_exec_cmd(
|
|
chip->dma_channel, DMOV_CMD_PTR_LIST |
|
|
DMOV_CMD_ADDR(msm_virt_to_dma(chip, &dma_buffer->cmdptr)));
|
|
dsb();
|
|
|
|
/* we fail if there was an operation error, a mpu error, or the
|
|
* erase success bit was not set.
|
|
*/
|
|
|
|
if (dma_buffer->data[5] & 0x110 || !(dma_buffer->data[5] & 0x80)) {
|
|
if (dma_buffer->data[5] & 0x10)
|
|
pr_warning("msm_nand: critical erase error, 0x%llx\n",
|
|
instr->addr);
|
|
err = -EIO;
|
|
} else
|
|
err = 0;
|
|
|
|
msm_nand_release_dma_buffer(chip, dma_buffer, sizeof(*dma_buffer));
|
|
if (err) {
|
|
pr_err("%s: erase failed, 0x%llx\n", __func__, instr->addr);
|
|
instr->fail_addr = instr->addr;
|
|
instr->state = MTD_ERASE_FAILED;
|
|
} else {
|
|
instr->state = MTD_ERASE_DONE;
|
|
instr->fail_addr = 0xffffffff;
|
|
mtd_erase_callback(instr);
|
|
}
|
|
return err;
|
|
}
|
|
|
|
static int
|
|
msm_nand_block_isbad(struct mtd_info *mtd, loff_t ofs)
|
|
{
|
|
struct msm_nand_chip *chip = mtd->priv;
|
|
int ret;
|
|
struct {
|
|
dmov_s cmd[5];
|
|
unsigned cmdptr;
|
|
struct {
|
|
uint32_t cmd;
|
|
uint32_t addr0;
|
|
uint32_t addr1;
|
|
uint32_t chipsel;
|
|
uint32_t cfg0;
|
|
uint32_t cfg1;
|
|
uint32_t exec;
|
|
uint32_t ecccfg;
|
|
struct {
|
|
uint32_t flash_status;
|
|
uint32_t buffer_status;
|
|
} result;
|
|
} data;
|
|
} *dma_buffer;
|
|
dmov_s *cmd;
|
|
uint8_t *buf;
|
|
unsigned page = 0;
|
|
unsigned cwperpage;
|
|
|
|
#ifdef ENABLE_ENTRY_TRACE
|
|
printk("+nand_block_isbad\n");
|
|
#endif
|
|
if (mtd->writesize == 2048)
|
|
page = ofs >> 11;
|
|
|
|
if (mtd->writesize == 4096)
|
|
page = ofs >> 12;
|
|
|
|
cwperpage = (mtd->writesize >> 9);
|
|
|
|
/* Check for invalid offset */
|
|
if (ofs > mtd->size)
|
|
return -EINVAL;
|
|
if (ofs & (mtd->erasesize - 1))
|
|
{
|
|
pr_err("%s: unsupported block address, 0x%x\n", __func__, (uint32_t)ofs);
|
|
return -EINVAL;
|
|
}
|
|
|
|
wait_event(chip->wait_queue,
|
|
(dma_buffer = msm_nand_get_dma_buffer(chip ,
|
|
sizeof(*dma_buffer) + 4)));
|
|
buf = (uint8_t *)dma_buffer + sizeof(*dma_buffer);
|
|
|
|
/* Read 4 bytes starting from the bad block marker location
|
|
* in the last code word of the page
|
|
*/
|
|
|
|
cmd = dma_buffer->cmd;
|
|
|
|
dma_buffer->data.cmd = MSM_NAND_CMD_PAGE_READ;
|
|
dma_buffer->data.cfg0 = MSM_NAND_CFG0_RAW & ~(7U << 6);
|
|
// ecc disabled
|
|
dma_buffer->data.cfg1 = MSM_NAND_CFG1_RAW | (chip->CFG1 & CFG1_WIDE_FLASH);
|
|
|
|
if (chip->CFG1 & CFG1_WIDE_FLASH)
|
|
dma_buffer->data.addr0 = (page << 16) | ((528*(cwperpage-1)) >> 1);
|
|
else
|
|
dma_buffer->data.addr0 = (page << 16) | (528*(cwperpage-1));
|
|
|
|
dma_buffer->data.addr1 = (page >> 16) & 0xff;
|
|
dma_buffer->data.chipsel = 0 | 4;
|
|
|
|
dma_buffer->data.exec = 1;
|
|
|
|
dma_buffer->data.result.flash_status = 0xeeeeeeee;
|
|
dma_buffer->data.result.buffer_status = 0xeeeeeeee;
|
|
|
|
cmd->cmd = DST_CRCI_NAND_CMD;
|
|
cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.cmd);
|
|
cmd->dst = MSM_NAND_FLASH_CMD;
|
|
cmd->len = 16;
|
|
cmd++;
|
|
|
|
cmd->cmd = 0;
|
|
cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.cfg0);
|
|
cmd->dst = MSM_NAND_DEV0_CFG0;
|
|
cmd->len = 8;
|
|
cmd++;
|
|
|
|
cmd->cmd = 0;
|
|
cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.exec);
|
|
cmd->dst = MSM_NAND_EXEC_CMD;
|
|
cmd->len = 4;
|
|
cmd++;
|
|
|
|
cmd->cmd = SRC_CRCI_NAND_DATA;
|
|
cmd->src = MSM_NAND_FLASH_STATUS;
|
|
cmd->dst = msm_virt_to_dma(chip, &dma_buffer->data.result);
|
|
cmd->len = 8;
|
|
cmd++;
|
|
|
|
cmd->cmd = 0;
|
|
cmd->src = MSM_NAND_FLASH_BUFFER + (mtd->writesize - (528*(cwperpage-1)));
|
|
cmd->dst = msm_virt_to_dma(chip, buf);
|
|
cmd->len = 4;
|
|
cmd++;
|
|
|
|
BUILD_BUG_ON(5 != ARRAY_SIZE(dma_buffer->cmd));
|
|
BUG_ON(cmd - dma_buffer->cmd > ARRAY_SIZE(dma_buffer->cmd));
|
|
dma_buffer->cmd[0].cmd |= CMD_OCB;
|
|
cmd[-1].cmd |= CMD_OCU | CMD_LC;
|
|
|
|
dma_buffer->cmdptr = (msm_virt_to_dma(chip,
|
|
dma_buffer->cmd) >> 3) | CMD_PTR_LP;
|
|
|
|
dsb();
|
|
msm_dmov_exec_cmd(chip->dma_channel, DMOV_CMD_PTR_LIST | DMOV_CMD_ADDR(msm_virt_to_dma(chip, &dma_buffer->cmdptr)));
|
|
dsb();
|
|
|
|
ret = 0;
|
|
if (dma_buffer->data.result.flash_status & 0x110)
|
|
ret = -EIO;
|
|
|
|
if (!ret)
|
|
{
|
|
/* Check for bad block marker byte */
|
|
if (chip->CFG1 & CFG1_WIDE_FLASH)
|
|
{
|
|
if (buf[0] != 0xFF || buf[1] != 0xFF)
|
|
{
|
|
ret = 1;
|
|
printk("###BAD BLOCK [%08X] %08X###\n", (uint32_t)(ofs - 0x42c0000) / 0x800, (uint32_t)ofs);
|
|
}
|
|
}
|
|
else
|
|
{
|
|
if (buf[0] != 0xFF)
|
|
ret = 1;
|
|
}
|
|
}
|
|
|
|
msm_nand_release_dma_buffer(chip, dma_buffer, sizeof(*dma_buffer) + 4);
|
|
#ifdef ENABLE_ENTRY_TRACE
|
|
printk("-nand_block_isbad %d\n", ret);
|
|
#endif
|
|
return ret;
|
|
}
|
|
|
|
|
|
static int
|
|
msm_nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
|
|
{
|
|
/* struct msm_nand_chip *this = mtd->priv; */
|
|
int ret;
|
|
|
|
ret = msm_nand_block_isbad(mtd, ofs);
|
|
if (ret) {
|
|
/* If it was bad already, return success and do nothing */
|
|
if (ret > 0)
|
|
return 0;
|
|
return ret;
|
|
}
|
|
|
|
return -EIO;
|
|
}
|
|
|
|
/**
|
|
* msm_nand_suspend - [MTD Interface] Suspend the msm_nand flash
|
|
* @param mtd MTD device structure
|
|
*/
|
|
static int msm_nand_suspend(struct mtd_info *mtd)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* msm_nand_resume - [MTD Interface] Resume the msm_nand flash
|
|
* @param mtd MTD device structure
|
|
*/
|
|
static void msm_nand_resume(struct mtd_info *mtd)
|
|
{
|
|
}
|
|
|
|
/**
|
|
* Export 3 attributes for HTC SSD HW INFO tool
|
|
* >info :basic HW spec of this NAND chip
|
|
* >vendor :vendor information
|
|
* >pagesize:page size, either 2048 or 4096
|
|
*/
|
|
static int param_get_vendor_name(char *buffer, struct kernel_param *kp)
|
|
{
|
|
return sprintf(buffer, "%s", nand_info->maker_name);
|
|
}
|
|
module_param_call(vendor, NULL, param_get_vendor_name, NULL, S_IRUGO);
|
|
|
|
static int param_get_nand_info(char *buffer, struct kernel_param *kp)
|
|
{
|
|
int result = 0;
|
|
result += sprintf(buffer, "<< NAND INFO >>\n");
|
|
result += sprintf(buffer + result, "flash id\t =%X\n",
|
|
nand_info->flash_id);
|
|
result += sprintf(buffer + result, "vendor\t\t =%s\n",
|
|
nand_info->maker_name);
|
|
result += sprintf(buffer + result, "width\t\t =%d bits\n",
|
|
nand_info->width);
|
|
result += sprintf(buffer + result, "size\t\t =%d MB\n",
|
|
nand_info->size>>20);
|
|
result += sprintf(buffer + result, "block count\t =%d\n",
|
|
nand_info->block_count);
|
|
result += sprintf(buffer + result, "page count\t =%d",
|
|
nand_info->page_count);
|
|
return result;
|
|
}
|
|
module_param_call(info, NULL, param_get_nand_info, NULL, S_IRUGO);
|
|
|
|
static int param_get_page_size(char *buffer, struct kernel_param *kp)
|
|
{
|
|
return sprintf(buffer, "%d", nand_info->page_size);
|
|
}
|
|
module_param_call(pagesize, NULL, param_get_page_size, NULL, S_IRUGO);
|
|
|
|
/**
|
|
* msm_nand_scan - [msm_nand Interface] Scan for the msm_nand device
|
|
* @param mtd MTD device structure
|
|
* @param maxchips Number of chips to scan for
|
|
*
|
|
* This fills out all the not initialized function pointers
|
|
* with the defaults.
|
|
* The flash ID is read and the mtd/chip structures are
|
|
* filled with the appropriate values.
|
|
*/
|
|
int msm_nand_scan(struct mtd_info *mtd, int maxchips)
|
|
{
|
|
unsigned n;
|
|
struct msm_nand_chip *chip = mtd->priv;
|
|
uint32_t flash_id = 0, i = 1, mtd_writesize;
|
|
uint8_t dev_found = 0;
|
|
uint8_t wide_bus;
|
|
uint8_t index;
|
|
|
|
/* Read the Flash ID from the Nand Flash Device */
|
|
flash_id = flash_read_id(chip);
|
|
for (index = 1; index < ARRAY_SIZE(supported_flash); index++) {
|
|
if ((flash_id & supported_flash[index].mask) ==
|
|
(supported_flash[index].flash_id &
|
|
(supported_flash[index].mask))) {
|
|
dev_found = 1;
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (dev_found)
|
|
{
|
|
wide_bus = supported_flash[index].widebus;
|
|
mtd->size = supported_flash[index].density * i;
|
|
mtd->writesize = supported_flash[index].pagesize * i;
|
|
mtd->oobsize = supported_flash[index].oobsize * i;
|
|
mtd->erasesize = supported_flash[index].blksize * i;
|
|
mtd_writesize = mtd->writesize;
|
|
|
|
pr_info("Found a supported NAND device\n");
|
|
pr_info("NAND Id : 0x%X\n", supported_flash[index].
|
|
flash_id);
|
|
pr_info("Buswidth : %d Bits \n", (wide_bus) ? 16 : 8);
|
|
pr_info("Density : %lld MByte\n", (mtd->size>>20));
|
|
pr_info("Pagesize : %d Bytes\n", mtd->writesize);
|
|
pr_info("Erasesize: %d Bytes\n", mtd->erasesize);
|
|
pr_info("Oobsize : %d Bytes\n", mtd->oobsize);
|
|
} else {
|
|
pr_err("Unsupported Nand,Id: 0x%x \n", flash_id);
|
|
return -ENODEV;
|
|
}
|
|
|
|
|
|
if (mtd->writesize != 2048)
|
|
{
|
|
pr_err("ERROR: unsupported flash parameters!\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
if (flash_read_config(chip))
|
|
{
|
|
pr_err("ERROR: could not save CFG0 & CFG1 state\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
pr_info("CFG0 Old: 0x%08x \n", chip->CFG0);
|
|
pr_info("CFG1 Old: 0x%08x \n", chip->CFG1);
|
|
|
|
chip->CFG0 = (((mtd->writesize >> 9)-1) << 6) /* 4/8 cw/per page for 2/4k */
|
|
| (512 << 9) /* 512 user data bytes */
|
|
| (10 << 19) /* 10 parity bytes */
|
|
| (4 << 23) /* spare size */
|
|
| (5 << 27) /* 5 address cycles */
|
|
| (1 << 30) /* Read status before data */
|
|
| (1 << 31) /* Send read cmd */
|
|
| 0;
|
|
chip->CFG1 = chip->CFG1
|
|
#if IGNORE_ARM9_CONFIG
|
|
/* use ARM11 own setting on CFG1 */
|
|
| (7 << 2) /* 8 recovery cycles */
|
|
| (0 << 5) /* Allow CS deassertion */
|
|
| (2 << 17) /* 6 cycle tWB/tRB */
|
|
#endif
|
|
| ((mtd->writesize - (528 * ((mtd->writesize >> 9) - 1)) + 1) << 6) /* Bad block marker location */
|
|
| (wide_bus << 1); /* Wide flash bit */
|
|
chip->CFG1 = chip->CFG1
|
|
& ~(1 << 0) /* Enable ecc */
|
|
& ~(1 << 16); /* Bad block in user data area */
|
|
|
|
pr_info("CFG0 Init : 0x%08x \n", chip->CFG0);
|
|
pr_info("CFG1 Init : 0x%08x \n", chip->CFG1);
|
|
pr_info("CFG0: cw/page=%d ud_sz=%d ecc_sz=%d spare_sz=%d "
|
|
"num_addr_cycles=%d\n", (chip->CFG0 >> 6) & 7,
|
|
(chip->CFG0 >> 9) & 0x3ff, (chip->CFG0 >> 19) & 15,
|
|
(chip->CFG0 >> 23) & 15, (chip->CFG0 >> 27) & 7);
|
|
|
|
n = flash_rd_reg(chip, MSM_NAND_DEV_CMD1);
|
|
pr_info("DEV_CMD1: %x\n", n);
|
|
|
|
n = flash_rd_reg(chip, MSM_NAND_EBI2_ECC_BUF_CFG);
|
|
pr_info(KERN_INFO "NAND_EBI2_ECC_BUF_CFG: %x\n", n);
|
|
|
|
#if SUPPORT_WRONG_ECC_CONFIG
|
|
chip->ecc_buf_cfg = 0x1FF;
|
|
chip->saved_ecc_buf_cfg = n;
|
|
#endif
|
|
|
|
if (mtd->oobsize == 64)
|
|
{
|
|
mtd->oobavail = msm_nand_oob_64.oobavail;
|
|
mtd->ecclayout = &msm_nand_oob_64;
|
|
}
|
|
else
|
|
{
|
|
pr_err("Unsupported Nand, oobsize: 0x%x \n",
|
|
mtd->oobsize);
|
|
return -ENODEV;
|
|
}
|
|
|
|
/* Fill in remaining MTD driver data */
|
|
mtd->type = MTD_NANDFLASH;
|
|
mtd->flags = MTD_CAP_NANDFLASH;
|
|
/* mtd->ecctype = MTD_ECC_SW; */
|
|
mtd->erase = msm_nand_erase;
|
|
mtd->point = NULL;
|
|
mtd->unpoint = NULL;
|
|
mtd->read = msm_nand_read;
|
|
mtd->write = msm_nand_write;
|
|
mtd->read_oob = msm_nand_read_oob;
|
|
mtd->write_oob = msm_nand_write_oob;
|
|
/* mtd->sync = msm_nand_sync; */
|
|
mtd->lock = NULL;
|
|
/* mtd->unlock = msm_nand_unlock; */
|
|
mtd->suspend = msm_nand_suspend;
|
|
mtd->resume = msm_nand_resume;
|
|
mtd->block_isbad = msm_nand_block_isbad;
|
|
mtd->block_markbad = msm_nand_block_markbad;
|
|
mtd->owner = THIS_MODULE;
|
|
|
|
/* Information provides to HTC SSD HW Info tool */
|
|
nand_info = &chip->dev_info;
|
|
nand_info->flash_id = flash_id;
|
|
nand_info->maker_id = (flash_id & 0xff);
|
|
switch (nand_info->maker_id)
|
|
{
|
|
case 0xec:
|
|
strcpy(nand_info->maker_name, "Samsung");
|
|
break;
|
|
case 0xad:
|
|
strcpy(nand_info->maker_name, "Hynix");
|
|
break;
|
|
case 0x2c:
|
|
strcpy(nand_info->maker_name, "Micron");
|
|
break;
|
|
default:
|
|
strcpy(nand_info->maker_name, "Unknown");
|
|
break;
|
|
}
|
|
nand_info->width = (wide_bus? 16: 8);
|
|
nand_info->size = mtd->size;
|
|
nand_info->page_size = mtd->writesize;
|
|
nand_info->page_count = mtd->erasesize/mtd->writesize;
|
|
nand_info->block_count = mtd->size;
|
|
do_div(nand_info->block_count, nand_info->page_size * nand_info->page_count);
|
|
|
|
/* Unlock whole block */
|
|
/* msm_nand_unlock_all(mtd); */
|
|
|
|
/* return this->scan_bbt(mtd); */
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL_GPL(msm_nand_scan);
|
|
|
|
/**
|
|
* msm_nand_release - [msm_nand Interface] Free resources held by the msm_nand device
|
|
* @param mtd MTD device structure
|
|
*/
|
|
void msm_nand_release(struct mtd_info *mtd)
|
|
{
|
|
/* struct msm_nand_chip *this = mtd->priv; */
|
|
|
|
#ifdef CONFIG_MTD_PARTITIONS
|
|
/* Deregister partitions */
|
|
del_mtd_partitions(mtd);
|
|
#endif
|
|
/* Deregister the device */
|
|
del_mtd_device(mtd);
|
|
}
|
|
EXPORT_SYMBOL_GPL(msm_nand_release);
|
|
|
|
#ifdef CONFIG_MTD_PARTITIONS
|
|
static const char *part_probes[] = { "cmdlinepart", NULL, };
|
|
#endif
|
|
|
|
struct msm_nand_info {
|
|
struct mtd_info mtd;
|
|
struct mtd_partition *parts;
|
|
struct msm_nand_chip msm_nand;
|
|
};
|
|
|
|
static int __devinit msm_nand_probe(struct platform_device *pdev)
|
|
{
|
|
struct msm_nand_info *info;
|
|
struct flash_platform_data *pdata = pdev->dev.platform_data;
|
|
int err, i;
|
|
|
|
if (pdev->num_resources != 1) {
|
|
pr_err("invalid num_resources");
|
|
return -ENODEV;
|
|
}
|
|
if (pdev->resource[0].flags != IORESOURCE_DMA) {
|
|
pr_err("invalid resource type");
|
|
return -ENODEV;
|
|
}
|
|
|
|
info = kzalloc(sizeof(struct msm_nand_info), GFP_KERNEL);
|
|
if (!info)
|
|
return -ENOMEM;
|
|
|
|
info->msm_nand.dev = &pdev->dev;
|
|
|
|
init_waitqueue_head(&info->msm_nand.wait_queue);
|
|
|
|
info->msm_nand.dma_channel = pdev->resource[0].start;
|
|
/* this currently fails if dev is passed in */
|
|
info->msm_nand.dma_buffer =
|
|
dma_alloc_coherent(/*dev*/ NULL, MSM_NAND_DMA_BUFFER_SIZE,
|
|
&info->msm_nand.dma_addr, GFP_KERNEL);
|
|
if (info->msm_nand.dma_buffer == NULL) {
|
|
err = -ENOMEM;
|
|
goto out_free_info;
|
|
}
|
|
|
|
pr_info("msm_nand: allocated dma buffer at %p, dma_addr %x\n",
|
|
info->msm_nand.dma_buffer, info->msm_nand.dma_addr);
|
|
|
|
info->mtd.name = dev_name(&pdev->dev);
|
|
info->mtd.priv = &info->msm_nand;
|
|
info->mtd.owner = THIS_MODULE;
|
|
|
|
if (msm_nand_scan(&info->mtd, 1)) {
|
|
err = -ENXIO;
|
|
goto out_free_dma_buffer;
|
|
}
|
|
|
|
printk("#MTD# parts in atag = %d\n", pdata->nr_parts);
|
|
|
|
#ifdef CONFIG_MTD_PARTITIONS
|
|
/* Re-calculate the partition offset and size with correct page size */
|
|
for (i = 0; i < pdata->nr_parts; i++)
|
|
{
|
|
pdata->parts[i].offset = pdata->parts[i].offset * info->mtd.erasesize;
|
|
pdata->parts[i].size = pdata->parts[i].size * info->mtd.erasesize;
|
|
}
|
|
|
|
err = parse_mtd_partitions(&info->mtd, part_probes, &info->parts, 0);
|
|
if (err > 0)
|
|
add_mtd_partitions(&info->mtd, info->parts, err);
|
|
else if (err <= 0 && pdata && pdata->parts)
|
|
add_mtd_partitions(&info->mtd, pdata->parts, pdata->nr_parts);
|
|
else
|
|
#endif
|
|
err = add_mtd_device(&info->mtd);
|
|
|
|
dev_set_drvdata(&pdev->dev, info);
|
|
|
|
return 0;
|
|
|
|
out_free_dma_buffer:
|
|
dma_free_coherent(/*dev*/ NULL, SZ_4K, info->msm_nand.dma_buffer, info->msm_nand.dma_addr);
|
|
out_free_info:
|
|
kfree(info);
|
|
|
|
return err;
|
|
}
|
|
|
|
static int __devexit msm_nand_remove(struct platform_device *pdev)
|
|
{
|
|
struct msm_nand_info *info = dev_get_drvdata(&pdev->dev);
|
|
|
|
dev_set_drvdata(&pdev->dev, NULL);
|
|
|
|
if (info) {
|
|
#ifdef CONFIG_MTD_PARTITIONS
|
|
if (info->parts)
|
|
del_mtd_partitions(&info->mtd);
|
|
else
|
|
#endif
|
|
del_mtd_device(&info->mtd);
|
|
|
|
msm_nand_release(&info->mtd);
|
|
dma_free_coherent(/*dev*/ NULL, SZ_4K,
|
|
info->msm_nand.dma_buffer,
|
|
info->msm_nand.dma_addr);
|
|
kfree(info);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
#define DRIVER_NAME "msm_nand"
|
|
|
|
static struct platform_driver msm_nand_driver = {
|
|
.probe = msm_nand_probe,
|
|
.remove = __devexit_p(msm_nand_remove),
|
|
.driver = {
|
|
.name = DRIVER_NAME,
|
|
}
|
|
};
|
|
|
|
MODULE_ALIAS(DRIVER_NAME);
|
|
|
|
static int __init msm_nand_init(void)
|
|
{
|
|
return platform_driver_register(&msm_nand_driver);
|
|
}
|
|
|
|
static void __exit msm_nand_exit(void)
|
|
{
|
|
platform_driver_unregister(&msm_nand_driver);
|
|
}
|
|
|
|
module_init(msm_nand_init);
|
|
module_exit(msm_nand_exit);
|
|
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_DESCRIPTION("htcleo nand driver code");
|
|
|
|
|